From 5c24c98880f3f01bcd80c0b05a4140ddb227218f Mon Sep 17 00:00:00 2001
From: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Date: Tue, 23 Feb 2021 20:50:56 -0300
Subject: [PATCH] risc-v/esp32c3: Invalidate CPU interrupt number after free

---
 arch/risc-v/src/esp32c3/esp32c3_wdt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/risc-v/src/esp32c3/esp32c3_wdt.c b/arch/risc-v/src/esp32c3/esp32c3_wdt.c
index 02aae402f3..8c9f4f2b0e 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_wdt.c
+++ b/arch/risc-v/src/esp32c3/esp32c3_wdt.c
@@ -668,6 +668,7 @@ static int32_t esp32c3_wdt_setisr(struct esp32c3_wdt_dev_s *dev,
           up_disable_irq(wdt->cpuint);
           irq_detach(wdt->irq);
           esp32c3_free_cpuint(wdt->periph);
+          wdt->cpuint = -ENOMEM;
         }
     }