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arch/arm/src/stm32h7: Remove old references to RXDMA. Add configuration option to select the Rx FIFO threshold level.

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This commit is contained in:
Gregory Nutt 2018-09-02 08:35:22 -06:00
parent ff1e6a66e9
commit 5c5b6ab8f6
4 changed files with 234 additions and 155 deletions
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2
arch/arm/src/armv7-m/nvic.h
View File

@ -456,7 +456,7 @@
/* NVIC register bit definitions ************************************************************/
/* Interrrupt controller type (INCTCTL_TYPE) */
/* Interrupt controller type (INCTCTL_TYPE) */
#define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 0-3: Number of interrupt inputs / 32 - 1 */
#define NVIC_ICTR_INTLINESNUM_MASK (15 << NVIC_ICTR_INTLINESNUM_SHIFT)

203
arch/arm/src/stm32h7/Kconfig
View File

@ -299,8 +299,7 @@ config USART1_RS485
default n
---help---
Enable RS-485 interface on USART1. Your board config will have to
provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be
used with USART1_RXDMA.
provide GPIO_USART1_RS485_DIR pin definition.
config USART1_RS485_DIR_POLARITY
int "USART1 RS-485 DIR pin polarity"
@ -311,12 +310,23 @@ config USART1_RS485_DIR_POLARITY
Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config USART1_RXDMA
bool "USART1 Rx DMA"
default n
depends on STM32H7_DMA1
config USART1_RXFIFO_THRES
int "USART1 Rx FIFO Threshold"
default 3
range 0 5
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
Select the Rx FIFO threshold:
0 -> 1/8 full
1 -> 1/4 full
2 -> 1/2 full
3 -> 3/4 full
4 -> 7/8 full
5 -> Full
Higher values mean lower interrupt rates and better CPU performance.
Lower values are need at high BAUD rates to prevent Rx data overrun
errors.
endif # STM32H7_USART1
@ -327,8 +337,7 @@ config USART2_RS485
default n
---help---
Enable RS-485 interface on USART2. Your board config will have to
provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be
used with USART2_RXDMA.
provide GPIO_USART2_RS485_DIR pin definition.
config USART2_RS485_DIR_POLARITY
int "USART2 RS-485 DIR pin polarity"
@ -339,12 +348,23 @@ config USART2_RS485_DIR_POLARITY
Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config USART2_RXDMA
bool "USART2 Rx DMA"
default n
depends on STM32H7_DMA1
config USART2_RXFIFO_THRES
int "USART2 Rx FIFO Threshold"
default 3
range 0 5
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
Select the Rx FIFO threshold:
0 -> 1/8 full
1 -> 1/4 full
2 -> 1/2 full
3 -> 3/4 full
4 -> 7/8 full
5 -> Full
Higher values mean lower interrupt rates and better CPU performance.
Lower values are need at high BAUD rates to prevent Rx data overrun
errors.
endif # STM32H7_USART2
@ -355,8 +375,7 @@ config USART3_RS485
default n
---help---
Enable RS-485 interface on USART3. Your board config will have to
provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be
used with USART3_RXDMA.
provide GPIO_USART3_RS485_DIR pin definition.
config USART3_RS485_DIR_POLARITY
int "USART3 RS-485 DIR pin polarity"
@ -367,13 +386,23 @@ config USART3_RS485_DIR_POLARITY
Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config USART3_RXDMA
bool "USART3 Rx DMA"
default n
depends on STM32H7_DMA1
config USART3_RXFIFO_THRES
int "USART3 Rx FIFO Threshold"
default 3
range 0 5
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
Select the Rx FIFO threshold:
0 -> 1/8 full
1 -> 1/4 full
2 -> 1/2 full
3 -> 3/4 full
4 -> 7/8 full
5 -> Full
Higher values mean lower interrupt rates and better CPU performance.
Lower values are need at high BAUD rates to prevent Rx data overrun
errors.
endif # STM32H7_USART3
@ -384,8 +413,7 @@ config UART4_RS485
default n
---help---
Enable RS-485 interface on UART4. Your board config will have to
provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be
used with UART4_RXDMA.
provide GPIO_UART4_RS485_DIR pin definition.
config UART4_RS485_DIR_POLARITY
int "UART4 RS-485 DIR pin polarity"
@ -396,12 +424,23 @@ config UART4_RS485_DIR_POLARITY
Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config UART4_RXDMA
bool "UART4 Rx DMA"
default n
depends on STM32H7_DMA1
config UART4_RXFIFO_THRES
int "UART4 Rx FIFO Threshold"
default 3
range 0 5
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
Select the Rx FIFO threshold:
0 -> 1/8 full
1 -> 1/4 full
2 -> 1/2 full
3 -> 3/4 full
4 -> 7/8 full
5 -> Full
Higher values mean lower interrupt rates and better CPU performance.
Lower values are need at high BAUD rates to prevent Rx data overrun
errors.
endif # STM32H7_UART4
@ -412,8 +451,7 @@ config UART5_RS485
default n
---help---
Enable RS-485 interface on UART5. Your board config will have to
provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be
used with UART5_RXDMA.
provide GPIO_UART5_RS485_DIR pin definition.
config UART5_RS485_DIR_POLARITY
int "UART5 RS-485 DIR pin polarity"
@ -424,12 +462,23 @@ config UART5_RS485_DIR_POLARITY
Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config UART5_RXDMA
bool "UART5 Rx DMA"
default n
depends on STM32H7_DMA1
config UART5_RXFIFO_THRES
int "UART5 Rx FIFO Threshold"
default 3
range 0 5
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
Select the Rx FIFO threshold:
0 -> 1/8 full
1 -> 1/4 full
2 -> 1/2 full
3 -> 3/4 full
4 -> 7/8 full
5 -> Full
Higher values mean lower interrupt rates and better CPU performance.
Lower values are need at high BAUD rates to prevent Rx data overrun
errors.
endif # STM32H7_UART5
@ -440,8 +489,7 @@ config USART6_RS485
default n
---help---
Enable RS-485 interface on USART6. Your board config will have to
provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be
used with USART6_RXDMA.
provide GPIO_USART6_RS485_DIR pin definition.
config USART6_RS485_DIR_POLARITY
int "USART6 RS-485 DIR pin polarity"
@ -452,12 +500,23 @@ config USART6_RS485_DIR_POLARITY
Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config USART6_RXDMA
bool "USART6 Rx DMA"
default n
depends on STM32H7_DMA2
config USART6_RXFIFO_THRES
int "USART6 Rx FIFO Threshold"
default 3
range 0 5
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
Select the Rx FIFO threshold:
0 -> 1/8 full
1 -> 1/4 full
2 -> 1/2 full
3 -> 3/4 full
4 -> 7/8 full
5 -> Full
Higher values mean lower interrupt rates and better CPU performance.
Lower values are need at high BAUD rates to prevent Rx data overrun
errors.
endif # STM32H7_USART
@ -468,8 +527,7 @@ config UART7_RS485
default n
---help---
Enable RS-485 interface on UART7. Your board config will have to
provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be
used with UART7_RXDMA.
provide GPIO_UART7_RS485_DIR pin definition.
config UART7_RS485_DIR_POLARITY
int "UART7 RS-485 DIR pin polarity"
@ -480,12 +538,23 @@ config UART7_RS485_DIR_POLARITY
Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config UART7_RXDMA
bool "UART7 Rx DMA"
default n
depends on STM32H7_DMA2
config UART7_RXFIFO_THRES
int "UART7 Rx FIFO Threshold"
default 3
range 0 5
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
Select the Rx FIFO threshold:
0 -> 1/8 full
1 -> 1/4 full
2 -> 1/2 full
3 -> 3/4 full
4 -> 7/8 full
5 -> Full
Higher values mean lower interrupt rates and better CPU performance.
Lower values are need at high BAUD rates to prevent Rx data overrun
errors.
endif # STM32H7_UART7
@ -496,8 +565,7 @@ config UART8_RS485
default n
---help---
Enable RS-485 interface on UART8. Your board config will have to
provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be
used with UART8_RXDMA.
provide GPIO_UART8_RS485_DIR pin definition.
config UART8_RS485_DIR_POLARITY
int "UART8 RS-485 DIR pin polarity"
@ -508,27 +576,26 @@ config UART8_RS485_DIR_POLARITY
Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config UART8_RXDMA
bool "UART8 Rx DMA"
default n
depends on STM32H7_DMA2
config UART8_RXFIFO_THRES
int "UART8 Rx FIFO Threshold"
default 3
range 0 5
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
Select the Rx FIFO threshold:
0 -> 1/8 full
1 -> 1/4 full
2 -> 1/2 full
3 -> 3/4 full
4 -> 7/8 full
5 -> Full
Higher values mean lower interrupt rates and better CPU performance.
Lower values are need at high BAUD rates to prevent Rx data overrun
errors.
endif # STM32H7_UART8
config STM32H7_SERIAL_RXDMA_BUFFER_SIZE
int "Rx DMA buffer size"
default 32
depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA || USART6_RXDMA || UART7_RXDMA || UART8_RXDMA
---help---
The DMA buffer size when using RX DMA to emulate a FIFO.
When streaming data, the generic serial layer will be called
every time the FIFO receives half this number of bytes.
Value given here will be rounded up to next multiple of 32 bytes.
config STM32H7_SERIAL_DISABLE_REORDERING
bool "Disable reordering of ttySx devices."
default n

2
arch/arm/src/stm32h7/chip/stm32h7x3xx_uart.h
View File

@ -292,6 +292,7 @@
# define USART_CR3_SCARCNT(n) ((uint32_t)(n) << USART_CR3_SCARCNT_SHIFT)
#define USART_CR3_RXFTCFG_SHIFT (25) /* Bit 25-27: Receive FIFO threshold configuration */
#define USART_CR3_RXFTCFG_MASK (7 << USART_CR3_RXFTCFG_SHIFT)
# define USART_CR3_RXFTCFG(n) ((uint32_t)(n) << USART_CR3_RXFTCFG_SHIFT)
# define USART_CR3_RXFTCFG_12PCT (0 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/8 full */
# define USART_CR3_RXFTCFG_25PCT (1 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/4 full */
# define USART_CR3_RXFTCFG_50PCT (2 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/2 full */
@ -301,6 +302,7 @@
#define USART_CR3_RXFTIE (1 << 28) /* Bit 28: RXFIFO threshold interrupt enable */
#define USART_CR3_TXFTCFG_SHIFT (29) /* Bits 29-31: TXFIFO threshold configuration */
#define USART_CR3_TXFTCFG_MASK (7 << USART_CR3_TXFTCFG_SHIFT)
# define USART_CR3_TXFTCFG(n) ((uint32_t)(n) << USART_CR3_TXFTCFG_SHIFT)
# define USART_CR3_TXFTCFG_12PCT (0 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/8 full */
# define USART_CR3_TXFTCFG_24PCT (1 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/4 full */
# define USART_CR3_TXFTCFG_50PCT (2 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/2 full */

182
arch/arm/src/stm32h7/stm32_serial.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32h7/stm32_serial.c
*
* Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2015-2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
@ -146,6 +146,7 @@ struct up_dev_s
#endif
uint32_t baud; /* Configured baud */
#else
const uint8_t rxftcfg; /* Rx FIFO threshold level */
const uint8_t parity; /* 0=none, 1=odd, 2=even */
const uint8_t bits; /* Number of bits (7 or 8) */
const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
@ -295,6 +296,7 @@ static struct up_dev_s g_usart1priv =
},
.irq = STM32_IRQ_USART1,
.rxftcfg = CONFIG_USART1_RXFIFO_THRES,
.parity = CONFIG_USART1_PARITY,
.bits = CONFIG_USART1_BITS,
.stopbits2 = CONFIG_USART1_2STOP,
@ -348,6 +350,7 @@ static struct up_dev_s g_usart2priv =
},
.irq = STM32_IRQ_USART2,
.rxftcfg = CONFIG_USART2_RXFIFO_THRES,
.parity = CONFIG_USART2_PARITY,
.bits = CONFIG_USART2_BITS,
.stopbits2 = CONFIG_USART2_2STOP,
@ -401,6 +404,7 @@ static struct up_dev_s g_usart3priv =
},
.irq = STM32_IRQ_USART3,
.rxftcfg = CONFIG_USART3_RXFIFO_THRES,
.parity = CONFIG_USART3_PARITY,
.bits = CONFIG_USART3_BITS,
.stopbits2 = CONFIG_USART3_2STOP,
@ -454,6 +458,7 @@ static struct up_dev_s g_uart4priv =
},
.irq = STM32_IRQ_UART4,
.rxftcfg = CONFIG_UART4_RXFIFO_THRES,
.parity = CONFIG_UART4_PARITY,
.bits = CONFIG_UART4_BITS,
.stopbits2 = CONFIG_UART4_2STOP,
@ -496,35 +501,36 @@ static struct up_dev_s g_uart5priv =
#if CONSOLE_UART == 5
.isconsole = true,
#endif
.recv =
.recv =
{
.size = CONFIG_UART5_RXBUFSIZE,
.buffer = g_uart5rxbuffer,
.size = CONFIG_UART5_RXBUFSIZE,
.buffer = g_uart5rxbuffer,
},
.xmit =
.xmit =
{
.size = CONFIG_UART5_TXBUFSIZE,
.buffer = g_uart5txbuffer,
.size = CONFIG_UART5_TXBUFSIZE,
.buffer = g_uart5txbuffer,
},
.ops = &g_uart_ops,
.priv = &g_uart5priv,
.ops = &g_uart_ops,
.priv = &g_uart5priv,
},
.irq = STM32_IRQ_UART5,
.parity = CONFIG_UART5_PARITY,
.bits = CONFIG_UART5_BITS,
.stopbits2 = CONFIG_UART5_2STOP,
.irq = STM32_IRQ_UART5,
.rxftcfg = CONFIG_UART5_RXFIFO_THRES,
.parity = CONFIG_UART5_PARITY,
.bits = CONFIG_UART5_BITS,
.stopbits2 = CONFIG_UART5_2STOP,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.iflow = false,
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
.oflow = false,
#endif
.baud = CONFIG_UART5_BAUD,
.apbclock = STM32_PCLK1_FREQUENCY,
.usartbase = STM32_UART5_BASE,
.tx_gpio = GPIO_UART5_TX,
.rx_gpio = GPIO_UART5_RX,
.baud = CONFIG_UART5_BAUD,
.apbclock = STM32_PCLK1_FREQUENCY,
.usartbase = STM32_UART5_BASE,
.tx_gpio = GPIO_UART5_TX,
.rx_gpio = GPIO_UART5_RX,
#ifdef CONFIG_SERIAL_OFLOWCONTROL
.cts_gpio = 0,
#endif
@ -553,36 +559,37 @@ static struct up_dev_s g_usart6priv =
#if CONSOLE_UART == 6
.isconsole = true,
#endif
.recv =
.recv =
{
.size = CONFIG_USART6_RXBUFSIZE,
.buffer = g_usart6rxbuffer,
.size = CONFIG_USART6_RXBUFSIZE,
.buffer = g_usart6rxbuffer,
},
.xmit =
.xmit =
{
.size = CONFIG_USART6_TXBUFSIZE,
.buffer = g_usart6txbuffer,
.size = CONFIG_USART6_TXBUFSIZE,
.buffer = g_usart6txbuffer,
},
.ops = &g_uart_ops,
.priv = &g_usart6priv,
.ops = &g_uart_ops,
.priv = &g_usart6priv,
},
.irq = STM32_IRQ_USART6,
.parity = CONFIG_USART6_PARITY,
.bits = CONFIG_USART6_BITS,
.stopbits2 = CONFIG_USART6_2STOP,
.baud = CONFIG_USART6_BAUD,
.apbclock = STM32_PCLK2_FREQUENCY,
.usartbase = STM32_USART6_BASE,
.tx_gpio = GPIO_USART6_TX,
.rx_gpio = GPIO_USART6_RX,
.irq = STM32_IRQ_USART6,
.rxftcfg = CONFIG_USART6_RXFIFO_THRES,
.parity = CONFIG_USART6_PARITY,
.bits = CONFIG_USART6_BITS,
.stopbits2 = CONFIG_USART6_2STOP,
.baud = CONFIG_USART6_BAUD,
.apbclock = STM32_PCLK2_FREQUENCY,
.usartbase = STM32_USART6_BASE,
.tx_gpio = GPIO_USART6_TX,
.rx_gpio = GPIO_USART6_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART6_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART6_CTS,
.oflow = true,
.cts_gpio = GPIO_USART6_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART6_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART6_RTS,
.iflow = true,
.rts_gpio = GPIO_USART6_RTS,
#endif
#ifdef CONFIG_USART6_RS485
@ -606,36 +613,37 @@ static struct up_dev_s g_uart7priv =
#if CONSOLE_UART == 7
.isconsole = true,
#endif
.recv =
.recv =
{
.size = CONFIG_UART7_RXBUFSIZE,
.buffer = g_uart7rxbuffer,
.size = CONFIG_UART7_RXBUFSIZE,
.buffer = g_uart7rxbuffer,
},
.xmit =
.xmit =
{
.size = CONFIG_UART7_TXBUFSIZE,
.buffer = g_uart7txbuffer,
.size = CONFIG_UART7_TXBUFSIZE,
.buffer = g_uart7txbuffer,
},
.ops = &g_uart_ops,
.priv = &g_uart7priv,
.ops = &g_uart_ops,
.priv = &g_uart7priv,
},
.irq = STM32_IRQ_UART7,
.parity = CONFIG_UART7_PARITY,
.bits = CONFIG_UART7_BITS,
.stopbits2 = CONFIG_UART7_2STOP,
.baud = CONFIG_UART7_BAUD,
.apbclock = STM32_PCLK1_FREQUENCY,
.usartbase = STM32_UART7_BASE,
.tx_gpio = GPIO_UART7_TX,
.rx_gpio = GPIO_UART7_RX,
.irq = STM32_IRQ_UART7,
.rxftcfg = CONFIG_UART7_RXFIFO_THRES,
.parity = CONFIG_UART7_PARITY,
.bits = CONFIG_UART7_BITS,
.stopbits2 = CONFIG_UART7_2STOP,
.baud = CONFIG_UART7_BAUD,
.apbclock = STM32_PCLK1_FREQUENCY,
.usartbase = STM32_UART7_BASE,
.tx_gpio = GPIO_UART7_TX,
.rx_gpio = GPIO_UART7_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART7_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_UART7_CTS,
.oflow = true,
.cts_gpio = GPIO_UART7_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART7_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_UART7_RTS,
.iflow = true,
.rts_gpio = GPIO_UART7_RTS,
#endif
#ifdef CONFIG_UART7_RS485
@ -659,36 +667,37 @@ static struct up_dev_s g_uart8priv =
#if CONSOLE_UART == 8
.isconsole = true,
#endif
.recv =
.recv =
{
.size = CONFIG_UART8_RXBUFSIZE,
.buffer = g_uart8rxbuffer,
.size = CONFIG_UART8_RXBUFSIZE,
.buffer = g_uart8rxbuffer,
},
.xmit =
.xmit =
{
.size = CONFIG_UART8_TXBUFSIZE,
.buffer = g_uart8txbuffer,
.size = CONFIG_UART8_TXBUFSIZE,
.buffer = g_uart8txbuffer,
},
.ops = &g_uart_ops,
.priv = &g_uart8priv,
.ops = &g_uart_ops,
.priv = &g_uart8priv,
},
.irq = STM32_IRQ_UART8,
.parity = CONFIG_UART8_PARITY,
.bits = CONFIG_UART8_BITS,
.stopbits2 = CONFIG_UART8_2STOP,
.baud = CONFIG_UART8_BAUD,
.apbclock = STM32_PCLK1_FREQUENCY,
.usartbase = STM32_UART8_BASE,
.tx_gpio = GPIO_UART8_TX,
.rx_gpio = GPIO_UART8_RX,
.irq = STM32_IRQ_UART8,
.rxftcfg = CONFIG_USRT8_RXFIFO_THRES,
.parity = CONFIG_UART8_PARITY,
.bits = CONFIG_UART8_BITS,
.stopbits2 = CONFIG_UART8_2STOP,
.baud = CONFIG_UART8_BAUD,
.apbclock = STM32_PCLK1_FREQUENCY,
.usartbase = STM32_UART8_BASE,
.tx_gpio = GPIO_UART8_TX,
.rx_gpio = GPIO_UART8_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART8_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_UART8_CTS,
.oflow = true,
.cts_gpio = GPIO_UART8_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART8_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_UART8_RTS,
.iflow = true,
.rts_gpio = GPIO_UART8_RTS,
#endif
#ifdef CONFIG_UART8_RS485
@ -1198,8 +1207,9 @@ static int up_setup(struct uart_dev_s *dev)
regval = up_serialin(priv, STM32_USART_CR3_OFFSET);
regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE);
/* Set FIFO threshold to empty */
regval |= USART_CR3_RXFTCFG_FULL;
/* Set Rx FIFO threshold to empty */
regval |= USART_CR3_RXFTCFG(priv->rxftcfg);
up_serialout(priv, STM32_USART_CR3_OFFSET, regval);
@ -1210,8 +1220,8 @@ static int up_setup(struct uart_dev_s *dev)
/* Enable Rx, Tx, and the USART */
/* Enable FIFO */
regval = up_serialin(priv, STM32_USART_CR1_OFFSET);
regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
regval = up_serialin(priv, STM32_USART_CR1_OFFSET);
regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
regval |= USART_CR1_FIFOEN;
up_serialout(priv, STM32_USART_CR1_OFFSET, regval);
@ -1220,7 +1230,7 @@ static int up_setup(struct uart_dev_s *dev)
/* Set up the cached interrupt enables value */
priv->ie = 0;
priv->ie = 0;
/* Mark device as initialized. */