arch/arm/src/stm32h7: Remove old references to RXDMA. Add configuration option to select the Rx FIFO threshold level.
This commit is contained in:
Gregory Nutt
parent
ff1e6a66e9
commit
5c5b6ab8f6
@ -456,7 +456,7 @@
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/* NVIC register bit definitions ************************************************************/
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/* Interrrupt controller type (INCTCTL_TYPE) */
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/* Interrupt controller type (INCTCTL_TYPE) */
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#define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 0-3: Number of interrupt inputs / 32 - 1 */
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#define NVIC_ICTR_INTLINESNUM_MASK (15 << NVIC_ICTR_INTLINESNUM_SHIFT)
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@ -299,8 +299,7 @@ config USART1_RS485
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default n
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---help---
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Enable RS-485 interface on USART1. Your board config will have to
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provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be
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used with USART1_RXDMA.
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provide GPIO_USART1_RS485_DIR pin definition.
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config USART1_RS485_DIR_POLARITY
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int "USART1 RS-485 DIR pin polarity"
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@ -311,12 +310,23 @@ config USART1_RS485_DIR_POLARITY
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Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which
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enables TX (0 - low / nTXEN, 1 - high / TXEN).
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config USART1_RXDMA
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bool "USART1 Rx DMA"
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default n
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depends on STM32H7_DMA1
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config USART1_RXFIFO_THRES
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int "USART1 Rx FIFO Threshold"
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default 3
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range 0 5
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---help---
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In high data rate usage, Rx DMA may eliminate Rx overrun errors
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Select the Rx FIFO threshold:
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0 -> 1/8 full
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1 -> 1/4 full
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2 -> 1/2 full
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3 -> 3/4 full
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4 -> 7/8 full
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5 -> Full
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Higher values mean lower interrupt rates and better CPU performance.
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Lower values are need at high BAUD rates to prevent Rx data overrun
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errors.
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endif # STM32H7_USART1
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@ -327,8 +337,7 @@ config USART2_RS485
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default n
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---help---
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Enable RS-485 interface on USART2. Your board config will have to
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provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be
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used with USART2_RXDMA.
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provide GPIO_USART2_RS485_DIR pin definition.
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config USART2_RS485_DIR_POLARITY
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int "USART2 RS-485 DIR pin polarity"
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@ -339,12 +348,23 @@ config USART2_RS485_DIR_POLARITY
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Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which
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enables TX (0 - low / nTXEN, 1 - high / TXEN).
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config USART2_RXDMA
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bool "USART2 Rx DMA"
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default n
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depends on STM32H7_DMA1
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config USART2_RXFIFO_THRES
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int "USART2 Rx FIFO Threshold"
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default 3
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range 0 5
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---help---
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In high data rate usage, Rx DMA may eliminate Rx overrun errors
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Select the Rx FIFO threshold:
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0 -> 1/8 full
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1 -> 1/4 full
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2 -> 1/2 full
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3 -> 3/4 full
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4 -> 7/8 full
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5 -> Full
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Higher values mean lower interrupt rates and better CPU performance.
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Lower values are need at high BAUD rates to prevent Rx data overrun
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errors.
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endif # STM32H7_USART2
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@ -355,8 +375,7 @@ config USART3_RS485
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default n
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---help---
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Enable RS-485 interface on USART3. Your board config will have to
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provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be
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used with USART3_RXDMA.
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provide GPIO_USART3_RS485_DIR pin definition.
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config USART3_RS485_DIR_POLARITY
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int "USART3 RS-485 DIR pin polarity"
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@ -367,13 +386,23 @@ config USART3_RS485_DIR_POLARITY
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Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which
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enables TX (0 - low / nTXEN, 1 - high / TXEN).
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config USART3_RXDMA
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bool "USART3 Rx DMA"
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default n
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depends on STM32H7_DMA1
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config USART3_RXFIFO_THRES
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int "USART3 Rx FIFO Threshold"
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default 3
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range 0 5
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---help---
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In high data rate usage, Rx DMA may eliminate Rx overrun errors
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Select the Rx FIFO threshold:
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0 -> 1/8 full
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1 -> 1/4 full
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2 -> 1/2 full
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3 -> 3/4 full
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4 -> 7/8 full
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5 -> Full
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Higher values mean lower interrupt rates and better CPU performance.
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Lower values are need at high BAUD rates to prevent Rx data overrun
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errors.
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endif # STM32H7_USART3
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@ -384,8 +413,7 @@ config UART4_RS485
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default n
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---help---
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Enable RS-485 interface on UART4. Your board config will have to
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provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be
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used with UART4_RXDMA.
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provide GPIO_UART4_RS485_DIR pin definition.
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config UART4_RS485_DIR_POLARITY
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int "UART4 RS-485 DIR pin polarity"
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@ -396,12 +424,23 @@ config UART4_RS485_DIR_POLARITY
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Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which
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enables TX (0 - low / nTXEN, 1 - high / TXEN).
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config UART4_RXDMA
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bool "UART4 Rx DMA"
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default n
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depends on STM32H7_DMA1
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config UART4_RXFIFO_THRES
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int "UART4 Rx FIFO Threshold"
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default 3
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range 0 5
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---help---
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In high data rate usage, Rx DMA may eliminate Rx overrun errors
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Select the Rx FIFO threshold:
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0 -> 1/8 full
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1 -> 1/4 full
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2 -> 1/2 full
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3 -> 3/4 full
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4 -> 7/8 full
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5 -> Full
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Higher values mean lower interrupt rates and better CPU performance.
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Lower values are need at high BAUD rates to prevent Rx data overrun
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errors.
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endif # STM32H7_UART4
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@ -412,8 +451,7 @@ config UART5_RS485
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default n
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---help---
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Enable RS-485 interface on UART5. Your board config will have to
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provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be
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used with UART5_RXDMA.
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provide GPIO_UART5_RS485_DIR pin definition.
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config UART5_RS485_DIR_POLARITY
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int "UART5 RS-485 DIR pin polarity"
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@ -424,12 +462,23 @@ config UART5_RS485_DIR_POLARITY
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Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which
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enables TX (0 - low / nTXEN, 1 - high / TXEN).
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config UART5_RXDMA
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bool "UART5 Rx DMA"
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default n
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depends on STM32H7_DMA1
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config UART5_RXFIFO_THRES
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int "UART5 Rx FIFO Threshold"
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default 3
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range 0 5
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---help---
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In high data rate usage, Rx DMA may eliminate Rx overrun errors
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Select the Rx FIFO threshold:
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0 -> 1/8 full
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1 -> 1/4 full
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2 -> 1/2 full
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3 -> 3/4 full
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4 -> 7/8 full
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5 -> Full
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Higher values mean lower interrupt rates and better CPU performance.
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Lower values are need at high BAUD rates to prevent Rx data overrun
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errors.
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endif # STM32H7_UART5
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@ -440,8 +489,7 @@ config USART6_RS485
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default n
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---help---
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Enable RS-485 interface on USART6. Your board config will have to
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provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be
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used with USART6_RXDMA.
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provide GPIO_USART6_RS485_DIR pin definition.
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config USART6_RS485_DIR_POLARITY
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int "USART6 RS-485 DIR pin polarity"
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@ -452,12 +500,23 @@ config USART6_RS485_DIR_POLARITY
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Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which
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enables TX (0 - low / nTXEN, 1 - high / TXEN).
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config USART6_RXDMA
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bool "USART6 Rx DMA"
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default n
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depends on STM32H7_DMA2
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config USART6_RXFIFO_THRES
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int "USART6 Rx FIFO Threshold"
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default 3
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range 0 5
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---help---
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In high data rate usage, Rx DMA may eliminate Rx overrun errors
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Select the Rx FIFO threshold:
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0 -> 1/8 full
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1 -> 1/4 full
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2 -> 1/2 full
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3 -> 3/4 full
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4 -> 7/8 full
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5 -> Full
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Higher values mean lower interrupt rates and better CPU performance.
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Lower values are need at high BAUD rates to prevent Rx data overrun
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errors.
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endif # STM32H7_USART
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@ -468,8 +527,7 @@ config UART7_RS485
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default n
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---help---
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Enable RS-485 interface on UART7. Your board config will have to
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provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be
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used with UART7_RXDMA.
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provide GPIO_UART7_RS485_DIR pin definition.
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config UART7_RS485_DIR_POLARITY
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int "UART7 RS-485 DIR pin polarity"
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@ -480,12 +538,23 @@ config UART7_RS485_DIR_POLARITY
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Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which
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enables TX (0 - low / nTXEN, 1 - high / TXEN).
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config UART7_RXDMA
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bool "UART7 Rx DMA"
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default n
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depends on STM32H7_DMA2
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config UART7_RXFIFO_THRES
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int "UART7 Rx FIFO Threshold"
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default 3
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range 0 5
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---help---
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In high data rate usage, Rx DMA may eliminate Rx overrun errors
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Select the Rx FIFO threshold:
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0 -> 1/8 full
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1 -> 1/4 full
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2 -> 1/2 full
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3 -> 3/4 full
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4 -> 7/8 full
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5 -> Full
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Higher values mean lower interrupt rates and better CPU performance.
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Lower values are need at high BAUD rates to prevent Rx data overrun
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errors.
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endif # STM32H7_UART7
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@ -496,8 +565,7 @@ config UART8_RS485
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default n
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---help---
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Enable RS-485 interface on UART8. Your board config will have to
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provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be
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used with UART8_RXDMA.
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provide GPIO_UART8_RS485_DIR pin definition.
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config UART8_RS485_DIR_POLARITY
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int "UART8 RS-485 DIR pin polarity"
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@ -508,27 +576,26 @@ config UART8_RS485_DIR_POLARITY
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Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which
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enables TX (0 - low / nTXEN, 1 - high / TXEN).
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config UART8_RXDMA
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bool "UART8 Rx DMA"
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default n
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depends on STM32H7_DMA2
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config UART8_RXFIFO_THRES
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int "UART8 Rx FIFO Threshold"
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default 3
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range 0 5
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---help---
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In high data rate usage, Rx DMA may eliminate Rx overrun errors
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Select the Rx FIFO threshold:
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0 -> 1/8 full
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1 -> 1/4 full
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2 -> 1/2 full
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3 -> 3/4 full
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4 -> 7/8 full
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5 -> Full
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Higher values mean lower interrupt rates and better CPU performance.
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Lower values are need at high BAUD rates to prevent Rx data overrun
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errors.
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endif # STM32H7_UART8
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config STM32H7_SERIAL_RXDMA_BUFFER_SIZE
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int "Rx DMA buffer size"
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default 32
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depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA || USART6_RXDMA || UART7_RXDMA || UART8_RXDMA
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---help---
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The DMA buffer size when using RX DMA to emulate a FIFO.
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When streaming data, the generic serial layer will be called
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every time the FIFO receives half this number of bytes.
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Value given here will be rounded up to next multiple of 32 bytes.
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config STM32H7_SERIAL_DISABLE_REORDERING
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bool "Disable reordering of ttySx devices."
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default n
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@ -292,6 +292,7 @@
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# define USART_CR3_SCARCNT(n) ((uint32_t)(n) << USART_CR3_SCARCNT_SHIFT)
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#define USART_CR3_RXFTCFG_SHIFT (25) /* Bit 25-27: Receive FIFO threshold configuration */
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#define USART_CR3_RXFTCFG_MASK (7 << USART_CR3_RXFTCFG_SHIFT)
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# define USART_CR3_RXFTCFG(n) ((uint32_t)(n) << USART_CR3_RXFTCFG_SHIFT)
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# define USART_CR3_RXFTCFG_12PCT (0 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/8 full */
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# define USART_CR3_RXFTCFG_25PCT (1 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/4 full */
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# define USART_CR3_RXFTCFG_50PCT (2 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/2 full */
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@ -301,6 +302,7 @@
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#define USART_CR3_RXFTIE (1 << 28) /* Bit 28: RXFIFO threshold interrupt enable */
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#define USART_CR3_TXFTCFG_SHIFT (29) /* Bits 29-31: TXFIFO threshold configuration */
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#define USART_CR3_TXFTCFG_MASK (7 << USART_CR3_TXFTCFG_SHIFT)
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# define USART_CR3_TXFTCFG(n) ((uint32_t)(n) << USART_CR3_TXFTCFG_SHIFT)
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# define USART_CR3_TXFTCFG_12PCT (0 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/8 full */
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# define USART_CR3_TXFTCFG_24PCT (1 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/4 full */
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# define USART_CR3_TXFTCFG_50PCT (2 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/2 full */
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/stm32h7/stm32_serial.c
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*
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* Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015-2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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@ -146,6 +146,7 @@ struct up_dev_s
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#endif
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uint32_t baud; /* Configured baud */
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#else
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const uint8_t rxftcfg; /* Rx FIFO threshold level */
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const uint8_t parity; /* 0=none, 1=odd, 2=even */
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const uint8_t bits; /* Number of bits (7 or 8) */
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const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
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@ -295,6 +296,7 @@ static struct up_dev_s g_usart1priv =
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},
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.irq = STM32_IRQ_USART1,
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.rxftcfg = CONFIG_USART1_RXFIFO_THRES,
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.parity = CONFIG_USART1_PARITY,
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.bits = CONFIG_USART1_BITS,
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.stopbits2 = CONFIG_USART1_2STOP,
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@ -348,6 +350,7 @@ static struct up_dev_s g_usart2priv =
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},
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.irq = STM32_IRQ_USART2,
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.rxftcfg = CONFIG_USART2_RXFIFO_THRES,
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.parity = CONFIG_USART2_PARITY,
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.bits = CONFIG_USART2_BITS,
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.stopbits2 = CONFIG_USART2_2STOP,
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@ -401,6 +404,7 @@ static struct up_dev_s g_usart3priv =
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},
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.irq = STM32_IRQ_USART3,
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.rxftcfg = CONFIG_USART3_RXFIFO_THRES,
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.parity = CONFIG_USART3_PARITY,
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.bits = CONFIG_USART3_BITS,
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.stopbits2 = CONFIG_USART3_2STOP,
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@ -454,6 +458,7 @@ static struct up_dev_s g_uart4priv =
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},
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.irq = STM32_IRQ_UART4,
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.rxftcfg = CONFIG_UART4_RXFIFO_THRES,
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.parity = CONFIG_UART4_PARITY,
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.bits = CONFIG_UART4_BITS,
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.stopbits2 = CONFIG_UART4_2STOP,
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@ -511,6 +516,7 @@ static struct up_dev_s g_uart5priv =
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},
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.irq = STM32_IRQ_UART5,
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.rxftcfg = CONFIG_UART5_RXFIFO_THRES,
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.parity = CONFIG_UART5_PARITY,
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.bits = CONFIG_UART5_BITS,
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.stopbits2 = CONFIG_UART5_2STOP,
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@ -568,6 +574,7 @@ static struct up_dev_s g_usart6priv =
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},
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.irq = STM32_IRQ_USART6,
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.rxftcfg = CONFIG_USART6_RXFIFO_THRES,
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.parity = CONFIG_USART6_PARITY,
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.bits = CONFIG_USART6_BITS,
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.stopbits2 = CONFIG_USART6_2STOP,
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@ -621,6 +628,7 @@ static struct up_dev_s g_uart7priv =
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},
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.irq = STM32_IRQ_UART7,
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.rxftcfg = CONFIG_UART7_RXFIFO_THRES,
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.parity = CONFIG_UART7_PARITY,
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.bits = CONFIG_UART7_BITS,
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.stopbits2 = CONFIG_UART7_2STOP,
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@ -674,6 +682,7 @@ static struct up_dev_s g_uart8priv =
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},
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.irq = STM32_IRQ_UART8,
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.rxftcfg = CONFIG_USRT8_RXFIFO_THRES,
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.parity = CONFIG_UART8_PARITY,
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.bits = CONFIG_UART8_BITS,
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.stopbits2 = CONFIG_UART8_2STOP,
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@ -1198,8 +1207,9 @@ static int up_setup(struct uart_dev_s *dev)
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regval = up_serialin(priv, STM32_USART_CR3_OFFSET);
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regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE);
|
||||
|
||||
/* Set FIFO threshold to empty */
|
||||
regval |= USART_CR3_RXFTCFG_FULL;
|
||||
/* Set Rx FIFO threshold to empty */
|
||||
|
||||
regval |= USART_CR3_RXFTCFG(priv->rxftcfg);
|
||||
|
||||
up_serialout(priv, STM32_USART_CR3_OFFSET, regval);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user