procfs：add armv7-a cpuinfo
Signed-off-by: liaoao <liaoao@xiaomi.com>
This commit is contained in:
liaoao
Xiang Xiao
parent
108c47c07b
commit
5c5d9420af
@ -772,6 +772,7 @@ config ARCH_CORTEXM7
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config ARCH_ARMV7A
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bool
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default n
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select ARCH_HAVE_CPUINFO
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select ARM_HAVE_WFE_SEV
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config ARCH_CORTEXA5
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@ -41,7 +41,7 @@ CMN_ASRCS += arm_saveusercontext.S
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# Common C source files
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CMN_CSRCS += arm_cache.c arm_dataabort.c
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CMN_CSRCS += arm_cache.c arm_cpuinfo.c arm_dataabort.c
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CMN_CSRCS += arm_doirq.c arm_gicv2.c arm_gicv2_dump.c
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CMN_CSRCS += arm_initialstate.c arm_mmu.c arm_prefetchabort.c
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CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
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167
arch/arm/src/armv7-a/arm_cpuinfo.c
Normal file
167
arch/arm/src/armv7-a/arm_cpuinfo.c
Normal file
@ -0,0 +1,167 @@
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/****************************************************************************
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* arch/arm/src/armv7-a/arm_cpuinfo.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/arch.h>
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#include <nuttx/config.h>
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#include <nuttx/fs/procfs.h>
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#include "arm_internal.h"
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#include "hwcap.h"
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#include "cp15.h"
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#if defined(CONFIG_FS_PROCFS) && !defined(CONFIG_FS_PROCFS_EXCLUDE_CPUINFO)
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* name: hwcap_extract_field
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****************************************************************************/
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static int hwcap_extract_field(uint32_t features, int field)
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{
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int feature;
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feature = (features >> field) & 0xf;
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if (feature > 7)
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{
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feature -= 16;
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}
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return feature;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* name: up_show_cpuinfo
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****************************************************************************/
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ssize_t up_show_cpuinfo(FAR char *buf, size_t buf_size, off_t file_off)
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{
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int i;
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uint32_t cpuid;
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for (i = 0; i < CONFIG_SMP_NCPUS; i++)
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{
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procfs_sprintf(buf, buf_size, &file_off, "processor\t: %d\n", i);
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procfs_sprintf(buf, buf_size, &file_off, "BogoMIPS\t: %u.%02u\n",
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(CONFIG_BOARD_LOOPSPERMSEC / 1000),
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(CONFIG_BOARD_LOOPSPERMSEC / 10) % 100);
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procfs_sprintf(buf, buf_size, &file_off, "cpu MHz\t\t: %lu.%02lu\n",
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up_perf_getfreq() / 1000000,
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(up_perf_getfreq() / 10000) % 100);
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/* CPU Features */
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procfs_sprintf(buf, buf_size, &file_off, "Features\t:");
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procfs_sprintf(buf, buf_size, &file_off, " %s %s %s",
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HWCAP_HALF, HWCAP_FAST_MULT, HWCAP_EDSP);
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/* If the CPU supports LDREX/STREX and LDREXB/STREXB,
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* avoid advertising SWP; it may not be atomic with
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* multiprocessing cores.
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*/
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if (hwcap_extract_field(CP15_GET(ID_ISAR3), 12) <= 1 &&
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hwcap_extract_field(CP15_GET(ID_ISAR4), 20) < 3)
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{
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procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_SWP);
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}
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#ifdef CONFIG_ARM_THUMB
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if (hwcap_extract_field(CP15_GET(ID_ISAR0), 24) >= 1)
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{
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procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_IDIVT);
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}
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procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_THUMB);
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#endif
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if (hwcap_extract_field(CP15_GET(ID_ISAR0), 24) == 2)
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{
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procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_IDIVA);
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}
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#ifdef CONFIG_SCHED_THREAD_LOCAL
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procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_TLS);
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#endif
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/* LPAE implies atomic ldrd/strd instructions */
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if (hwcap_extract_field(CP15_GET(ID_ISAR2), 0) == 1)
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{
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procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_LPAE);
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}
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/* VFP Features */
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#if defined(CONFIG_ARCH_FPU)
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# if defined(CONFIG_ARCH_CORTEXA8) || defined(CONFIG_ARCH_CORTEXA9)
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procfs_sprintf(buf, buf_size, &file_off, " %s %s %s",
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HWCAP_VFPV3, HWCAP_FPSP, HWCAP_FPDP);
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# else
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procfs_sprintf(buf, buf_size, &file_off, " %s %s %s",
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HWCAP_VFPV4, HWCAP_FPSP, HWCAP_FPDP);
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# endif
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# if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA9)
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procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_FPHP);
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# endif
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# ifdef CONFIG_ARM_DPFPU32
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procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_VFPD32);
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# else
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procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_VFPV3D16);
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# endif
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# ifdef CONFIG_ARM_NEON
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procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_NEON);
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# endif
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#endif
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/* Cpuid info */
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cpuid = CP15_GET(MIDR);
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procfs_sprintf(buf, buf_size, &file_off,
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"\nmodel name\t: %s rev %" PRIx32 " (%s)\n"
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"CPU architecture: %s\n",
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"ARMv7 Processor", cpuid & 15, "v7", "7");
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procfs_sprintf(buf, buf_size, &file_off,
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"CPU implementer\t: 0x%02" PRIx32 "\n"
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"CPU variant\t: 0x%" PRIx32 "\n"
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"CPU part\t: 0x%03" PRIx32 "\n"
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"CPU revision\t: %" PRIu32 "\n\n",
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cpuid >> 24,
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(cpuid >> 20) & 0xf,
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(cpuid >> 4) & 0xfff,
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cpuid & 0xf);
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}
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return -file_off;
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}
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#endif /* CONFIG_FS_PROCFS && !CONFIG_FS_PROCFS_EXCLUDE_CPUINFO */
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