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Add m9s12 serial logic

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3305 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-02-20 15:19:44 +00:00
parent 64010e82ae
commit 5c5f8e33e6
1 changed files with 21 additions and 0 deletions
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21
configs/demo9s12ne64/include/board.h
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@ -51,9 +51,30 @@
************************************************************************************/
/* Clocking *************************************************************************/
/* Frequency of the crystal oscillator */
#define HCS12_OSCCLK 16000000 /* 16MHz */
/* PLL Settings
*
* SYNR register controls the multiplication factor of the PLL. If the PLL is on, the
* count in the loop divider (SYNR) register effectively multiplies up the PLL clock
* (PLLCLK) from the reference frequency by 2 x (SYNR+1). PLLCLK will not be below
* the minimum VCO frequency (fSCM).
*
* The REFDV register provides a finer granularity for the PLL multiplier steps. The
* count in the reference divider divides OSCCLK frequency by REFDV + 1.
*
* PLLCLK = 2 * OSCCLK * (SYNR + 1) / (REFDV + 1)
*
* If (PLLSEL = 1), Bus Clock = PLLCLK / 2
*/
#define HCS12_SYNR_VALUE 0x15
#define HCS12_REFDV_VALUE 0x15
#define HCS12_PLLCLK (2*HCS12_OSCCLK*(HCS12_SYNR+1)/(HCS12_REFDV+1))
#define HCS12_BUSCLK (HSC12_PLLCLK/2)
/* LED definitions ******************************************************************/
/* The DEMO9S12NE64 board has 2 LEDs that we will encode as: */