STM32 F7: Add PWR register definitions
This commit is contained in:
Gregory Nutt
parent
64869024f3
commit
5c76329d2e
@ -89,7 +89,7 @@
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#define EXTI_RTC_TAMPER (1 << 21) /* EXTI line 21 = RTC Tamper and TimeStamp events */
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#define EXTI_RTC_TIMESTAMP (1 << 21) /* EXTI line 21 = RTC Tamper and TimeStamp events */
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#define EXTI_RTC_WAKEUP (1 << 22) /* EXTI line 22 = RTC Wakeup event */
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#define EXTI_RTC_WAKEUP (1 << 23) /* EXTI line 23 = LPTIM1 asynchronous event */
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#define EXTI_LPTIM1_WAKEUP (1 << 23) /* EXTI line 23 = LPTIM1 asynchronous event */
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/* Interrupt mask register */
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52
arch/arm/src/stm32f7/chip/stm32_pwr.h
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52
arch/arm/src/stm32f7/chip/stm32_pwr.h
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@ -0,0 +1,52 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32_pwr.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PWR_H
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#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PWR_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# include "chip/stm32f74xx75xx_pwr.h"
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#else
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# error "Unsupported STM32 F7 part"
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#endif
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#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PWR_H */
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156
arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h
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156
arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h
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@ -0,0 +1,156 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32_pwr.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_PWR_H
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#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_PWR_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */
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#define STM32_PWR_CSR1_OFFSET 0x0004 /* Power control/status register 1 */
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#define STM32_PWR_CR2_OFFSET 0x0008 /* Power control register 1 */
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#define STM32_PWR_CSR2_OFFSET 0x000c /* Power control/status register 1 */
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/* Register Addresses ***************************************************************/
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#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET)
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#define STM32_PWR_CSR1 (STM32_PWR_BASE+STM32_PWR_CSR1_OFFSET)
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#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET)
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#define STM32_PWR_CSR2 (STM32_PWR_BASE+STM32_PWR_CSR2_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* Power control register 1 */
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#define PWR_CR1_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */
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#define PWR_CR1_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */
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#define PWR_CR1_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */
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#define PWR_CR1_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */
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#define PWR_CR1_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */
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#define PWR_CR1_PLS_MASK (7 << PWR_CR1_PLS_SHIFT)
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# define PWR_CR1_2p0V (0 << PWR_CR1_PLS_SHIFT) /* 000: 2.0V */
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# define PWR_CR1_2p1V (1 << PWR_CR1_PLS_SHIFT) /* 001: 2.1V */
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# define PWR_CR1_2p3V (2 << PWR_CR1_PLS_SHIFT) /* 010: 2.3V */
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# define PWR_CR1_2p5V (3 << PWR_CR1_PLS_SHIFT) /* 011: 2.5V */
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# define PWR_CR1_2p6V (4 << PWR_CR1_PLS_SHIFT) /* 100: 2.6V */
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# define PWR_CR1_2p7V (5 << PWR_CR1_PLS_SHIFT) /* 101: 2.7V */
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# define PWR_CR1_2p8V (6 << PWR_CR1_PLS_SHIFT) /* 110: 2.8V */
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# define PWR_CR1_2p9V (7 << PWR_CR1_PLS_SHIFT) /* 111: 2.9V */
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#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */
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#define PWR_CR1_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */
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#define PWR_CR1_LPUDS (1 << 10) /* Bit 10: Low-power regulator in deepsleep under-drive mode */
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#define PWR_CR1_MRUDS (1 << 11) /* Bit 11: Main regulator in deepsleep under-drive mode */
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#define PWR_CR1_ADCDC1 (1 << 13) /* Bit 13: see AN4073 for details */
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#define PWR_CR1_VOS_SHIFT (14) /* Bits 14-15: Regulator voltage scaling output selection */
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#define PWR_CR1_VOS_MASK (3 << PWR_CR1_VOS_SHIFT)
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# define PWR_CR1_VOS_SCALE_3 (1 << PWR_CR1_VOS_SHIFT) /* Fmax = 144MHz */
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# define PWR_CR1_VOS_SCALE_2 (2 << PWR_CR1_VOS_SHIFT) /* Fmax = 168/180MHz */
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# define PWR_CR1_VOS_SCALE_1 (3 << PWR_CR1_VOS_SHIFT) /* Fmax = 180/216MHz */
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#define PWR_CR1_ODEN (1 << 16) /* Bit 16: Over Drive enable */
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#define PWR_CR1_ODSWEN (1 << 17) /* Bit 17: Over Drive switch enabled */
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#define PWR_CR1_UDEN_SHIFT (18) /* Bits 18-19: Under-drive enable in stop mode */
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#define PWR_CR1_UDEN_MASK (3 << PWR_CR1_UDEN_SHIFT)
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# define PWR_CR1_UDEN_DISABLE (0 << PWR_CR1_UDEN_SHIFT) /* Under-drive disable */
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# define PWR_CR1_UDEN_ENABLE (3 << PWR_CR1_UDEN_SHIFT) /* Under-drive enable */
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/* Power control/status register 1 */
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#define PWR_CSR1_WUIF (1 << 0) /* Bit 0: Wakeup internal flag */
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#define PWR_CSR1_SBF (1 << 1) /* Bit 1: Standby flag */
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#define PWR_CSR1_PVDO (1 << 2) /* Bit 2: PVD Output */
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#define PWR_CSR1_BRR (1 << 3) /* Bit 3: Backup regulator ready */
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#define PWR_CSR1_BRE (1 << 9) /* Bit 9: Backup regulator enable */
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#define PWR_CSR1_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */
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#define PWR_CSR1_ODRDY (1 << 16) /* Bit 16: Over Drive generator ready */
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#define PWR_CSR1_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */
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#define PWR_CSR1_UDSRDY_SHIFT (18) /* Bits 18-19: Under-drive ready flag */
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#define PWR_CSR1_UDSRDY_MASK (3 << PWR_CSR1_UDSRDY_SHIFT)
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# define PWR_CSR1_UDSRDY_DISAB (0 << PWR_CSR1_UDSRDY_SHIFT) /* Under-drive is disabled */
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# define PWR_CSR1_UDSRDY_STOP (3 << PWR_CSR1_UDSRDY_SHIFT) /* Under-drive mode is activated in Stop mode */
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/* Power control register 2 */
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#define PWR_CR2_CWUPF1 (1 << 0) /* Bit 0: Clear Wakeup Pin flag for PA0 */
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#define PWR_CR2_CWUPF2 (1 << 1) /* Bit 1: Clear Wakeup Pin flag for PA2 */
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#define PWR_CR2_CWUPF3 (1 << 2) /* Bit 2: Clear Wakeup Pin flag for PC1 */
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#define PWR_CR2_CWUPF4 (1 << 3) /* Bit 3: Clear Wakeup Pin flag for PC13 */
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#define PWR_CR2_CWUPF5 (1 << 4) /* Bit 4: Clear Wakeup Pin flag for PI8 */
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#define PWR_CR2_CWUPF6 (1 << 5) /* Bit 5: Clear Wakeup Pin flag for PI11 */
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#define PWR_CR2_WUPP1 (1 << 8) /* Bit 8: Wakeup pin polarity bit for PA0 */
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# define PWR_CR2_WUPP1_RISING (0 << 8) /* 0=Detection on rising edge */
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# define PWR_CR2_WUPP1_FALLING (1 << 8) /* 1= Detection on falling edge */
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#define PWR_CR2_WUPP2 (1 << 9) /* Bit 9: Wakeup pin polarity bit for PA2 */
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# define PWR_CR2_WUPP2_RISING (0 << 9) /* 0=Detection on rising edge */
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# define PWR_CR2_WUPP2_FALLING (1 << 9) /* 1= Detection on falling edge */
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#define PWR_CR2_WUPP3 (1 << 10) /* Bit 10: Wakeup pin polarity bit for PC1 */
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# define PWR_CR2_WUPP3_RISING (0 << 10) /* 0=Detection on rising edge */
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# define PWR_CR2_WUPP3_FALLING (1 << 10) /* 1= Detection on falling edge */
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#define PWR_CR2_WUPP4 (1 << 11) /* Bit 11: Wakeup pin polarity bit for PC13 */
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# define PWR_CR2_WUPP4_RISING (0 << 11) /* 0=Detection on rising edge */
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# define PWR_CR2_WUPP4_FALLING (1 << 11) /* 1= Detection on falling edge */
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#define PWR_CR2_WUPP5 (1 << 12) /* Bit 12: Wakeup pin polarity bit for PI8 */
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# define PWR_CR2_WUPP5_RISING (0 << 12) /* 0=Detection on rising edge */
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# define PWR_CR2_WUPP5_FALLING (1 << 12) /* 1= Detection on falling edge */
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#define PWR_CR2_WUPP6 (1 << 13) /* Bits 13: Wakeup pin polarity bit for PI11 */
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# define PWR_CR2_WUPP6_RISING (0 << 13) /* 0=Detection on rising edge */
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# define PWR_CR2_WUPP6_FALLING (1 << 13) /* 1= Detection on falling edge */
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/* Power control/status register 2 */
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#define PWR_CSR2_WUPF1 (1 << 0) /* Bit 0: Wakeup Pin flag for PA0 */
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#define PWR_CSR2_WUPF2 (1 << 1) /* Bit 1: Wakeup Pin flag for PA2 */
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#define PWR_CSR2_WUPF3 (1 << 2) /* Bit 2: Wakeup Pin flag for PC1 */
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#define PWR_CSR2_WUPF4 (1 << 3) /* Bit 3: Wakeup Pin flag for PC13 */
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#define PWR_CSR2_WUPF5 (1 << 4) /* Bit 4: Wakeup Pin flag for PI8 */
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#define PWR_CSR2_WUPF6 (1 << 5) /* Bit 5: Wakeup Pin flag for PI11 */
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#define PWR_CSR2_EWUP1 (1 << 8) /* Bit 8: Enable wakeup pin for PA0 */
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#define PWR_CSR2_EWUP2 (1 << 9) /* Bit 9: Enable wakeup pin for PA2 */
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#define PWR_CSR2_EWUP3 (1 << 10) /* Bit 10: Enable wakeup pin for PC1 */
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#define PWR_CSR2_EWUP4 (1 << 11) /* Bit 11: Enable wakeup pin for PC13 */
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#define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */
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#define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */
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#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_PWR_H */
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113
arch/arm/src/stm32f7/stm32_pwr.h
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113
arch/arm/src/stm32f7/stm32_pwr.h
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@ -0,0 +1,113 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/stm32_pwr.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
|
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* distribution.
|
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* 3. Neither the name NuttX nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
|
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*
|
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32F7_STM32_PWR_H
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#define __ARCH_ARM_SRC_STM32F7_STM32_PWR_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdbool.h>
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#include "chip.h"
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#include "chip/stm32_pwr.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: stm32_pwr_enablebkp
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*
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* Description:
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* Enables access to the backup domain (RTC registers, RTC backup data registers
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* and backup SRAM).
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*
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* Input Parameters:
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* writable - True: enable ability to write to backup domain registers
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*
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* Returned Value:
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* True: The backup domain was previously writeable.
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*
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************************************************************************************/
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bool stm32_pwr_enablebkp(bool writable);
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/************************************************************************************
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* Name: stm32_pwr_enablebreg
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*
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* Description:
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* Enables the Backup regulator, the Backup regulator (used to maintain backup
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* SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup
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* regulator is switched off. The backup SRAM can still be used but its content will
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* be lost in the Standby and VBAT modes. Once set, the application must wait that
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* the Backup Regulator Ready flag (BRR) is set to indicate that the data written
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* into the RAM will be maintained in the Standby and VBAT modes.
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*
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* Input Parameters:
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* regon - state to set it to
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*
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* Returned Values:
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* None
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*
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************************************************************************************/
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void stm32_pwr_enablebreg(bool regon);
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_STM32F7_STM32_PWR_H */
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@ -59,6 +59,14 @@
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#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000
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/* FLASH wait states */
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#if !defined(BOARD_FLASH_WAITSTATES)
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# error BOARD_FLASH_WAITSTATES not defined
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#elif BOARD_FLASH_WAITSTATES < 0 || BOARD_FLASH_WAITSTATES > 15
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# error BOARD_FLASH_WAITSTATES is out of range
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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@ -704,17 +712,17 @@ static void stm32_stdclockconfig(void)
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if (timeout > 0)
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{
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/* Select regulator voltage output Scale 1 mode to support system
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* frequencies up to 168 MHz.
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* frequencies up to 216 MHz.
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*/
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|
||||
regval = getreg32(STM32_RCC_APB1ENR);
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
putreg32(regval, STM32_RCC_APB1ENR);
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval &= ~PWR_CR_VOS_MASK;
|
||||
regval |= PWR_CR_VOS_SCALE_1;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
regval = getreg32(STM32_PWR_CR1);
|
||||
regval &= ~PWR_CR1_VOS_MASK;
|
||||
regval |= PWR_CR1_VOS_SCALE_1;
|
||||
putreg32(regval, STM32_PWR_CR1);
|
||||
|
||||
/* Set the HCLK source/divider */
|
||||
|
||||
@ -769,29 +777,41 @@ static void stm32_stdclockconfig(void)
|
||||
{
|
||||
}
|
||||
|
||||
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
|
||||
/* Enable the Over-drive to extend the clock frequency to 216 Mhz */
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval |= PWR_CR_ODEN;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODRDY) == 0)
|
||||
regval = getreg32(STM32_PWR_CR1);
|
||||
regval |= PWR_CR1_ODEN;
|
||||
putreg32(regval, STM32_PWR_CR1);
|
||||
while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval |= PWR_CR_ODSWEN;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0)
|
||||
regval = getreg32(STM32_PWR_CR1);
|
||||
regval |= PWR_CR1_ODSWEN;
|
||||
putreg32(regval, STM32_PWR_CR1);
|
||||
while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODSWRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
|
||||
/* Configure FLASH wait states */
|
||||
|
||||
regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
|
||||
|
||||
#ifdef CONFIG_STM32F7_FLASH_PREFETCH
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
|
||||
#else
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
|
||||
/* Enable FLASH prefetch */
|
||||
|
||||
regval |= FLASH_ACR_PRFTEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARMV7M_ITCM
|
||||
/* The Flash memory interface accelerates code execution with a system of
|
||||
* instruction prefetch and cache lines on ITCM interface (ART
|
||||
* Accelerator™).
|
||||
*/
|
||||
|
||||
regval |= FLASH_ACR_ARTEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_FLASH_ACR);
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
|
||||
2
configs
2
configs
@ -1 +1 @@
|
||||
Subproject commit b10f2d0aaed2a5bc41215cb099c3bf7fb8f1f345
|
||||
Subproject commit 48042df172ab3aabf7b08ce1a75d0743a4601a57
|
||||
Loading…
Reference in New Issue
Block a user