From 5c76329d2e61697f280f8b5421a7b522f005c134 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 18 Jul 2015 11:55:35 -0600 Subject: [PATCH] STM32 F7: Add PWR register definitions --- arch/arm/src/stm32f7/chip/stm32_exti.h | 2 +- arch/arm/src/stm32f7/chip/stm32_pwr.h | 52 ++++++ .../arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h | 156 ++++++++++++++++++ arch/arm/src/stm32f7/stm32_pwr.h | 113 +++++++++++++ arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 56 +++++-- configs | 2 +- 6 files changed, 361 insertions(+), 20 deletions(-) create mode 100644 arch/arm/src/stm32f7/chip/stm32_pwr.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h create mode 100644 arch/arm/src/stm32f7/stm32_pwr.h diff --git a/arch/arm/src/stm32f7/chip/stm32_exti.h b/arch/arm/src/stm32f7/chip/stm32_exti.h index db52a202f0..1bf43de793 100644 --- a/arch/arm/src/stm32f7/chip/stm32_exti.h +++ b/arch/arm/src/stm32f7/chip/stm32_exti.h @@ -89,7 +89,7 @@ #define EXTI_RTC_TAMPER (1 << 21) /* EXTI line 21 = RTC Tamper and TimeStamp events */ #define EXTI_RTC_TIMESTAMP (1 << 21) /* EXTI line 21 = RTC Tamper and TimeStamp events */ #define EXTI_RTC_WAKEUP (1 << 22) /* EXTI line 22 = RTC Wakeup event */ -#define EXTI_RTC_WAKEUP (1 << 23) /* EXTI line 23 = LPTIM1 asynchronous event */ +#define EXTI_LPTIM1_WAKEUP (1 << 23) /* EXTI line 23 = LPTIM1 asynchronous event */ /* Interrupt mask register */ diff --git a/arch/arm/src/stm32f7/chip/stm32_pwr.h b/arch/arm/src/stm32f7/chip/stm32_pwr.h new file mode 100644 index 0000000000..427fab1f3f --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32_pwr.h @@ -0,0 +1,52 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32_pwr.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PWR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +# include "chip/stm32f74xx75xx_pwr.h" +#else +# error "Unsupported STM32 F7 part" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PWR_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h new file mode 100644 index 0000000000..0a5a0a4ea6 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h @@ -0,0 +1,156 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32_pwr.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_PWR_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_PWR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CSR1_OFFSET 0x0004 /* Power control/status register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0008 /* Power control register 1 */ +#define STM32_PWR_CSR2_OFFSET 0x000c /* Power control/status register 1 */ + +/* Register Addresses ***************************************************************/ + +#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CSR1 (STM32_PWR_BASE+STM32_PWR_CSR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CSR2 (STM32_PWR_BASE+STM32_PWR_CSR2_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* Power control register 1 */ + +#define PWR_CR1_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */ +#define PWR_CR1_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */ +#define PWR_CR1_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */ +#define PWR_CR1_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */ +#define PWR_CR1_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */ +#define PWR_CR1_PLS_MASK (7 << PWR_CR1_PLS_SHIFT) +# define PWR_CR1_2p0V (0 << PWR_CR1_PLS_SHIFT) /* 000: 2.0V */ +# define PWR_CR1_2p1V (1 << PWR_CR1_PLS_SHIFT) /* 001: 2.1V */ +# define PWR_CR1_2p3V (2 << PWR_CR1_PLS_SHIFT) /* 010: 2.3V */ +# define PWR_CR1_2p5V (3 << PWR_CR1_PLS_SHIFT) /* 011: 2.5V */ +# define PWR_CR1_2p6V (4 << PWR_CR1_PLS_SHIFT) /* 100: 2.6V */ +# define PWR_CR1_2p7V (5 << PWR_CR1_PLS_SHIFT) /* 101: 2.7V */ +# define PWR_CR1_2p8V (6 << PWR_CR1_PLS_SHIFT) /* 110: 2.8V */ +# define PWR_CR1_2p9V (7 << PWR_CR1_PLS_SHIFT) /* 111: 2.9V */ +#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ +#define PWR_CR1_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */ +#define PWR_CR1_LPUDS (1 << 10) /* Bit 10: Low-power regulator in deepsleep under-drive mode */ +#define PWR_CR1_MRUDS (1 << 11) /* Bit 11: Main regulator in deepsleep under-drive mode */ +#define PWR_CR1_ADCDC1 (1 << 13) /* Bit 13: see AN4073 for details */ +#define PWR_CR1_VOS_SHIFT (14) /* Bits 14-15: Regulator voltage scaling output selection */ +#define PWR_CR1_VOS_MASK (3 << PWR_CR1_VOS_SHIFT) +# define PWR_CR1_VOS_SCALE_3 (1 << PWR_CR1_VOS_SHIFT) /* Fmax = 144MHz */ +# define PWR_CR1_VOS_SCALE_2 (2 << PWR_CR1_VOS_SHIFT) /* Fmax = 168/180MHz */ +# define PWR_CR1_VOS_SCALE_1 (3 << PWR_CR1_VOS_SHIFT) /* Fmax = 180/216MHz */ +#define PWR_CR1_ODEN (1 << 16) /* Bit 16: Over Drive enable */ +#define PWR_CR1_ODSWEN (1 << 17) /* Bit 17: Over Drive switch enabled */ +#define PWR_CR1_UDEN_SHIFT (18) /* Bits 18-19: Under-drive enable in stop mode */ +#define PWR_CR1_UDEN_MASK (3 << PWR_CR1_UDEN_SHIFT) +# define PWR_CR1_UDEN_DISABLE (0 << PWR_CR1_UDEN_SHIFT) /* Under-drive disable */ +# define PWR_CR1_UDEN_ENABLE (3 << PWR_CR1_UDEN_SHIFT) /* Under-drive enable */ + +/* Power control/status register 1 */ + +#define PWR_CSR1_WUIF (1 << 0) /* Bit 0: Wakeup internal flag */ +#define PWR_CSR1_SBF (1 << 1) /* Bit 1: Standby flag */ +#define PWR_CSR1_PVDO (1 << 2) /* Bit 2: PVD Output */ +#define PWR_CSR1_BRR (1 << 3) /* Bit 3: Backup regulator ready */ +#define PWR_CSR1_BRE (1 << 9) /* Bit 9: Backup regulator enable */ +#define PWR_CSR1_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */ +#define PWR_CSR1_ODRDY (1 << 16) /* Bit 16: Over Drive generator ready */ +#define PWR_CSR1_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */ +#define PWR_CSR1_UDSRDY_SHIFT (18) /* Bits 18-19: Under-drive ready flag */ +#define PWR_CSR1_UDSRDY_MASK (3 << PWR_CSR1_UDSRDY_SHIFT) +# define PWR_CSR1_UDSRDY_DISAB (0 << PWR_CSR1_UDSRDY_SHIFT) /* Under-drive is disabled */ +# define PWR_CSR1_UDSRDY_STOP (3 << PWR_CSR1_UDSRDY_SHIFT) /* Under-drive mode is activated in Stop mode */ + +/* Power control register 2 */ + +#define PWR_CR2_CWUPF1 (1 << 0) /* Bit 0: Clear Wakeup Pin flag for PA0 */ +#define PWR_CR2_CWUPF2 (1 << 1) /* Bit 1: Clear Wakeup Pin flag for PA2 */ +#define PWR_CR2_CWUPF3 (1 << 2) /* Bit 2: Clear Wakeup Pin flag for PC1 */ +#define PWR_CR2_CWUPF4 (1 << 3) /* Bit 3: Clear Wakeup Pin flag for PC13 */ +#define PWR_CR2_CWUPF5 (1 << 4) /* Bit 4: Clear Wakeup Pin flag for PI8 */ +#define PWR_CR2_CWUPF6 (1 << 5) /* Bit 5: Clear Wakeup Pin flag for PI11 */ +#define PWR_CR2_WUPP1 (1 << 8) /* Bit 8: Wakeup pin polarity bit for PA0 */ +# define PWR_CR2_WUPP1_RISING (0 << 8) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP1_FALLING (1 << 8) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP2 (1 << 9) /* Bit 9: Wakeup pin polarity bit for PA2 */ +# define PWR_CR2_WUPP2_RISING (0 << 9) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP2_FALLING (1 << 9) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP3 (1 << 10) /* Bit 10: Wakeup pin polarity bit for PC1 */ +# define PWR_CR2_WUPP3_RISING (0 << 10) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP3_FALLING (1 << 10) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP4 (1 << 11) /* Bit 11: Wakeup pin polarity bit for PC13 */ +# define PWR_CR2_WUPP4_RISING (0 << 11) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP4_FALLING (1 << 11) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP5 (1 << 12) /* Bit 12: Wakeup pin polarity bit for PI8 */ +# define PWR_CR2_WUPP5_RISING (0 << 12) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP5_FALLING (1 << 12) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP6 (1 << 13) /* Bits 13: Wakeup pin polarity bit for PI11 */ +# define PWR_CR2_WUPP6_RISING (0 << 13) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP6_FALLING (1 << 13) /* 1= Detection on falling edge */ + +/* Power control/status register 2 */ + +#define PWR_CSR2_WUPF1 (1 << 0) /* Bit 0: Wakeup Pin flag for PA0 */ +#define PWR_CSR2_WUPF2 (1 << 1) /* Bit 1: Wakeup Pin flag for PA2 */ +#define PWR_CSR2_WUPF3 (1 << 2) /* Bit 2: Wakeup Pin flag for PC1 */ +#define PWR_CSR2_WUPF4 (1 << 3) /* Bit 3: Wakeup Pin flag for PC13 */ +#define PWR_CSR2_WUPF5 (1 << 4) /* Bit 4: Wakeup Pin flag for PI8 */ +#define PWR_CSR2_WUPF6 (1 << 5) /* Bit 5: Wakeup Pin flag for PI11 */ +#define PWR_CSR2_EWUP1 (1 << 8) /* Bit 8: Enable wakeup pin for PA0 */ +#define PWR_CSR2_EWUP2 (1 << 9) /* Bit 9: Enable wakeup pin for PA2 */ +#define PWR_CSR2_EWUP3 (1 << 10) /* Bit 10: Enable wakeup pin for PC1 */ +#define PWR_CSR2_EWUP4 (1 << 11) /* Bit 11: Enable wakeup pin for PC13 */ +#define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ +#define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/stm32_pwr.h b/arch/arm/src/stm32f7/stm32_pwr.h new file mode 100644 index 0000000000..3c5a30f967 --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_pwr.h @@ -0,0 +1,113 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/stm32_pwr.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32F7_STM32_PWR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "chip.h" +#include "chip/stm32_pwr.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_pwr_enablebkp + * + * Description: + * Enables access to the backup domain (RTC registers, RTC backup data registers + * and backup SRAM). + * + * Input Parameters: + * writable - True: enable ability to write to backup domain registers + * + * Returned Value: + * True: The backup domain was previously writeable. + * + ************************************************************************************/ + +bool stm32_pwr_enablebkp(bool writable); + +/************************************************************************************ + * Name: stm32_pwr_enablebreg + * + * Description: + * Enables the Backup regulator, the Backup regulator (used to maintain backup + * SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup + * regulator is switched off. The backup SRAM can still be used but its content will + * be lost in the Standby and VBAT modes. Once set, the application must wait that + * the Backup Regulator Ready flag (BRR) is set to indicate that the data written + * into the RAM will be maintained in the Standby and VBAT modes. + * + * Input Parameters: + * regon - state to set it to + * + * Returned Values: + * None + * + ************************************************************************************/ + +void stm32_pwr_enablebreg(bool regon); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_PWR_H */ diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index 93a4875218..eac8636eba 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -59,6 +59,14 @@ #define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 +/* FLASH wait states */ + +#if !defined(BOARD_FLASH_WAITSTATES) +# error BOARD_FLASH_WAITSTATES not defined +#elif BOARD_FLASH_WAITSTATES < 0 || BOARD_FLASH_WAITSTATES > 15 +# error BOARD_FLASH_WAITSTATES is out of range +#endif + /**************************************************************************** * Private Data ****************************************************************************/ @@ -704,17 +712,17 @@ static void stm32_stdclockconfig(void) if (timeout > 0) { /* Select regulator voltage output Scale 1 mode to support system - * frequencies up to 168 MHz. + * frequencies up to 216 MHz. */ regval = getreg32(STM32_RCC_APB1ENR); regval |= RCC_APB1ENR_PWREN; putreg32(regval, STM32_RCC_APB1ENR); - regval = getreg32(STM32_PWR_CR); - regval &= ~PWR_CR_VOS_MASK; - regval |= PWR_CR_VOS_SCALE_1; - putreg32(regval, STM32_PWR_CR); + regval = getreg32(STM32_PWR_CR1); + regval &= ~PWR_CR1_VOS_MASK; + regval |= PWR_CR1_VOS_SCALE_1; + putreg32(regval, STM32_PWR_CR1); /* Set the HCLK source/divider */ @@ -769,29 +777,41 @@ static void stm32_stdclockconfig(void) { } - /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ + /* Enable the Over-drive to extend the clock frequency to 216 Mhz */ - regval = getreg32(STM32_PWR_CR); - regval |= PWR_CR_ODEN; - putreg32(regval, STM32_PWR_CR); - while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODRDY) == 0) + regval = getreg32(STM32_PWR_CR1); + regval |= PWR_CR1_ODEN; + putreg32(regval, STM32_PWR_CR1); + while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODRDY) == 0) { } - regval = getreg32(STM32_PWR_CR); - regval |= PWR_CR_ODSWEN; - putreg32(regval, STM32_PWR_CR); - while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0) + regval = getreg32(STM32_PWR_CR1); + regval |= PWR_CR1_ODSWEN; + putreg32(regval, STM32_PWR_CR1); + while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODSWRDY) == 0) { } - /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */ + /* Configure FLASH wait states */ + + regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); #ifdef CONFIG_STM32F7_FLASH_PREFETCH - regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); -#else - regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); + /* Enable FLASH prefetch */ + + regval |= FLASH_ACR_PRFTEN; #endif + +#ifdef CONFIG_ARMV7M_ITCM + /* The Flash memory interface accelerates code execution with a system of + * instruction prefetch and cache lines on ITCM interface (ART + * Accelerator™). + */ + + regval |= FLASH_ACR_ARTEN; +#endif + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ diff --git a/configs b/configs index b10f2d0aae..48042df172 160000 --- a/configs +++ b/configs @@ -1 +1 @@ -Subproject commit b10f2d0aaed2a5bc41215cb099c3bf7fb8f1f345 +Subproject commit 48042df172ab3aabf7b08ce1a75d0743a4601a57