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SAMA5 UDPHS: Support USPHS clock configuration

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This commit is contained in:
Gregory Nutt 2013-09-01 11:29:51 -06:00
parent ac130dc2f3
commit 5c950889cf
5 changed files with 25 additions and 9 deletions
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2
ChangeLog
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@ -5485,4 +5485,6 @@
function. From Alan Carvalho de Assis (2013-8-31).
* drivers/usbdev/cdcacm_desc.c: Fixed some compilation errors that
only occur when dual speed support is enabled (2013-9-1).
* arch/arm/src/sama5/sam_clockconfig.c and configs/sama5d3x-ek/include/board_*mhz.h:
Add logic to support UDPHS clocking (2013-9-13).

14
arch/arm/src/sama5/sam_clockconfig.c
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@ -330,7 +330,14 @@ static inline void sam_selectplla(void)
static inline void sam_usbclockconfig(void)
{
#if defined(CONFIG_SAMA5_EHCI)
#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
defined(CONFIG_SAMA5_UDPHS)
/* We can either get the clock from the UPLL or from PLLA. In this latter
* case, however, the PLLACK frequency must be a multiple of 48MHz.
*/
#if defined(BOARD_USE_UPLL)
uint32_t regval;
/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the
@ -395,7 +402,7 @@ static inline void sam_usbclockconfig(void)
regval |= PMC_USB_USBDIV(9);
putreg32(regval, SAM_PMC_USB);
#elif defined(CONFIG_SAMA5_OHCI)
#else /* BOARD_USE_UPLL */
/* For OHCI Full-speed operations only, the user has to perform the
* following:
*
@ -415,7 +422,8 @@ static inline void sam_usbclockconfig(void)
putreg32(BOARD_OHCI_INPUT | BOARD_OHCI_DIVIDER << PMC_USB_USBDIV_SHIFT,
SAM_PMC_USB);
#endif
#endif /* BOARD_USE_UPLL */
#endif /* CONFIG_SAMA5_EHCI ||CONFIG_SAMA5_OHCI) || CONFIG_SAMA5_UDPHS */
}
/****************************************************************************

4
arch/arm/src/sama5/sam_periphclks.h
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@ -52,8 +52,8 @@
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0)
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1)
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
#define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0)
#define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0)

9
configs/sama5d3x-ek/include/board_384mhz.h
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@ -100,7 +100,9 @@
#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2
#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3
#ifdef CONFIG_SAMA5_OHCI
#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
defined(CONFIG_SAMA5_UDPHS)
/* For OHCI Full-speed operations, the user has to perform the following:
*
* 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER
@ -132,8 +134,9 @@
* frame rate. I cannot explain the factor of 2 difference.
*/
# define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA
# define BOARD_OHCI_DIVIDER (7)
# undef BOARD_USE_UPLL /* Use PLLA as source clock */
# define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA /* Input is PLLACK */
# define BOARD_OHCI_DIVIDER (7) /* Divided by 8 */
#endif
/* Resulting frequencies */

5
configs/sama5d3x-ek/include/board_396mhz.h
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@ -106,7 +106,9 @@
#define BOARD_PCK_FREQUENCY (396000000) /* CPU: PLLACK / 2 / 1 */
#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 2 / 1 / 3 */
#ifdef CONFIG_SAMA5_EHCI
#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
defined(CONFIG_SAMA5_UDPHS)
/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded
* High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL
* (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either
@ -132,6 +134,7 @@
* driver is initialized.
*/
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
#endif