SAMD20: Finishes basic clock configuration logic
This commit is contained in:
Gregory Nutt
parent
d0782933b7
commit
5caa92f463
@ -49,6 +49,7 @@
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <assert.h>
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#include "up_arch.h"
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@ -67,9 +68,167 @@
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This structure describes the configuration of on GCLK */
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#ifdef BOARD_GCLK_ENABLE
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struct sam_gclkconfig_s
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{
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uint8_t gclk; /* Clock generator */
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bool runstandby; /* Run clock in standby */
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bool output; /* Output enable */
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uint8_t clksrc; /* Encoded clock source */
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uint16_t prescaler; /* Prescaler value */
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};
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* This structure describes the configuration of every enabled GCLK */
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#ifdef BOARD_GCLK_ENABLE
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static const struct sam_gclkconfig_s g_gclkconfig[] =
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{
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/* GCLK generator 0 (Main Clock) */
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{
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.gclk = 0,
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#ifdef BOARD_GCLK0_RUN_IN_STANDBY
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.runstandby = true,
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#endif
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#ifdef BOARD_GCLK0_OUTPUT_ENABLE
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.output = true,
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#endif
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.prescaler = BOARD_GCLK0_PRESCALER,
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.clksrc = (uint8_t)(BOARD_GCLK0_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT),
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}
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/* GCLK generator 1 */
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#ifdef BOARD_GCLK1_ENABLE
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,
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{
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.gclk = 1,
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#ifdef BOARD_GCLK1_RUN_IN_STANDBY
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.runstandby = true;
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#endif
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#ifdef BOARD_GCLK1_OUTPUT_ENABLE
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.output = true;
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#endif
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.prescaler = BOARD_GCLK1_PRESCALER,
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.clksrc = (uint8_t)(BOARD_GCLK1_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT),
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}
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#endif
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/* GCLK generator 2 (RTC) */
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#ifdef BOARD_GCLK2_ENABLE
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,
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{
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.gclk = 2,
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#ifdef BOARD_GCLK2_RUN_IN_STANDBY
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.runstandby = true;
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#endif
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#ifdef BOARD_GCLK2_OUTPUT_ENABLE
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.output = true;
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#endif
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.prescaler = BOARD_GCLK2_PRESCALER,
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.clksrc = (uint8_t)(BOARD_GCLK2_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT),
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}
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#endif
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/* GCLK generator 3 */
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#ifdef BOARD_GCLK3_ENABLE
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,
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{
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.gclk = 3,
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#ifdef BOARD_GCLK3_RUN_IN_STANDBY
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.runstandby = true;
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#endif
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#ifdef BOARD_GCLK3_OUTPUT_ENABLE
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.output = true;
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#endif
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.prescaler = BOARD_GCLK3_PRESCALER,
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.clksrc = (uint8_t)(BOARD_GCLK3_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT),
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}
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#endif
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/* GCLK generator 4 */
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#ifdef BOARD_GCLK4_ENABLE
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,
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{
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.gclk = 4,
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#ifdef BOARD_GCLK4_RUN_IN_STANDBY
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.runstandby = true;
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#endif
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#ifdef BOARD_GCLK4_OUTPUT_ENABLE
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.output = true;
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#endif
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.prescaler = BOARD_GCLK4_PRESCALER,
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.clksrc = (uint8_t)(BOARD_GCLK4_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT),
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}
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#endif
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/* GCLK generator 5 */
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#ifdef BOARD_GCLK5_ENABLE
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,
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{
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.gclk = 5,
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#ifdef BOARD_GCLK5_RUN_IN_STANDBY
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.runstandby = true;
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#endif
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#ifdef BOARD_GCLK5_OUTPUT_ENABLE
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.output = true;
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#endif
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.prescaler = BOARD_GCLK5_PRESCALER,
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.clksrc = (uint8_t)(BOARD_GCLK5_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT),
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}
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#endif
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/* GCLK generator 6 */
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#ifdef BOARD_GCLK6_ENABLE
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,
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{
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.gclk = 6,
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#ifdef BOARD_GCLK6_RUN_IN_STANDBY
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.runstandby = true;
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#endif
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#ifdef BOARD_GCLK6_OUTPUT_ENABLE
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.output = true;
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#endif
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.prescaler = BOARD_GCLK6_PRESCALER,
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.clksrc = (uint8_t)(BOARD_GCLK6_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT),
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}
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#endif
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/* GCLK generator 7 */
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#ifdef BOARD_GCLK7_ENABLE
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,
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{
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.gclk = 7,
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#ifdef BOARD_GCLK7_RUN_IN_STANDBY
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.runstandby = true;
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#endif
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#ifdef BOARD_GCLK7_OUTPUT_ENABLE
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.output = true;
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#endif
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.prescaler = BOARD_GCLK7_PRESCALER,
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.clksrc = (uint8_t)(BOARD_GCLK7_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT),
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}
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#endif
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};
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#define NGCLKS_ENABLED (sizeof(g_gclkconfig) / sizeof(struct sam_gclkconfig_s))
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#endif
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/****************************************************************************
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* Private Functions
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@ -125,7 +284,7 @@ static inline void sam_flash_waitstates(void)
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*
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****************************************************************************/
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#if defined(CONFIG_SAMD_XOSC) || defined(BOARD_XOSC_ENABLE)
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#ifdef BOARD_XOSC_ENABLE
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static inline void sam_xosc_config(void)
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{
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uint16_t regval;
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@ -207,7 +366,7 @@ static inline void sam_xosc_config(void)
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*
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****************************************************************************/
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#if defined(CONFIG_SAMD_XOSC32K) || defined(BOARD_XOSC32K_ENABLE)
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#ifdef BOARD_XOSC32K_ENABLE
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static inline void sam_xosc32k_config(void)
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{
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uint16_t regval;
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@ -274,7 +433,7 @@ static inline void sam_xosc32k_config(void)
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*
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****************************************************************************/
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#if defined(CONFIG_SAMD_OSC32K) || defined(BOARD_OSC32K_ENABLE)
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#ifdef BOARD_OSC32K_ENABLE
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static inline void sam_osc32k_config(void)
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{
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uint32_t regval;
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@ -376,10 +535,15 @@ static inline void sam_osc8m_config(void)
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* BOARD_DFLL_COARSEVALUE - Value
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* BOARD_DFLL_FINEVALUE - Value
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*
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* Closed Loop mode only:
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* Open Loop mode only:
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* BOARD_DFLL_COARSEVALUE - Value
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* BOARD_DFLL_FINEVALUE - Value
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*
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* Closed loop mode only:
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* BOARD_DFLL_SRCGCLKGEN - See GCLK_CLKCTRL_GEN* definitions
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* BOARD_DFLL_MULTIPLIER - Value
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* BOARD_DFLL_MAXCOARSESTEP - Value
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* BOARD_DFLL_MAXFINESTEP - Value
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* BOARD_DFLL_MULTIPLIER - Value
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*
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* Input Parameters:
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* None
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@ -389,7 +553,7 @@ static inline void sam_osc8m_config(void)
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*
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****************************************************************************/
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#if defined(CONFIG_SAMD_DFLL) || defined(BOARD_DFLL_ENABLE)
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#ifdef BOARD_DFLL_ENABLE
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static inline void sam_dfll_config(void)
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{
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uint16_t control;
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@ -456,13 +620,13 @@ static inline void sam_dfll_config(void)
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#endif
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/****************************************************************************
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* Name: sam_gclk_config
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* Name: sam_dfll_reference
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*
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* Description:
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* Configure GCLK(s) based on settings in the board.h header file.
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* Enable DFLL reference clock if in closed loop mode.
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* Depends on:
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*
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*
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* BOARD_DFLL_SRCGCLKGEN - See GCLK_CLKCTRL_GEN* definitions
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*
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* Input Parameters:
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* None
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@ -472,13 +636,233 @@ static inline void sam_dfll_config(void)
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*
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****************************************************************************/
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#if defined(CONFIG_SAMD_GCLK) || defined(BOARD_GCLK_ENABLE)
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static inline void sam_gclk_config(void)
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#if defined(BOARD_GCLK_ENABLE) && defined(BOARD_DFLL_ENABLE) && \
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!defined(BOARD_DFLL_OPENLOOP)
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static inline void sam_dfll_reference(void)
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{
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#warning Missing logic
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uint16_t regval;
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/* Disabled the generic clock */
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regval = GCLK_CLKCTRL_GEN0;
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putreg16(regval, SAM_GCLK_CLKCTRL);
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/* Wait for the clock to become disabled */
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while ((getreg16(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) != 0);
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/* Select the configured clock generator and configure the GCLK output
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* (always Generic clock generator 0)
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*
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* NOTE: We could enable write lock here to prevent further modification
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*/
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regval = (GCLK_CLKCTRL_GEN0 | BOARD_DFLL_SRCGCLKGEN);
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putreg16(regval, SAM_GCLK_CLKCTRL);
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/* Enable the generic clock */
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regval |= GCLK_CLKCTRL_CLKEN;
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putreg16(regval, SAM_GCLK_CLKCTRL);
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}
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#else
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# define sam_gclk_config()
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# define sam_dfll_reference()
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#endif
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/****************************************************************************
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* Name: sam_config_gclks
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*
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* Description:
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* Configure a single GCLK(s) based on settings in the board.h header file.
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* Depends on:
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*
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* BOARD_GCLKn_RUN_IN_STANDBY - Boolean (defined / not defined)
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* BOARD_GCLKn_CLOCK_SOURCE - See GCLK_GENCTRL_SRC_* definitions
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* BOARD_GCLKn_PRESCALER - Value
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* BOARD_GCLKn_OUTPUT_ENABLE - Boolean (defined / not defined)
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef BOARD_GCLK_ENABLE
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static inline void sam_gclk_config(FAR const struct sam_gclkconfig_s *config)
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{
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uint32_t genctrl;
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uint32_t gendiv;
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/* Select the requested source clock for the generator */
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genctrl = ((uint32_t)config->gclk << GCLK_GENCTRL_ID_SHIFT) |
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((uint32_t)config->clksrc << GCLK_GENCTRL_SRC_SHIFT);
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gendiv = ((uint32_t)config->gclk << GCLK_GENDIV_ID_SHIFT);
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#if 0 /* Not yet supported */
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/* Configure the clock to be either high or low when disabled */
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if (config->level)
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{
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genctrl |= GCLK_GENCTRL_OOV;
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}
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#endif
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/* Configure if the clock output to I/O pin should be enabled */
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if (config->output)
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{
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genctrl |= GCLK_GENCTRL_OE;
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}
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/* Set the prescaler division factor */
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if (config->prescaler > 1)
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{
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/* Check if division is a power of two */
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if (((config->prescaler & (config->prescaler - 1)) == 0))
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{
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/* Determine the index of the highest bit set to get the
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* division factor that must be loaded into the division
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* register.
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*/
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uint32_t count = 0;
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uint32_t mask;
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for (mask = 2; mask < (uint32_t)config->prescaler; mask <<= 1)
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{
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count++;
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}
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/* Set binary divider power of 2 division factor */
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gendiv |= count << GCLK_GENDIV_DIV_SHIFT;
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genctrl |= GCLK_GENCTRL_DIVSEL;
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}
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else
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{
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/* Set integer division factor */
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gendiv |= GCLK_GENDIV_DIV((uint32_t)config->prescaler);
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/* Enable non-binary division with increased duty cycle accuracy */
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genctrl |= GCLK_GENCTRL_IDC;
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}
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}
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/* Enable or disable the clock in standby mode */
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if (config->runstandby)
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{
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genctrl |= GCLK_GENCTRL_RUNSTDBY;
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}
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/* Wait for synchronization */
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while ((getreg8(SAM_GCLK_STATUS) & GCLK_STATUS_SYNCBUSY) != 0);
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/* Select the generator */
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putreg32(((uint32_t)config->gclk << GCLK_GENDIV_ID_SHIFT),
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SAM_GCLK_GENDIV);
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/* Wait for synchronization */
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while ((getreg8(SAM_GCLK_STATUS) & GCLK_STATUS_SYNCBUSY) != 0);
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/* Write the new generator configuration */
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putreg32(gendiv, SAM_GCLK_GENDIV);
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/* Wait for synchronization */
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while ((getreg8(SAM_GCLK_STATUS) & GCLK_STATUS_SYNCBUSY) != 0);
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/* Enable the clock generator */
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genctrl |= GCLK_GENCTRL_GENEN;
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putreg16(genctrl, SAM_GCLK_GENCTRL);
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/* Wait for synchronization */
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while ((getreg8(SAM_GCLK_STATUS) & GCLK_STATUS_SYNCBUSY) != 0);
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}
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#endif
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/****************************************************************************
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* Name: sam_config_gclks
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*
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* Description:
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* Configure GCLK(s) based on settings in the board.h header file.
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* Depends on:
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*
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* Global enable/disable.
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*
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* BOARD_GCLK_ENABLE - Boolean (defined / not defined)
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*
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* For n=1-7:
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* BOARD_GCLKn_ENABLE - Boolean (defined / not defined)
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*
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* For n=0-8:
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* BOARD_GCLKn_RUN_IN_STANDBY - Boolean (defined / not defined)
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* BOARD_GCLKn_CLOCK_SOURCE - See GCLK_GENCTRL_SRC_* definitions
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* BOARD_GCLKn_PRESCALER - Value
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* BOARD_GCLKn_OUTPUT_ENABLE - Boolean (defined / not defined)
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef BOARD_GCLK_ENABLE
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static inline void sam_config_gclks(void)
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{
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uint32_t regval;
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int i;
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/* Turn on the GCLK interface clock */
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regval = getreg32(SAM_PM_APBAMASK);
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regval |= PM_APBAMASK_GCLK;
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putreg32(regval, SAM_PM_APBAMASK);
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/* Reset the GCLK module */
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putreg8(GCLK_CTRL_SWRST, SAM_GCLK_CTRL);
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/* Wait for the reset to complete */
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while ((getreg8(SAM_GCLK_CTRL) & GCLK_CTRL_SWRST) != 0);
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/* Configure all GCLK generators, skipping GLCK_MAIN which is configured
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* below.
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*/
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for (i = 1; i < NGCLKS_ENABLED; i++)
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{
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sam_gclk_config(&g_gclkconfig[i]);
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}
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/* Enable DFLL reference clock if the DFLL is enabled in closed loop mode */
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sam_dfll_reference();
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/* Configure the GCLK_MAIN last as it may depend on the DFLL or other
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* generators
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*/
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sam_gclk_config(&g_gclkconfig[0]);
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}
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#else
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# define sam_config_gclks()
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#endif
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/****************************************************************************
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@ -579,7 +963,7 @@ void sam_clockconfig(void)
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/* Configure GCLK(s) */
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sam_gclk_config();
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sam_config_gclks();
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/* Set CPU and BUS clock dividers */
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@ -54,17 +54,23 @@
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* Nominal frequencies of on-chip RC oscillators. These are *not* configurable
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* but appear here for use in frequency calculations. NOTE: These frequencies
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* may vary with temperature changes.
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*/
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#define BOARD_OSCULP32K_FREQUENCY 32000 /* 32kHz ultra-low-power internal oscillator */
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/* The SAMD20 Xplained Pro has one on-board crystal:
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/* Overview
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*
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* OSC8M Output = 8MHz
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* `- GCLK1 Input = 8MHz Prescaler = 1 output = 8MHz
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* `- DFLL Input = 8MHz Multiplier = 6 output = 48MHz
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* `- PM Input = 48Mhz CPU divider = 1 CPU frequency = 48MHz
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* APBA divider = 1 APBA frequency = 48MHz
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* APBB divider = 1 APBB frequency = 48MHz
|
||||
* APBC divider = 1 APBC frequency = 48MHz
|
||||
*
|
||||
* The SAMD20 Xplained Pro has one on-board crystal:
|
||||
*
|
||||
* XC101 32.768KHz XOSC32
|
||||
*
|
||||
* REVISIT: Not currently used, may want to use as GCLK1 source with
|
||||
* DFLL multiplier of ((48000000+16384)/32768) = 1465 which would yield
|
||||
* a clock of 48,005,120 MHz.
|
||||
*/
|
||||
|
||||
/* XOSC Configuration -- Not available
|
||||
@ -137,17 +143,22 @@
|
||||
|
||||
#define BOARD_OSC8M_PRESCALER SYSCTRL_OSC8M_PRESC_DIV1
|
||||
#define BOARD_OSC8M_ONDEMAND 1
|
||||
#undef BOARD_OSC8M_RUNINSTANDBY
|
||||
#undef BOARD_OSC8M_RUNINSTANDBY
|
||||
|
||||
#define BOARD_OSC8M_FREQUENCY 8000000 /* 8MHz high-accuracy internal oscillator */
|
||||
|
||||
/* OSCULP32K Configuration -- not used. */
|
||||
|
||||
#define BOARD_OSCULP32K_FREQUENCY 32000 /* 32kHz ultra-low-power internal oscillator */
|
||||
|
||||
/* Digital Frequency Locked Loop configuration. In closed-loop mode, the
|
||||
* DFLL output frequency (Fdfll) is given by:
|
||||
*
|
||||
* Fdfll = DFLLmul * Frefclk
|
||||
* = (48000000/32768) * 32768 = 48MHz
|
||||
* = 6 * 8000000 = 48MHz
|
||||
*
|
||||
* Where the reference clock is always the Generic Clock Channel 0 output.
|
||||
* Where the reference clock is Generic Clock Channel 0 output of GLCK1.
|
||||
* GCLCK1 provides OSC8M, undivided.
|
||||
*
|
||||
* When operating in open-loop mode, the output frequency of the DFLL will
|
||||
* be determined by the values written to the DFLL Coarse Value bit group
|
||||
@ -163,14 +174,20 @@
|
||||
* BOARD_DFLL_FINEVALUE - Value
|
||||
*
|
||||
* Open Loop mode only:
|
||||
* BOARD_DFLL_COARSEVALUE - Value
|
||||
* BOARD_DFLL_FINEVALUE - Value
|
||||
*
|
||||
* Closed loop mode only:
|
||||
* BOARD_DFLL_SRCGCLKGEN - See GCLK_CLKCTRL_GEN* definitions
|
||||
* BOARD_DFLL_MULTIPLIER - Value
|
||||
* BOARD_DFLL_MAXCOARSESTEP - Value
|
||||
* BOARD_DFLL_MAXFINESTEP - Value
|
||||
* BOARD_DFLL_MULTIPLIER - Value
|
||||
*
|
||||
* BOARD_DFLL_FREQUENCY - The resulting frequency
|
||||
*/
|
||||
|
||||
#define BOARD_DFLL_OPENLOOP 1
|
||||
#define BOARD_DFLL_ENABLE 1
|
||||
#undef BOARD_DFLL_OPENLOOP
|
||||
#undef BOARD_DFLL_ONDEMAND
|
||||
#undef BOARD_DFLL_RUNINSTANDBY
|
||||
|
||||
@ -181,7 +198,7 @@
|
||||
|
||||
/* DFLL closed loop mode configuration */
|
||||
|
||||
#define BOARD_DFLL_SRCGCLKGEN 1 /* GCLK generator channel 1 */
|
||||
#define BOARD_DFLL_SRCGCLKGEN GCLK_CLKCTRL_GEN1
|
||||
#define BOARD_DFLL_MULTIPLIER 6
|
||||
#define BOARD_DFLL_QUICKLOCK 1
|
||||
#define BOARD_DFLL_TRACKAFTERFINELOCK 1
|
||||
@ -192,30 +209,103 @@
|
||||
|
||||
#define BOARD_DFLL_FREQUENCY (48000000)
|
||||
|
||||
/* The source of the main clock is always GLCK_MAIN. Also called GCLKGEN[0], this is
|
||||
/* GCLK Configuration
|
||||
*
|
||||
* Global enable/disable.
|
||||
*
|
||||
* BOARD_GCLK_ENABLE - Boolean (defined / not defined)
|
||||
*
|
||||
* For n=1-7:
|
||||
* BOARD_GCLKn_ENABLE - Boolean (defined / not defined)
|
||||
*
|
||||
* For n=0-8:
|
||||
* BOARD_GCLKn_RUN_IN_STANDBY - Boolean (defined / not defined)
|
||||
* BOARD_GCLKn_CLOCK_SOURCE - See GCLK_GENCTRL_SRC_* definitions
|
||||
* BOARD_GCLKn_PRESCALER - Value
|
||||
* BOARD_GCLKn_OUTPUT_ENABLE - Boolean (defined / not defined)
|
||||
*/
|
||||
|
||||
#define BOARD_GCLK_ENABLE 1
|
||||
|
||||
/* GCLK generator 0 (Main Clock) - Source is the DFLL */
|
||||
|
||||
#undef BOARD_GCLK0_RUN_IN_STANDBY
|
||||
#define BOARD_GCLK0_CLOCK_SOURCE GCLK_GENCTRL_SRC_DFLL48M
|
||||
#define BOARD_GCLK0_PRESCALER 1
|
||||
#undef BOARD_GCLK0_OUTPUT_ENABLE
|
||||
#define BOARD_GCLK0_FREQUENCY (BOARD_DFLL_FREQUENCY / BOARD_GCLK0_PRESCALER)
|
||||
|
||||
/* Configure GCLK generator 1 - Drives the DFLL */
|
||||
|
||||
#define BOARD_GCLK1_ENABLE 1
|
||||
#undef BOARD_GCLK1_RUN_IN_STANDBY
|
||||
#define BOARD_GCLK1_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
|
||||
#define BOARD_GCLK1_PRESCALER 1
|
||||
#undef BOARD_GCLK1_OUTPUT_ENABLE
|
||||
#define BOARD_GCLK1_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK1_PRESCALER)
|
||||
|
||||
/* Configure GCLK generator 2 (RTC) */
|
||||
|
||||
#undef BOARD_GCLK2_ENABLE
|
||||
#undef BOARD_GCLK2_RUN_IN_STANDBY
|
||||
#define BOARD_GCLK2_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC32K
|
||||
#define BOARD_GCLK2_PRESCALER 32
|
||||
#undef BOARD_GCLK2_OUTPUT_ENABLE
|
||||
#define BOARD_GCLK2_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK2_PRESCALER)
|
||||
|
||||
/* Configure GCLK generator 3 */
|
||||
|
||||
#undef BOARD_GCLK3_ENABLE
|
||||
#undef BOARD_GCLK3_RUN_IN_STANDBY
|
||||
#define BOARD_GCLK3_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
|
||||
#define BOARD_GCLK3_PRESCALER 1
|
||||
#undef BOARD_GCLK3_OUTPUT_ENABLE
|
||||
#define BOARD_GCLK3_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK3_PRESCALER)
|
||||
|
||||
/* Configure GCLK generator 4 */
|
||||
|
||||
#undef BOARD_GCLK4_ENABLE
|
||||
#undef BOARD_GCLK4_RUN_IN_STANDBY
|
||||
#define BOARD_GCLK4_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
|
||||
#define BOARD_GCLK4_PRESCALER 1
|
||||
#undef BOARD_GCLK4_OUTPUT_ENABLE
|
||||
#define BOARD_GCLK4_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK4_PRESCALER)
|
||||
|
||||
/* Configure GCLK generator 5 */
|
||||
|
||||
#undef BOARD_GCLK5_ENABLE
|
||||
#undef BOARD_GCLK5_RUN_IN_STANDBY
|
||||
#define BOARD_GCLK5_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
|
||||
#define BOARD_GCLK5_PRESCALER 1
|
||||
#undef BOARD_GCLK5_OUTPUT_ENABLE
|
||||
#define BOARD_GCLK5_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK5_PRESCALER)
|
||||
|
||||
/* Configure GCLK generator 6 */
|
||||
|
||||
#undef BOARD_GCLK6_ENABLE
|
||||
#undef BOARD_GCLK6_RUN_IN_STANDBY
|
||||
#define BOARD_GCLK6_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
|
||||
#define BOARD_GCLK6_PRESCALER 1
|
||||
#undef BOARD_GCLK6_OUTPUT_ENABLE
|
||||
#define BOARD_GCLK6_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK6_PRESCALER)
|
||||
|
||||
/* Configure GCLK generator 7 */
|
||||
|
||||
#undef BOARD_GCLK7_ENABLE
|
||||
#undef BOARD_GCLK7_RUN_IN_STANDBY
|
||||
#define BOARD_GCLK7_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
|
||||
#define BOARD_GCLK7_PRESCALER 1
|
||||
#undef BOARD_GCLK7_OUTPUT_ENABLE
|
||||
#define BOARD_GCLK7_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK7_PRESCALER)
|
||||
|
||||
/* The source of the main clock is always GCLK_MAIN. Also called GCLKGEN[0], this is
|
||||
* the clock feeding the Power Manager. The Power Manager, in turn, generates main
|
||||
* clock which is divided down to produce the CPU, AHB, and APB clocks.
|
||||
*
|
||||
* The main clock is initially OSC8M divided by 8. But will be reconfigured here to
|
||||
* be DFLL48M.
|
||||
*
|
||||
* Select the OSC8M as the source of the GLCK_MAIN. Options (define one):
|
||||
*
|
||||
* BOARD_GLCK_MAIN_SRC_XOSC - XOSC oscillator output
|
||||
* BOARD_GLCK_MAIN_SRC_GCLKIN - Generator input pad
|
||||
* BOARD_GLCK_MAIN_SRC_GCLKGEN1 - Generic clock generator 1 output
|
||||
* BOARD_GLCK_MAIN_SRC_OSCULP32K - OSCULP32K oscillator output
|
||||
* BOARD_GLCK_MAIN_SRC_OSC32K - OSC32K oscillator output
|
||||
* BOARD_GLCK_MAIN_SRC_XOSC32K - XOSC32K oscillator output
|
||||
* BOARD_GLCK_MAIN_SRC_OSC8M - OSC8M oscillator output
|
||||
* BOARD_GLCK_MAIN_SRC_DFLL48M - DFLL48M output
|
||||
*
|
||||
* Fglckmain = Frefclk / Divider
|
||||
* The main clock is initially OSC8M divided by 8.
|
||||
*/
|
||||
|
||||
#define BOARD_GLCK_MAIN_SRC_OSC8M 1
|
||||
#define BOARD_GLCK_MAIN_DIVIDER 1
|
||||
#define BOARD_GLCK_MAIN_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GLCK_MAIN_DIVIDER)
|
||||
#define BOARD_GCLK_MAIN_FREQUENCY BOARD_GCLK0_FREQUENCY
|
||||
|
||||
/* Main clock dividers
|
||||
*
|
||||
@ -238,7 +328,7 @@
|
||||
|
||||
/* Resulting frequencies */
|
||||
|
||||
#define BOARD_MCK_FREQUENCY (BOARD_GLCK_MAIN_FREQUENCY)
|
||||
#define BOARD_MCK_FREQUENCY (BOARD_GCLK_MAIN_FREQUENCY)
|
||||
#define BOARD_CPU_FREQUENCY (BOARD_MCK_FREQUENCY)
|
||||
#define BOARD_PBA_FREQUENCY (BOARD_MCK_FREQUENCY)
|
||||
#define BOARD_PBB_FREQUENCY (BOARD_MCK_FREQUENCY)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user