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Rename STM32F0L0 to STM32F0L0G0 since it now alsow supports the STM32G0 thanks to Mateusz Szafoni's contribution

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Squashed commit of the following:

    arch/arm:  Rename include/stm32f0l0 and src/stm32f0l0 to stm32f0l0g0.

    Change all occurrences of lower-case stm32f0l0 to stm32f0l0g0.

    Change all occurrences of upper-case STM32F0L0 to STM32F0L0G0.
This commit is contained in:
Gregory Nutt 2019-05-27 08:16:24 -06:00
parent dbb40e5fe7
commit 5cdd038df2
142 changed files with 1560 additions and 1560 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/Kconfig
View File

@ -684,7 +684,7 @@ config ARCH_CHIP
default "sam34" if ARCH_CHIP_SAM34
default "samv7" if ARCH_CHIP_SAMV7
default "stm32" if ARCH_CHIP_STM32
default "stm32f0l0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0
default "stm32f0l0g0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0
default "stm32f7" if ARCH_CHIP_STM32F7
default "stm32h7" if ARCH_CHIP_STM32H7
default "stm32l4" if ARCH_CHIP_STM32L4
@ -917,7 +917,7 @@ if ARCH_CHIP_STM32
source arch/arm/src/stm32/Kconfig
endif
if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0
source arch/arm/src/stm32f0l0/Kconfig
source arch/arm/src/stm32f0l0g0/Kconfig
endif
if ARCH_CHIP_STM32F7
source arch/arm/src/stm32f7/Kconfig

8
arch/arm/include/stm32f0l0/chip.h → arch/arm/include/stm32f0l0g0/chip.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/include/stm32f0l0/chip.h
* arch/arm/include/stm32f0l0g0/chip.h
*
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H
#define __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H
#define __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H
/************************************************************************************
* Included Files
@ -552,4 +552,4 @@
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H */

14
arch/arm/include/stm32f0l0/irq.h → arch/arm/include/stm32f0l0g0/irq.h
View File

@ -38,8 +38,8 @@
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H
/****************************************************************************
* Included Files
@ -48,7 +48,7 @@
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#include <arch/stm32f0l0/chip.h>
#include <arch/stm32f0l0g0/chip.h>
/****************************************************************************
* Pre-processor Definitions
@ -79,11 +79,11 @@
/* Include MCU-specific external interrupt definitions */
#if defined(CONFIG_ARCH_CHIP_STM32F0)
# include <arch/stm32f0l0/stm32f0_irq.h>
# include <arch/stm32f0l0g0/stm32f0_irq.h>
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
# include <arch/stm32f0l0/stm32l0_irq.h>
# include <arch/stm32f0l0g0/stm32l0_irq.h>
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
# include <arch/stm32f0l0/stm32g0_irq.h>
# include <arch/stm32f0l0g0/stm32g0_irq.h>
#else
# error Unrecognized STM32 Cortex M0 family
#endif
@ -119,4 +119,4 @@ extern "C"
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H */

12
arch/arm/include/stm32f0l0/stm32f0_irq.h → arch/arm/include/stm32f0l0g0/stm32f0_irq.h
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/stm32f0l0/stm32f0_irq.h
* arch/arm/include/stm32f0l0g0/stm32f0_irq.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -38,8 +38,8 @@
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H
/****************************************************************************
* Included Files
@ -47,7 +47,7 @@
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <arch/stm32f0l0/chip.h>
#include <arch/stm32f0l0g0/chip.h>
/****************************************************************************
* Pre-processor Definitions
@ -58,7 +58,7 @@
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32f0l0/irq.h
* in nuttx/arch/arm/include/stm32f0l0g0/irq.h
*/
#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: WWDG */
@ -142,4 +142,4 @@ extern "C"
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H */

12
arch/arm/include/stm32f0l0/stm32g0_irq.h → arch/arm/include/stm32f0l0g0/stm32g0_irq.h
View File

@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/include/stm32f0l0/stm32g0_irq.h
* arch/arm/include/stm32f0l0g0/stm32g0_irq.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -35,8 +35,8 @@
/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32G0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32G0_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H
/****************************************************************************************************
* Included Files
@ -44,7 +44,7 @@
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <arch/stm32f0l0/chip.h>
#include <arch/stm32f0l0g0/chip.h>
/****************************************************************************************************
* Pre-processor Definitions
@ -55,7 +55,7 @@
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32f0l0/irq.h
* in nuttx/arch/arm/include/stm32f0l0g0/irq.h
*/
#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */
@ -139,4 +139,4 @@ extern "C"
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32G0_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H */

12
arch/arm/include/stm32f0l0/stm32l0_irq.h → arch/arm/include/stm32f0l0g0/stm32l0_irq.h
View File

@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/include/stm32f0l0/stm32l0_irq.h
* arch/arm/include/stm32f0l0g0/stm32l0_irq.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -35,8 +35,8 @@
/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H
/****************************************************************************************************
* Included Files
@ -44,7 +44,7 @@
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <arch/stm32f0l0/chip.h>
#include <arch/stm32f0l0g0/chip.h>
/****************************************************************************************************
* Pre-processor Definitions
@ -55,7 +55,7 @@
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32f0l0/irq.h
* in nuttx/arch/arm/include/stm32f0l0g0/irq.h
*/
#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */
@ -129,4 +129,4 @@ extern "C"
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H */

1134
arch/arm/src/stm32f0l0/Kconfig → arch/arm/src/stm32f0l0g0/Kconfig
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File diff suppressed because it is too large Load Diff

24
arch/arm/src/stm32f0l0/Make.defs → arch/arm/src/stm32f0l0g0/Make.defs
View File

@ -1,5 +1,5 @@
############################################################################
# arch/arm/src/stm32f0l0/Make.defs
# arch/arm/src/stm32f0l0g0/Make.defs
#
# Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
@ -66,11 +66,11 @@ CHIP_ASRCS =
CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c
CHIP_CSRCS += stm32_lse.c stm32_lowputc.c stm32_serial.c stm32_rcc.c
ifeq ($(CONFIG_STM32F0L0_DMA),y)
ifeq ($(CONFIG_STM32F0L0G0_DMA),y)
CHIP_CSRCS += stm32_dma_v1.c
endif
ifeq ($(CONFIG_STM32F0L0_PWR),y)
ifeq ($(CONFIG_STM32F0L0G0_PWR),y)
CHIP_CSRCS += stm32_pwr.c
endif
@ -86,7 +86,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += stm32_userspace.c
endif
ifeq ($(CONFIG_STM32F0L0_GPIOIRQ),y)
ifeq ($(CONFIG_STM32F0L0G0_GPIOIRQ),y)
CHIP_CSRCS += stm32_gpioint.c
endif
@ -94,34 +94,34 @@ ifeq ($(CONFIG_ARCH_IRQPRIO),y)
CHIP_CSRCS += stm32_irqprio.c
endif
ifeq ($(CONFIG_STM32F0L0_HAVE_HSI48),y)
ifeq ($(CONFIG_STM32F0L0G0_HAVE_HSI48),y)
CHIP_CSRCS += stm32_hsi48.c
endif
ifeq ($(CONFIG_STM32F0L0_USB),y)
ifeq ($(CONFIG_STM32F0L0G0_USB),y)
CHIP_CSRCS += stm32_usbdev.c
endif
ifeq ($(CONFIG_STM32F0L0_I2C),y)
ifeq ($(CONFIG_STM32F0L0G0_I2C),y)
CHIP_CSRCS += stm32_i2c.c
endif
ifeq ($(CONFIG_STM32F0L0_SPI),y)
ifeq ($(CONFIG_STM32F0L0G0_SPI),y)
CHIP_CSRCS += stm32_spi.c
endif
ifeq ($(CONFIG_STM32F0L0_PWM),y)
ifeq ($(CONFIG_STM32F0L0G0_PWM),y)
CHIP_CSRCS += stm32_pwm.c
endif
ifeq ($(CONFIG_STM32F0L0_ADC),y)
ifeq ($(CONFIG_STM32F0L0G0_ADC),y)
CHIP_CSRCS += stm32_adc.c
endif
ifeq ($(CONFIG_STM32F0L0_AES),y)
ifeq ($(CONFIG_STM32F0L0G0_AES),y)
CHIP_CSRCS += stm32_aes.c
endif
ifeq ($(CONFIG_STM32F0L0_RNG),y)
ifeq ($(CONFIG_STM32F0L0G0_RNG),y)
CHIP_CSRCS += stm32_rng.c
endif

10
arch/arm/src/stm32f0l0/chip.h → arch/arm/src/stm32f0l0g0/chip.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/chip.h
* arch/arm/src/stm32f0l0g0/chip.h
*
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H
/************************************************************************************
* Included Files
@ -46,7 +46,7 @@
/* Include the chip capabilities file */
#include <arch/stm32f0l0/chip.h>
#include <arch/stm32f0l0g0/chip.h>
#define ARMV6M_PERIPHERAL_INTERRUPTS 32
@ -56,4 +56,4 @@
#include "hardware/stm32_memorymap.h"
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H */

14
arch/arm/src/stm32f0l0/hardware/stm32_adc.h → arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h
View File

@ -1,5 +1,5 @@
/********************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_adc.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
********************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_ADC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H
/********************************************************************************
* Included Files
@ -62,7 +62,7 @@
/* Support for ADC clock prescaler */
#if defined(CONFIG_STM32F0L0_STM32L0) || defined(CONFIG_STM32F0L0_STM32G0)
#if defined(CONFIG_STM32F0L0G0_STM32L0) || defined(CONFIG_STM32F0L0G0_STM32G0)
# define HAVE_ADC_PRE
#else
# undef HAVE_ADC_PRE
@ -70,7 +70,7 @@
/* Support for LCD voltage */
#ifdef CONFIG_STM32F0L0_HAVE_LCD
#ifdef CONFIG_STM32F0L0G0_HAVE_LCD
# define HAVE_ADC_VLCD
#else
# undef HAVE_ADC_VLCD
@ -78,7 +78,7 @@
/* Supprot for Low frequency mode */
#ifdef CONFIG_STM32F0L0_ENERGYLITE
#ifdef CONFIG_STM32F0L0G0_ENERGYLITE
# define HAVE_ADC_LFM
#else
# undef HAVE_ADC_LFM
@ -268,4 +268,4 @@
# define ADC_CCR_LFMEN (1 << 25) /* Bit 25: Low Frequency Mode enable */
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_ADC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_aes.h → arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h
View File

@ -1,5 +1,5 @@
/********************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_aes.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h
*
* Copyright (C) 2015 Haltian Ltd. All rights reserved.
* Author: Juha Niskanen <juha.niskanen@haltian.com>
@ -33,8 +33,8 @@
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_AES_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_AES_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H
/********************************************************************************************
* Included Files
@ -111,4 +111,4 @@
#define AES_SR_RDERR (1 << 1) /* Read Error Flag */
#define AES_SR_WRERR (1 << 2) /* Write Error Flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_AES_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_can.h → arch/arm/src/stm32f0l0g0/hardware/stm32_can.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_can.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_can.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CAN_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CAN_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H
/************************************************************************************
* Included Files
@ -466,4 +466,4 @@
#define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */
#define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CAN_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_comp.h → arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_comp.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_COMP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_COMP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H
/************************************************************************************
* Included Files
@ -135,4 +135,4 @@
#define COMP_CSR_COMP2OUT (1 << 14) /* Bit 14: Comparator 1 output */
#define COMP_CSR_COMP2LOCK (1 << 15) /* Bit 15: Comparator 1 lock */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_COMP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_crc.h → arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h
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@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_crc.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRC_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H
/************************************************************************************
* Included Files
@ -87,4 +87,4 @@
# define CRC_CR_REVIN_WORD (3 << CRC_CR_REVIN_SHIFT) /* 11: reversal done by word */
#define CRC_CR_REVOUT (1 << 7) /* This bit controls the reversal of the bit order of the output data */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_crs.h → arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_crs.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRS_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRS_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H
/************************************************************************************
* Pre-processor Definitions
@ -112,4 +112,4 @@
#define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */
#define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRS_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_dac.h → arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h
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@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_dac.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DAC_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DAC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H
/************************************************************************************
* Included Files
@ -215,4 +215,4 @@
#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */
#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DAC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h → arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMA_V1_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMA_V1_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H
/************************************************************************************
* Pre-processor Definitions
@ -550,4 +550,4 @@
# error "Unknown DMA channel assignments"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMA_V1_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H */

10
arch/arm/src/stm32f0l0/hardware/stm32_dmamux.h → arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_dmamux.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMAMUX_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMAMUX_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H
/************************************************************************************
* Included Files
@ -153,10 +153,10 @@
/* Import DMAMUX map */
#if defined(CONFIG_STM32F0L0_STM32G0)
#if defined(CONFIG_STM32F0L0G0_STM32G0)
# include "chip/stm32g0_dmamux.h"
#else
# error "Unsupported STM32 M0 sub family"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMAMUX_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_exti.h → arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_exti.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h
*
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_EXTI_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H
/************************************************************************************
* Included Files
@ -54,4 +54,4 @@
# error "Unrecognized STM32 M0 EXTI"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_EXTI_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_flash.h → arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_flash.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h
*
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_FLASH_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_FLASH_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H
/************************************************************************************
* Included Files
@ -53,4 +53,4 @@
# error "Unsupported STM32 M0 FLASH"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_FLASH_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_gpio.h → arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_gpio.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_GPIO_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_GPIO_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H
/************************************************************************************
* Pre-processor Definitions
@ -355,4 +355,4 @@
#define GPIO_BRR(n) (1 << (n))
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_GPIO_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_i2c.h → arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_i2c.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_I2C_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H
/************************************************************************************
* Pre-processor Definitions
@ -235,4 +235,4 @@
#define I2C_TXDR_MASK (0xff)
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_I2C_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H */

12
arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h → arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h
*
* Copyright (C) 2017, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H
/************************************************************************************
* Included Files
@ -44,8 +44,8 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F0L0_STM32F05X) || defined(CONFIG_STM32F0L0_STM32F07X) || \
defined(CONFIG_STM32F0L0_STM32F09X)
#if defined(CONFIG_STM32F0L0G0_STM32F05X) || defined(CONFIG_STM32F0L0G0_STM32F07X) || \
defined(CONFIG_STM32F0L0G0_STM32F09X)
# include "hardware/stm32f05xf07xf09x_memorymap.h"
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
# include "hardware/stm32l0_memorymap.h"
@ -55,4 +55,4 @@
# error "Unsupported STM32 M0 memory map"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H */

14
arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h → arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H
/************************************************************************************
* Included Files
@ -43,11 +43,11 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F0L0_STM32F05X)
#if defined(CONFIG_STM32F0L0G0_STM32F05X)
# include "hardware/stm32f05x_pinmap.h"
#elif defined(CONFIG_STM32F0L0_STM32F07X)
#elif defined(CONFIG_STM32F0L0G0_STM32F07X)
# include "hardware/stm32f07x_pinmap.h"
#elif defined(CONFIG_STM32F0L0_STM32F09X)
#elif defined(CONFIG_STM32F0L0G0_STM32F09X)
# include "hardware/stm32f09x_pinmap.h"
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
# include "hardware/stm32l0_pinmap.h"
@ -57,4 +57,4 @@
# error "Unsupported STM32 M0 pin map"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_pwr.h → arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_pwr.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h
*
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H
/************************************************************************************
* Included Files
@ -54,5 +54,5 @@
# error "Unsupported STM32 M0 PWR"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_rcc.h → arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_rcc.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h
*
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RCC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H
/************************************************************************************
* Included Files
@ -54,4 +54,4 @@
# error "Unsupported STM32 M0 RCC"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RCC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_rng.h → arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_rng.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h
*
* Copyright (C) 2012 Max Holtzberg. All rights reserved.
* Author: Max Holtzberg <mh@uvc.de>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RNG_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RNG_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H
/************************************************************************************
* Included Files
@ -75,4 +75,4 @@
#define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */
#define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RNG_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h → arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RTCC_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RTCC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H
/************************************************************************************
* Pre-processor Definitions
@ -321,4 +321,4 @@
#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */
#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RTCC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H */

12
arch/arm/src/stm32f0l0/hardware/stm32_spi.h → arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_spi.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SPI_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SPI_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H
/************************************************************************************
* Included Files
@ -45,9 +45,9 @@
/* Select STM32 SPI IP core */
#if defined(CONFIG_STM32F0L0_STM32F0)
#if defined(CONFIG_STM32F0L0G0_STM32F0)
# define HAVE_IP_SPI_V2
#elif defined(CONFIG_STM32F0L0_STM32L0)
#elif defined(CONFIG_STM32F0L0G0_STM32L0)
# define HAVE_IP_SPI_V1
#else
# error Unsupported family
@ -269,4 +269,4 @@
#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SPI_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h → arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h
View File

@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h
*
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SYSCFG_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H
/****************************************************************************************************
* Included Files
@ -54,4 +54,4 @@
# error "Unsupported STM32 M0 SYSCFG"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SYSCFG_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_tim.h → arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h
View File

@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_tim.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_TIM_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_TIM_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H
/****************************************************************************************************
* Pre-processor Definitions
@ -49,4 +49,4 @@
/* Register Bitfield Definitions ********************************************************************/
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_TIM_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H */

12
arch/arm/src/stm32f0l0/hardware/stm32_uart.h → arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_uart.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h
*
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H
/************************************************************************************
* Included Files
@ -44,12 +44,12 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F0L0_HAVE_IP_USART_V1)
#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1)
# include "hardware/stm32_uart_v1.h"
#elif defined(CONFIG_STM32F0L0_HAVE_IP_USART_V2)
#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2)
# include "hardware/stm32_uart_v2.h"
#else
# error "Unsupported STM32 M0 USART"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_uart_v1.h → arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_uart_v1.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h
*
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_UART_V1_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_UART_V1_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V1_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V1_H
/************************************************************************************
* Included Files
@ -313,4 +313,4 @@
#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_TDR_MASK (0xff << USART_TDR_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_V1_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_uart_v2.h → arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_uart_v2.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_UART_V2_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_UART_V2_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V2_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V2_H
/************************************************************************************
* Included Files
@ -360,4 +360,4 @@
# define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */
# define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_V2_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H */

12
arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h → arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_USBDEV_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_USBDEV_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H
/************************************************************************************
* Included Files
@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include <chip.h>
#ifdef CONFIG_STM32F0L0_HAVE_USBDEV
#ifdef CONFIG_STM32F0L0G0_HAVE_USBDEV
/************************************************************************************
* Pre-processor Definitions
@ -260,5 +260,5 @@
#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */
#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT)
#endif /* CONFIG_STM32F0L0_HAVE_USBDEV */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_USBDEV_H */
#endif /* CONFIG_STM32F0L0G0_HAVE_USBDEV */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H */

8
arch/arm/src/stm32f0l0/hardware/stm32_wdt.h → arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_wdt.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_WDG_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_WDG_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H
/************************************************************************************
* Included Files
@ -139,4 +139,4 @@
#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_WDG_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */

8
arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h → arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h
* arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F05X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F05X_PINMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H
/************************************************************************************
* Included Files
@ -133,4 +133,4 @@
#define GPIO_I2C2_SCL (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN10)
#define GPIO_I2C2_SDA (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN11)
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F05X_PINMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H */

8
arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h → arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h
* arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H
/************************************************************************************
* Pre-processor Definitions
@ -154,4 +154,4 @@
#define STM32_SCS_BASE 0xe000e000
#define STM32_DEBUGMCU_BASE 0xe0042000
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H */

8
arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h → arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h
* arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F07X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F07X_PINMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H
/************************************************************************************
* Included Files
@ -397,4 +397,4 @@
#define GPIO_USB_NOE (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN13)
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F07X_PINMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H */

8
arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h → arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h
* arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F09X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F09X_PINMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H
/************************************************************************************
* Included Files
@ -427,4 +427,4 @@
#define GPIO_USART8_RX_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN13)
#define GPIO_USART8_CK_RST (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN14)
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F09X_PINMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H */

8
arch/arm/src/stm32f0l0/hardware/stm32f0_exti.h → arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_exti.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h
*
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_EXTI_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H
/************************************************************************************
* Included Files
@ -128,4 +128,4 @@
#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
#define EXTI_PR_MASK STM32_EXTI_MASK
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_EXTI_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H */

8
arch/arm/src/stm32f0l0/hardware/stm32f0_flash.h → arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32f0_flash.h
* arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_FLASH_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_FLASH_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H
/************************************************************************************
* Included Files
@ -105,4 +105,4 @@
#define FLASH_OBR_ /* To be provided */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_FLASH_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H */

8
arch/arm/src/stm32f0l0/hardware/stm32f0_pwr.h → arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32f0_pwr.h
* arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h
*
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_PWR_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_PWR_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H
/************************************************************************************
* Included Files
@ -97,4 +97,4 @@
#define PWR_CSR_EWUP7 (1 << 14) /* Bit 14: Enable WKUP7 pin */
#define PWR_CSR_EWUP8 (1 << 15) /* Bit 15: Enable WKUP8 pin */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_PWR_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H */

8
arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h → arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h
* arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_RCC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H
/************************************************************************************
* Pre-processor Definitions
@ -393,4 +393,4 @@
#define RCC_CR2_HSI48CAL_SHIFT (24) /* Bits 24-31: HSI48 factory clock calibration */
#define RCC_CR2_HSI48CAL_MASK (0xff << RCC_CR2_HSI48CAL_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_RCC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H */

8
arch/arm/src/stm32f0l0/hardware/stm32f0_syscfg.h → arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h
View File

@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32f0_syscfg.h
* arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h
*
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_SYSCFG_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H
/****************************************************************************************************
* Included Files
@ -388,4 +388,4 @@
#define SYSCFG_ITLINE30_CEC (1 << 0) /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */
#define SYSCFG_ITLINE30_CAN (1 << 1) /* Bit 1: CAN interrupt request pending */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_SYSCFG_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H */

8
arch/arm/src/stm32f0l0/hardware/stm32g0_dmamux.h → arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32g0_dmamux.h
* arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_DMAMUX_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_DMAMUX_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H
/************************************************************************************
* Included Files
@ -71,4 +71,4 @@
/* TODO: ... */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_DMAMUX_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H */

8
arch/arm/src/stm32f0l0/hardware/stm32g0_exti.h → arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32g0_exti.h
* arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_EXTI_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H
/************************************************************************************
* Included Files
@ -100,4 +100,4 @@
/* TODO */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_EXTI_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H */

8
arch/arm/src/stm32f0l0/hardware/stm32g0_flash.h → arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32g0_flash.h
* arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_FLASH_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_FLASH_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H
/************************************************************************************
* Included Files
@ -104,4 +104,4 @@
/* TODO */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_FLASH_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H */

8
arch/arm/src/stm32f0l0/hardware/stm32g0_memorymap.h → arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32g0_memorymap.h
* arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32G0_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32G0_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32G0_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32G0_MEMORYMAP_H
/************************************************************************************
* Pre-processor Definitions
@ -137,4 +137,4 @@
#define STM32_SCS_BASE 0xe000e000
#define STM32_DEBUGMCU_BASE 0xe0042000
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32G0_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32G0_MEMORYMAP_H */

8
arch/arm/src/stm32f0l0/hardware/stm32g0_pinmap.h → arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32g0_pinmap.h
* arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PINMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H
/************************************************************************************
* Included Files
@ -119,4 +119,4 @@
/* TODO: CEC */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PINMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H */

8
arch/arm/src/stm32f0l0/hardware/stm32g0_pwr.h → arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32g0_pwr.h
* arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PWR_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PWR_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H
/************************************************************************************
* Included Files
@ -183,4 +183,4 @@
#define PWR_SCR_CWUF5 (1 << 4) /* Bit 4: Clear wakeup flag 5 */
#define PWR_SCR_CSBF (1 << 8) /* Bit 8: Clear standby flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PWR_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H */

8
arch/arm/src/stm32f0l0/hardware/stm32g0_rcc.h → arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32g0_rcc.h
* arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_RCC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H
/************************************************************************************
* Pre-processor Definitions
@ -359,4 +359,4 @@
#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */
#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_RCC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H */

8
arch/arm/src/stm32f0l0/hardware/stm32g0_syscfg.h → arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h
View File

@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32g0_syscfg.h
* arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -33,8 +33,8 @@
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_SYSCFG_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H
/****************************************************************************************************
* Included Files
@ -313,4 +313,4 @@
#define SYSCFG_ITLINE30_RNG (1 << 0) /* Bit 0: RNG interrupt request pending */
#define SYSCFG_ITLINE30_AES (1 << 1) /* Bit 1: AES interrupt request pending */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_SYSCFG_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H */

8
arch/arm/src/stm32f0l0/hardware/stm32l0_exti.h → arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_exti.h
* arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_EXTI_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H
/************************************************************************************
* Included Files
@ -126,4 +126,4 @@
#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
#define EXTI_PR_MASK STM32_EXTI_MASK
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_EXTI_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H */

8
arch/arm/src/stm32f0l0/hardware/stm32l0_flash.h → arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32l0_flash.h
* arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_FLASH_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_FLASH_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H
/************************************************************************************
* Included Files
@ -114,4 +114,4 @@
#define FLASH_SR_OPTVERRUSR (1 << 12) /* Bit 12: Option UserValidity Error */
#define FLASH_SR_RDERR (1 << 13) /* Bit 13: Read protected error */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_FLASH_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H */

8
arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h → arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h
* arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H
/************************************************************************************
* Pre-processor Definitions
@ -127,4 +127,4 @@
#define STM32_GPIOE_BASE 0x50001000 /* 0x50001000-0x500013ff GPIO Port E */
#define STM32_GPIOH_BASE 0x50001c00 /* 0x50001c00-0x50001fff GPIO Port H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H */

8
arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h → arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h
* arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PINMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H
/************************************************************************************
* Included Files
@ -339,4 +339,4 @@
/* TODO: LPUART */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PINMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H */

8
arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h → arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h
* arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PWR_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PWR_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H
/************************************************************************************
* Included Files
@ -102,4 +102,4 @@
#define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */
#define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PWR_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H */

8
arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h → arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h
* arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_RCC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H
/************************************************************************************
* Pre-processor Definitions
@ -551,4 +551,4 @@
#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */
#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_RCC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H */

8
arch/arm/src/stm32f0l0/hardware/stm32l0_syscfg.h → arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h
View File

@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32l0_syscfg.h
* arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -33,8 +33,8 @@
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_SYSCFG_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H
/****************************************************************************************************
* Included Files
@ -145,4 +145,4 @@
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 configuration */
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_SYSCFG_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H */

8
arch/arm/src/stm32f0l0/stm32.h → arch/arm/src/stm32f0l0g0/stm32.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/stm32.h
* arch/arm/src/stm32f0l0g0/stm32.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_H
/************************************************************************************
* Included Files
@ -64,4 +64,4 @@
#include "stm32_lowputc.h"
#include "stm32_adc.h"
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_H */

80
arch/arm/src/stm32f0l0/stm32_adc.c → arch/arm/src/stm32f0l0g0/stm32_adc.c
View File

@ -67,13 +67,13 @@
/* STM32 ADC "lower-half" support must be enabled */
#ifdef CONFIG_STM32F0L0_ADC
#ifdef CONFIG_STM32F0L0G0_ADC
/* Some ADC peripheral must be enabled */
#if defined(CONFIG_STM32F0L0_ADC1)
#if defined(CONFIG_STM32F0L0G0_ADC1)
#if !defined(CONFIG_STM32F0L0_STM32L0)
#if !defined(CONFIG_STM32F0L0G0_STM32L0)
# error Only L0 supported for now
#endif
@ -123,7 +123,7 @@
/* G0 support additional sample time selection 2 */
#if defined(CONFIG_STM32F0L0_STM32G0)
#if defined(CONFIG_STM32F0L0G0_STM32G0)
# define ADC_HAVE_SMPR_SMP2
#endif
@ -145,7 +145,7 @@
* NOTE: this value can be obtained from SMPRx register description (ST manual)
*/
#if defined(CONFIG_STM32F0L0_STM32F0) || defined(CONFIG_STM32F0L0_STM32L0)
#if defined(CONFIG_STM32F0L0G0_STM32F0) || defined(CONFIG_STM32F0L0G0_STM32L0)
# define ADC_CHANNELS_NUMBER 19
#else
# error "Not supported"
@ -196,10 +196,10 @@ struct adccmn_data_s
struct stm32_dev_s
{
#ifdef CONFIG_STM32F0L0_ADC_LL_OPS
#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
FAR const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */
#endif
#if !defined(CONFIG_STM32F0L0_ADC_NOIRQ) | defined(ADC_HAVE_DMA)
#if !defined(CONFIG_STM32F0L0G0_ADC_NOIRQ) | defined(ADC_HAVE_DMA)
FAR const struct adc_callback_s *cb;
uint8_t irq; /* Interrupt generated by this ADC block */
#endif
@ -220,7 +220,7 @@ struct stm32_dev_s
# endif
bool hasdma; /* True: This channel supports DMA */
#endif
#ifdef CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
/* Sample time selection. These bits must be written only when ADON=0.
* REVISIT: this takes too much space. We need only 3 bits per channel.
*/
@ -295,10 +295,10 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset);
/* ADC Interrupt Handler */
#ifndef CONFIG_STM32F0L0_ADC_NOIRQ
#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
static int adc_interrupt(FAR struct adc_dev_s *dev);
static int adc1_interrupt(int irq, FAR void *context, FAR void *arg);
#endif /* CONFIG_STM32F0L0_ADC_NOIRQ */
#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */
/* ADC Driver Methods */
@ -349,7 +349,7 @@ static int adc_extcfg_set(FAR struct adc_dev_s *dev, uint32_t extcfg);
static void adc_dumpregs(FAR struct stm32_dev_s *priv);
#ifdef CONFIG_STM32F0L0_ADC_LL_OPS
#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
static void adc_llops_intack(FAR struct stm32_adc_dev_s *dev, uint32_t source);
static void adc_llops_inten(FAR struct stm32_adc_dev_s *dev, uint32_t source);
static void adc_llops_intdis(FAR struct stm32_adc_dev_s *dev, uint32_t source);
@ -360,7 +360,7 @@ static void adc_llops_reg_startconv(FAR struct stm32_adc_dev_s *dev, bool enable
static int adc_llops_regbufregister(FAR struct stm32_adc_dev_s *dev,
uint16_t *buffer, uint8_t len);
# endif
# ifdef CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME
# ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
static void adc_sampletime_set(FAR struct stm32_adc_dev_s *dev,
FAR struct adc_sample_time_s *time_samples);
static void adc_sampletime_write(FAR struct stm32_adc_dev_s *dev);
@ -386,7 +386,7 @@ static const struct adc_ops_s g_adcops =
/* Publicly visible ADC lower-half operations */
#ifdef CONFIG_STM32F0L0_ADC_LL_OPS
#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
static const struct stm32_adc_ops_s g_adc_llops =
{
.int_ack = adc_llops_intack,
@ -398,7 +398,7 @@ static const struct stm32_adc_ops_s g_adc_llops =
# ifdef ADC_HAVE_DMA
.regbuf_reg = adc_llops_regbufregister,
# endif
# ifdef CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME
# ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
.stime_set = adc_sampletime_set,
.stime_write = adc_sampletime_write,
# endif
@ -408,37 +408,37 @@ static const struct stm32_adc_ops_s g_adc_llops =
/* ADC1 state */
#ifdef CONFIG_STM32F0L0_ADC1
#ifdef CONFIG_STM32F0L0G0_ADC1
static struct stm32_dev_s g_adcpriv1 =
{
#ifdef CONFIG_STM32F0L0_ADC_LL_OPS
#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
.llops = &g_adc_llops,
#endif
#ifndef CONFIG_STM32F0L0_ADC_NOIRQ
#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
.irq = STM32_IRQ_ADC,
.isr = adc1_interrupt,
#endif /* CONFIG_STM32F0L0_ADC_NOIRQ */
#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */
#ifdef HAVE_ADC_CMN_DATA
.cmn = &ADC1CMN_DATA,
#endif
.intf = 1,
#ifdef HAVE_ADC_RESOLUTION
.resolution = CONFIG_STM32F0L0_ADC1_RESOLUTION,
.resolution = CONFIG_STM32F0L0G0_ADC1_RESOLUTION,
#endif
.base = STM32_ADC1_BASE,
#ifdef ADC1_HAVE_EXTCFG
.extcfg = ADC1_EXTCFG_VALUE,
#endif
#ifdef ADC1_HAVE_TIMER
.trigger = CONFIG_STM32F0L0_ADC1_TIMTRIG,
.trigger = CONFIG_STM32F0L0G0_ADC1_TIMTRIG,
.tbase = ADC1_TIMER_BASE,
.pclck = ADC1_TIMER_PCLK_FREQUENCY,
.freq = CONFIG_STM32F0L0_ADC1_SAMPLE_FREQUENCY,
.freq = CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY,
#endif
#ifdef ADC1_HAVE_DMA
.dmachan = ADC1_DMA_CHAN,
# ifdef ADC_HAVE_DMACFG
.dmacfg = CONFIG_STM32F0L0_ADC1_DMA_CFG,
.dmacfg = CONFIG_STM32F0L0G0_ADC1_DMA_CFG,
# endif
.hasdma = true,
#endif
@ -886,7 +886,7 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset)
switch (priv->intf)
{
#if defined(CONFIG_STM32F0L0_ADC1)
#if defined(CONFIG_STM32F0L0G0_ADC1)
case 1:
{
adcbit = RCC_RSTR_ADC1RST;
@ -1028,7 +1028,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
static int adc_bind(FAR struct adc_dev_s *dev,
FAR const struct adc_callback_s *callback)
{
#ifndef CONFIG_STM32F0L0_ADC_NOIRQ
#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
DEBUGASSERT(priv != NULL);
@ -1131,7 +1131,7 @@ static void adc_sampletime_cfg(FAR struct adc_dev_s *dev)
* During sample cycles channel selection bits must remain unchanged.
*/
#ifdef CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
adc_sampletime_write((FAR struct stm32_adc_dev_s *)dev);
#else
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
@ -1398,15 +1398,15 @@ static void adc_reset(FAR struct adc_dev_s *dev)
static int adc_setup(FAR struct adc_dev_s *dev)
{
#if !defined(CONFIG_STM32F0L0_ADC_NOIRQ) || defined(HAVE_ADC_CMN_DATA) || \
defined(ADC_HAVE_TIMER) || !defined(CONFIG_STM32F0L0_ADC_NO_STARTUP_CONV)
#if !defined(CONFIG_STM32F0L0G0_ADC_NOIRQ) || defined(HAVE_ADC_CMN_DATA) || \
defined(ADC_HAVE_TIMER) || !defined(CONFIG_STM32F0L0G0_ADC_NO_STARTUP_CONV)
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
#endif
int ret = OK;
/* Attach the ADC interrupt */
#ifndef CONFIG_STM32F0L0_ADC_NOIRQ
#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
ret = irq_attach(priv->irq, priv->isr, NULL);
if (ret < 0)
{
@ -1444,7 +1444,7 @@ static int adc_setup(FAR struct adc_dev_s *dev)
* or later with ANIOC_TRIGGER ioctl call.
*/
#ifndef CONFIG_STM32F0L0_ADC_NO_STARTUP_CONV
#ifndef CONFIG_STM32F0L0G0_ADC_NO_STARTUP_CONV
/* Start regular conversion */
adc_reg_startconv(priv, true);
@ -1453,7 +1453,7 @@ static int adc_setup(FAR struct adc_dev_s *dev)
/* Enable the ADC interrupt */
#ifndef CONFIG_STM32F0L0_ADC_NOIRQ
#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq);
up_enable_irq(priv->irq);
#endif
@ -1490,7 +1490,7 @@ static void adc_shutdown(FAR struct adc_dev_s *dev)
adc_enable(priv, false);
#ifndef CONFIG_STM32F0L0_ADC_NOIRQ
#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
/* Disable ADC interrupts and detach the ADC interrupt handler */
up_disable_irq(priv->irq);
@ -2051,7 +2051,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
return ret;
}
#ifndef CONFIG_STM32F0L0_ADC_NOIRQ
#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
/****************************************************************************
* Name: adc_interrupt
@ -2158,9 +2158,9 @@ static int adc1_interrupt(int irq, FAR void *context, FAR void *arg)
return OK;
}
#endif /* CONFIG_STM32F0L0_ADC_NOIRQ */
#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */
#ifdef CONFIG_STM32F0L0_ADC_LL_OPS
#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
/****************************************************************************
* Name: adc_llops_intack
@ -2283,7 +2283,7 @@ static int adc_llops_regbufregister(FAR struct stm32_adc_dev_s *dev,
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
static void adc_sampletime_write(FAR struct stm32_adc_dev_s *dev)
{
#error TODO adc_sampletime_write
@ -2315,7 +2315,7 @@ void adc_sampletime_set(FAR struct stm32_adc_dev_s *dev,
{
#error TODO adc_sampletime_write
}
#endif /* CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME */
#endif /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */
/****************************************************************************
* Name: adc_llops_dumpregs
@ -2328,7 +2328,7 @@ static void adc_llops_dumpregs(FAR struct stm32_adc_dev_s *dev)
adc_dumpregs(priv);
}
#endif /* CONFIG_STM32F0L0_ADC_LL_OPS */
#endif /* CONFIG_STM32F0L0G0_ADC_LL_OPS */
/****************************************************************************
* Public Functions
@ -2360,7 +2360,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
switch (intf)
{
#ifdef CONFIG_STM32F0L0_ADC1
#ifdef CONFIG_STM32F0L0G0_ADC1
case 1:
{
ainfo("ADC1 selected\n");
@ -2396,5 +2396,5 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
return dev;
}
#endif /* CONFIG_STM32F0L0_ADC1 */
#endif /* CONFIG_STM32F0L0_ADC */
#endif /* CONFIG_STM32F0L0G0_ADC1 */
#endif /* CONFIG_STM32F0L0G0_ADC */

34
arch/arm/src/stm32f0l0/stm32_adc.h → arch/arm/src/stm32f0l0g0/stm32_adc.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_ADC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H
/************************************************************************************
* Included Files
@ -61,19 +61,19 @@
/* Up to 1 ADC interfaces are supported */
#if STM32_NADC < 1
# undef CONFIG_STM32F0L0_ADC1
# undef CONFIG_STM32F0L0G0_ADC1
#endif
#if defined(CONFIG_STM32F0L0_ADC1)
#if defined(CONFIG_STM32F0L0G0_ADC1)
/* DMA support */
#undef ADC_HAVE_DMA
#if defined(CONFIG_STM32F0L0_ADC1_DMA)
#if defined(CONFIG_STM32F0L0G0_ADC1_DMA)
# define ADC_HAVE_DMA 1
#endif
#ifdef CONFIG_STM32F0L0_ADC1_DMA
#ifdef CONFIG_STM32F0L0G0_ADC1_DMA
# define ADC1_HAVE_DMA 1
#else
# undef ADC1_HAVE_DMA
@ -81,7 +81,7 @@
/* EXTSEL */
#if defined(CONFIG_STM32F0L0_STM32F0)
#if defined(CONFIG_STM32F0L0G0_STM32F0)
# define ADC1_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_TRG0
# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1
# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2
@ -90,7 +90,7 @@
/* TRG5 reserved */
/* TRG6 reserved */
/* TRG7 reserved */
#elif defined(CONFIG_STM32F0L0_STM32L0)
#elif defined(CONFIG_STM32F0L0G0_STM32L0)
/* TRG0 reserved */
# define ADC1_EXTSEL_T21CC2 ADC12_CFGR1_EXTSEL_TRG1
# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2
@ -99,7 +99,7 @@
# define ADC1_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_TRG5
/* TRG6 reserved */
# define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7
#elif defined(CONFIG_STM32F0L0_STM32G0)
#elif defined(CONFIG_STM32F0L0G0_STM32G0)
# define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_TRG0
# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1
# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2
@ -203,9 +203,9 @@ enum stm32_adc_resoluton_e
ADC_RESOLUTION_6BIT = 3 /* 6 bit */
};
#ifdef CONFIG_STM32F0L0_ADC_LL_OPS
#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
#ifdef CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
/* Channel and sample time pair */
@ -230,7 +230,7 @@ struct adc_sample_time_s
* same value of the sample time */
uint8_t all_ch_sample_time:3; /* Sample time for all channels */
};
#endif /* CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME */
#endif /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */
/* This structure provides the publicly visable representation of the
* "lower-half" ADC driver structure.
@ -277,7 +277,7 @@ struct stm32_adc_ops_s
void (*reg_startconv)(FAR struct stm32_adc_dev_s *dev, bool state);
#ifdef CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
/* Set ADC sample time */
void (*stime_set)(FAR struct stm32_adc_dev_s *dev,
@ -291,7 +291,7 @@ struct stm32_adc_ops_s
void (*dump_regs)(FAR struct stm32_adc_dev_s *dev);
};
#endif /* CONFIG_STM32F0L0_ADC_LL_OPS */
#endif /* CONFIG_STM32F0L0G0_ADC_LL_OPS */
/************************************************************************************
* Public Function Prototypes
@ -330,7 +330,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
* Name: stm32_adc_llops_get
************************************************************************************/
#ifdef CONFIG_STM32F0L0_ADC_LL_OPS
#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
FAR const struct stm32_adc_ops_s *stm32_adc_llops_get(FAR struct adc_dev_s *dev);
#endif
@ -340,5 +340,5 @@ FAR const struct stm32_adc_ops_s *stm32_adc_llops_get(FAR struct adc_dev_s *dev)
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32F0L0_ADC1 */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_ADC_H */
#endif /* CONFIG_STM32F0L0G0_ADC1 */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H */

2
arch/arm/src/stm32f0l0/stm32_aes.c → arch/arm/src/stm32f0l0g0/stm32_aes.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_aes.c
* arch/arm/src/stm32f0l0g0/stm32_aes.c
*
* Copyright (C) 2015 Haltian Ltd. All rights reserved.
* Author: Juha Niskanen <juha.niskanen@haltian.com>

8
arch/arm/src/stm32f0l0/stm32_aes.h → arch/arm/src/stm32f0l0g0/stm32_aes.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/stm32_aes.h
* arch/arm/src/stm32f0l0g0/stm32_aes.h
*
* Copyright (C) 2014 Haltian Ltd. All rights reserved.
* Author: Juha Niskanen <juha.niskanen@haltian.com>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_AES_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_AES_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H
/************************************************************************************
* Included Files
@ -60,4 +60,4 @@
* Inline Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_AES_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H */

8
arch/arm/src/stm32f0l0/stm32_dma.h → arch/arm/src/stm32f0l0g0/stm32_dma.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_DMA_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_DMA_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H
/************************************************************************************
* Included Files
@ -245,7 +245,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle);
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0_DMACAPABLE
#ifdef CONFIG_STM32F0L0G0_DMACAPABLE
bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr);
#else
# define stm32_dmacapable(maddr, count, ccr) (true)
@ -331,4 +331,4 @@ uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_DMA_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H */

4
arch/arm/src/stm32f0l0/stm32_dma_v1.c → arch/arm/src/stm32f0l0g0/stm32_dma_v1.c
View File

@ -64,7 +64,7 @@
* the DMA requests for each channel.
*/
#ifdef CONFIG_STM32F0L0_HAVE_DMAMUX
#ifdef CONFIG_STM32F0L0G0_HAVE_DMAMUX
# error DMAMUX not supported yet
#endif
@ -655,7 +655,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0_DMACAPABLE
#ifdef CONFIG_STM32F0L0G0_DMACAPABLE
bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
{
uint32_t transfer_size;

8
arch/arm/src/stm32f0l0/stm32_exti.h → arch/arm/src/stm32f0l0g0/stm32_exti.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/stm32_exti.h
* arch/arm/src/stm32f0l0g0/stm32_exti.h
*
* Copyright (C) 2009, 2012, 2015, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_EXTI_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H
/************************************************************************************
* Included Files
@ -140,4 +140,4 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event,
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_EXTI_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H */

8
arch/arm/src/stm32f0l0/stm32_exti_gpio.c → arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_exti_gpio.c
* arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c
*
* Copyright (C) 2009, 2011-2012, 2015, 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2011 Uros Platise. All rights reserved.
@ -59,7 +59,7 @@
* Pre-processor Definitions
************************************************************************************/
#if defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V2)
#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2)
# define STM32_EXTI_FTSR STM32_EXTI_FTSR1
# define STM32_EXTI_RTSR STM32_EXTI_RTSR1
# define STM32_EXTI_IMR STM32_EXTI_IMR1
@ -92,7 +92,7 @@ static struct gpio_callback_s g_gpio_callbacks[16];
* Interrupt Service Routines - Dispatchers
****************************************************************************/
#if defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V1)
#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1)
static int stm32_exti_multiisr(int irq, void *context, void *arg,
int first, int last)
{
@ -136,7 +136,7 @@ static int stm32_exti_multiisr(int irq, void *context, void *arg,
return ret;
}
#elif defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V2)
#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2)
static int stm32_exti_multiisr(int irq, void *context, void *arg,
int first, int last)
{

12
arch/arm/src/stm32f0l0/stm32_gpio.c → arch/arm/src/stm32f0l0g0/stm32_gpio.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_gpio.c
* arch/arm/src/stm32f0l0g0/stm32_gpio.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -47,16 +47,16 @@
#include <debug.h>
#include <arch/irq.h>
#include <arch/stm32f0l0/chip.h>
#include <arch/stm32f0l0g0/chip.h>
#include "up_arch.h"
#include "chip.h"
#include "stm32_gpio.h"
#if defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V1)
#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1)
# include "hardware/stm32_syscfg.h"
#elif defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V2)
#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2)
# include "hardware/stm32_exti.h"
#endif
@ -321,7 +321,7 @@ int stm32_configgpio(uint32_t cfgset)
uint32_t regaddr;
int shift;
#if defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V1)
#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1)
/* Set the bits in the SYSCFG EXTICR register */
regaddr = STM32_SYSCFG_EXTICR(pin);
@ -331,7 +331,7 @@ int stm32_configgpio(uint32_t cfgset)
regval |= (((uint32_t)port) << shift);
putreg32(regval, regaddr);
#elif defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V2)
#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2)
/* Set the bits in the EXTI EXTICR register */
regaddr = STM32_EXTI_EXTICR(pin);

10
arch/arm/src/stm32f0l0/stm32_gpio.h → arch/arm/src/stm32f0l0g0/stm32_gpio.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/stm32_gpio.h
* arch/arm/src/stm32f0l0g0/stm32_gpio.h
*
* Copyright (C) 2009, 2011-2012, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved.
@ -36,8 +36,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H
/************************************************************************************
* Included Files
@ -51,7 +51,7 @@
#endif
#include <nuttx/irq.h>
#include <arch/stm32f0l0/chip.h>
#include <arch/stm32f0l0g0/chip.h>
#include "chip.h"
#include "hardware/stm32_gpio.h"
@ -370,4 +370,4 @@ void stm32_gpioinit(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H */

2
arch/arm/src/stm32f0l0/stm32_hsi48.c → arch/arm/src/stm32f0l0g0/stm32_hsi48.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_hsi48.c
* arch/arm/src/stm32f0l0g0/stm32_hsi48.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>

12
arch/arm/src/stm32f0l0/stm32_hsi48.h → arch/arm/src/stm32f0l0g0/stm32_hsi48.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/stm32_hsi48.h
* arch/arm/src/stm32f0l0g0/stm32_hsi48.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.orgr>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H
/************************************************************************************
* Included Files
@ -43,7 +43,7 @@
#include <nuttx/config.h>
#ifdef CONFIG_STM32F0L0_HAVE_HSI48
#ifdef CONFIG_STM32F0L0G0_HAVE_HSI48
/************************************************************************************
* Public Types
@ -106,5 +106,5 @@ void stm32_enable_hsi48(enum syncsrc_e syncsrc);
void stm32_disable_hsi48(void);
#endif /* CONFIG_STM32F0L0_HAVE_HSI48 */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H */
#endif /* CONFIG_STM32F0L0G0_HAVE_HSI48 */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H */

98
arch/arm/src/stm32f0l0/stm32_i2c.c → arch/arm/src/stm32f0l0g0/stm32_i2c.c
View File

@ -158,21 +158,21 @@
*
* To use this driver, enable the following configuration variable:
*
* CONFIG_STM32F0L0_I2C1
* CONFIG_STM32F0L0_I2C2
* CONFIG_STM32F0L0_I2C3
* CONFIG_STM32F0L0_I2C4
* CONFIG_STM32F0L0G0_I2C1
* CONFIG_STM32F0L0G0_I2C2
* CONFIG_STM32F0L0G0_I2C3
* CONFIG_STM32F0L0G0_I2C4
*
* To configure the ISR timeout using fixed values (CONFIG_STM32F0L0_I2C_DYNTIMEO=n):
* To configure the ISR timeout using fixed values (CONFIG_STM32F0L0G0_I2C_DYNTIMEO=n):
*
* CONFIG_STM32F0L0_I2CTIMEOSEC (Timeout in seconds)
* CONFIG_STM32F0L0_I2CTIMEOMS (Timeout in milliseconds)
* CONFIG_STM32F0L0_I2CTIMEOTICKS (Timeout in ticks)
* CONFIG_STM32F0L0G0_I2CTIMEOSEC (Timeout in seconds)
* CONFIG_STM32F0L0G0_I2CTIMEOMS (Timeout in milliseconds)
* CONFIG_STM32F0L0G0_I2CTIMEOTICKS (Timeout in ticks)
*
* To configure the ISR timeout using dynamic values (CONFIG_STM32F0L0_I2C_DYNTIMEO=y):
* To configure the ISR timeout using dynamic values (CONFIG_STM32F0L0G0_I2C_DYNTIMEO=y):
*
* CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE (Timeout in microseconds per byte)
* CONFIG_STM32F0L0_I2C_DYNTIMEO_STARTSTOP (Timeout for start/stop in milliseconds)
* CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE (Timeout in microseconds per byte)
* CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP (Timeout for start/stop in milliseconds)
*
* Debugging output enabled with:
*
@ -243,8 +243,8 @@
/* At least one I2C peripheral must be enabled */
#if defined(CONFIG_STM32F0L0_I2C1) || defined(CONFIG_STM32F0L0_I2C2) || \
defined(CONFIG_STM32F0L0_I2C3) || defined(CONFIG_STM32F0L0_I2C4)
#if defined(CONFIG_STM32F0L0G0_I2C1) || defined(CONFIG_STM32F0L0G0_I2C2) || \
defined(CONFIG_STM32F0L0G0_I2C3) || defined(CONFIG_STM32F0L0G0_I2C4)
/************************************************************************************
* Pre-processor Definitions
@ -260,25 +260,25 @@
/* Interrupt wait timeout in seconds and milliseconds */
#if !defined(CONFIG_STM32F0L0_I2CTIMEOSEC) && !defined(CONFIG_STM32F0L0_I2CTIMEOMS)
# define CONFIG_STM32F0L0_I2CTIMEOSEC 0
# define CONFIG_STM32F0L0_I2CTIMEOMS 500 /* Default is 500 milliseconds */
#if !defined(CONFIG_STM32F0L0G0_I2CTIMEOSEC) && !defined(CONFIG_STM32F0L0G0_I2CTIMEOMS)
# define CONFIG_STM32F0L0G0_I2CTIMEOSEC 0
# define CONFIG_STM32F0L0G0_I2CTIMEOMS 500 /* Default is 500 milliseconds */
# warning "Using Default 500 Ms Timeout"
#elif !defined(CONFIG_STM32F0L0_I2CTIMEOSEC)
# define CONFIG_STM32F0L0_I2CTIMEOSEC 0 /* User provided milliseconds */
#elif !defined(CONFIG_STM32F0L0_I2CTIMEOMS)
# define CONFIG_STM32F0L0_I2CTIMEOMS 0 /* User provided seconds */
#elif !defined(CONFIG_STM32F0L0G0_I2CTIMEOSEC)
# define CONFIG_STM32F0L0G0_I2CTIMEOSEC 0 /* User provided milliseconds */
#elif !defined(CONFIG_STM32F0L0G0_I2CTIMEOMS)
# define CONFIG_STM32F0L0G0_I2CTIMEOMS 0 /* User provided seconds */
#endif
/* Interrupt wait time timeout in system timer ticks */
#ifndef CONFIG_STM32F0L0_I2CTIMEOTICKS
# define CONFIG_STM32F0L0_I2CTIMEOTICKS \
(SEC2TICK(CONFIG_STM32F0L0_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F0L0_I2CTIMEOMS))
#ifndef CONFIG_STM32F0L0G0_I2CTIMEOTICKS
# define CONFIG_STM32F0L0G0_I2CTIMEOTICKS \
(SEC2TICK(CONFIG_STM32F0L0G0_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F0L0G0_I2CTIMEOMS))
#endif
#ifndef CONFIG_STM32F0L0_I2C_DYNTIMEO_STARTSTOP
# define CONFIG_STM32F0L0_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F0L0_I2CTIMEOTICKS)
#ifndef CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP
# define CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F0L0G0_I2CTIMEOTICKS)
#endif
/* Macros to convert a I2C pin to a GPIO output */
@ -445,9 +445,9 @@ static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv,
uint8_t offset, uint32_t clearbits,
uint32_t setbits);
static inline void stm32_i2c_sem_wait(FAR struct i2c_master_s *dev);
#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO
#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs);
#endif /* CONFIG_STM32F0L0_I2C_DYNTIMEO */
#endif /* CONFIG_STM32F0L0G0_I2C_DYNTIMEO */
static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv);
static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv);
static inline void stm32_i2c_sem_post(FAR struct i2c_master_s *dev);
@ -488,7 +488,7 @@ static int stm32_i2c_pm_prepare(FAR struct pm_callback_s *cb, int domain,
* Private Data
************************************************************************************/
#ifdef CONFIG_STM32F0L0_I2C1
#ifdef CONFIG_STM32F0L0G0_I2C1
static const struct stm32_i2c_config_s stm32_i2c1_config =
{
.base = STM32_I2C1_BASE,
@ -519,7 +519,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv =
};
#endif
#ifdef CONFIG_STM32F0L0_I2C2
#ifdef CONFIG_STM32F0L0G0_I2C2
static const struct stm32_i2c_config_s stm32_i2c2_config =
{
.base = STM32_I2C2_BASE,
@ -550,7 +550,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv =
};
#endif
#ifdef CONFIG_STM32F0L0_I2C3
#ifdef CONFIG_STM32F0L0G0_I2C3
static const struct stm32_i2c_config_s stm32_i2c3_config =
{
.base = STM32_I2C3_BASE,
@ -581,7 +581,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
};
#endif
#ifdef CONFIG_STM32F0L0_I2C4
#ifdef CONFIG_STM32F0L0G0_I2C4
static const struct stm32_i2c_config_s stm32_i2c4_config =
{
.base = STM32_I2C4_BASE,
@ -733,7 +733,7 @@ static inline void stm32_i2c_sem_wait(FAR struct i2c_master_s *dev)
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO
#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
{
size_t bytecount = 0;
@ -750,7 +750,7 @@ static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
* factor.
*/
return (useconds_t)(CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE * bytecount);
return (useconds_t)(CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE * bytecount);
}
#endif
@ -809,13 +809,13 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
/* Calculate a time in the future */
#if CONFIG_STM32F0L0_I2CTIMEOSEC > 0
abstime.tv_sec += CONFIG_STM32F0L0_I2CTIMEOSEC;
#if CONFIG_STM32F0L0G0_I2CTIMEOSEC > 0
abstime.tv_sec += CONFIG_STM32F0L0G0_I2CTIMEOSEC;
#endif
/* Add a value proportional to the number of bytes in the transfer */
#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO
#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
abstime.tv_nsec += 1000 * stm32_i2c_tousecs(priv->msgc, priv->msgv);
if (abstime.tv_nsec >= 1000 * 1000 * 1000)
{
@ -823,8 +823,8 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
abstime.tv_nsec -= 1000 * 1000 * 1000;
}
#elif CONFIG_STM32F0L0_I2CTIMEOMS > 0
abstime.tv_nsec += CONFIG_STM32F0L0_I2CTIMEOMS * 1000 * 1000;
#elif CONFIG_STM32F0L0G0_I2CTIMEOMS > 0
abstime.tv_nsec += CONFIG_STM32F0L0G0_I2CTIMEOMS * 1000 * 1000;
if (abstime.tv_nsec >= 1000 * 1000 * 1000)
{
abstime.tv_sec++;
@ -870,10 +870,10 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
/* Get the timeout value */
#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO
#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
timeout = USEC2TICK(stm32_i2c_tousecs(priv->msgc, priv->msgv));
#else
timeout = CONFIG_STM32F0L0_I2CTIMEOTICKS;
timeout = CONFIG_STM32F0L0G0_I2CTIMEOTICKS;
#endif
/* Signal the interrupt handler that we are waiting. NOTE: Interrupts
@ -1012,10 +1012,10 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
/* Select a timeout */
#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO
timeout = USEC2TICK(CONFIG_STM32F0L0_I2C_DYNTIMEO_STARTSTOP);
#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
timeout = USEC2TICK(CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP);
#else
timeout = CONFIG_STM32F0L0_I2CTIMEOTICKS;
timeout = CONFIG_STM32F0L0G0_I2CTIMEOTICKS;
#endif
/* Wait as stop might still be in progress */
@ -2751,22 +2751,22 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
switch (port)
{
#ifdef CONFIG_STM32F0L0_I2C1
#ifdef CONFIG_STM32F0L0G0_I2C1
case 1:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv;
break;
#endif
#ifdef CONFIG_STM32F0L0_I2C2
#ifdef CONFIG_STM32F0L0G0_I2C2
case 2:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv;
break;
#endif
#ifdef CONFIG_STM32F0L0_I2C3
#ifdef CONFIG_STM32F0L0G0_I2C3
case 3:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv;
break;
#endif
#ifdef CONFIG_STM32F0L0_I2C4
#ifdef CONFIG_STM32F0L0G0_I2C4
case 4:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv;
break;
@ -2861,5 +2861,5 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
return OK;
}
#endif /* CONFIG_STM32F0L0_I2C1 || CONFIG_STM32F0L0_I2C2 || \
CONFIG_STM32F0L0_I2C3 || CONFIG_STM32F0L0_I2C4 */
#endif /* CONFIG_STM32F0L0G0_I2C1 || CONFIG_STM32F0L0G0_I2C2 || \
CONFIG_STM32F0L0G0_I2C3 || CONFIG_STM32F0L0G0_I2C4 */

16
arch/arm/src/stm32f0l0/stm32_i2c.h → arch/arm/src/stm32f0l0g0/stm32_i2c.h
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_i2c.h
* arch/arm/src/stm32f0l0g0/stm32_i2c.h
*
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H
/****************************************************************************
* Included Files
@ -54,10 +54,10 @@
* seconds per byte value must be provided as well.
*/
#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO
# if CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32F0L0_I2C_DYNTIMEO because of CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32F0L0_I2C_DYNTIMEO
#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
# if CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32F0L0G0_I2C_DYNTIMEO because of CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
# endif
#endif
@ -101,4 +101,4 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port);
int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H */

4
arch/arm/src/stm32f0l0/stm32_idle.c → arch/arm/src/stm32f0l0g0/stm32_idle.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_idle.c
* arch/arm/src/stm32f0l0g0/stm32_idle.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -97,7 +97,7 @@ void up_idle(void)
* disabled in order to save power."
*/
#ifdef CONFIG_STM32F0L0_GPDMA
#ifdef CONFIG_STM32F0L0G0_GPDMA
if (g_dma_inprogress == 0)
#endif
{

4
arch/arm/src/stm32f0l0/stm32_irq.c → arch/arm/src/stm32f0l0g0/stm32_irq.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_irq.c
* arch/arm/src/stm32f0l0g0/stm32_irq.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -245,7 +245,7 @@ void up_irqinitialize(void)
* configured pin interrupts.
*/
#ifdef CONFIG_STM32F0L0_GPIOIRQ
#ifdef CONFIG_STM32F0L0G0_GPIOIRQ
stm32_gpioirqinitialize();
#endif

6
arch/arm/src/stm32f0l0/stm32_lowputc.c → arch/arm/src/stm32f0l0g0/stm32_lowputc.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_lowputc.c
* arch/arm/src/stm32f0l0g0/stm32_lowputc.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -44,9 +44,9 @@
* Public Functions
****************************************************************************/
#if defined(CONFIG_STM32F0L0_HAVE_IP_USART_V1)
#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1)
# include "stm32_lowputc_v1.c"
#elif defined(CONFIG_STM32F0L0_HAVE_IP_USART_V2)
#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2)
# include "stm32_lowputc_v2.c"
#else
# error "Unsupported STM32 M0 serial"

8
arch/arm/src/stm32f0l0/stm32_lowputc.h → arch/arm/src/stm32f0l0g0/stm32_lowputc.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/stm32_lowputc.h
* arch/arm/src/stm32f0l0g0/stm32_lowputc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H
/************************************************************************************
* Included Files
@ -77,4 +77,4 @@ void stm32_lowsetup(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H */

12
arch/arm/src/stm32f0l0/stm32_lowputc_v1.c → arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_lowputc_v1.c
* arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c
*
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -280,7 +280,7 @@ void stm32_lowsetup(void)
/* Setup clocking and GPIO pins for all configured USARTs */
#ifdef CONFIG_STM32F0L0_USART1
#ifdef CONFIG_STM32F0L0G0_USART1
/* Enable USART APB2 clock */
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN);
@ -296,7 +296,7 @@ void stm32_lowsetup(void)
#endif
#endif
#ifdef CONFIG_STM32F0L0_USART2
#ifdef CONFIG_STM32F0L0G0_USART2
/* Enable USART APB1 clock */
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN);
@ -312,7 +312,7 @@ void stm32_lowsetup(void)
#endif
#endif
#ifdef CONFIG_STM32F0L0_USART3
#ifdef CONFIG_STM32F0L0G0_USART3
/* Enable USART APB1 clock */
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN);
@ -328,7 +328,7 @@ void stm32_lowsetup(void)
#endif
#endif
#ifdef CONFIG_STM32F0L0_USART4
#ifdef CONFIG_STM32F0L0G0_USART4
/* Enable USART APB1 clock */
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN);
@ -344,7 +344,7 @@ void stm32_lowsetup(void)
#endif
#endif
#ifdef CONFIG_STM32F0L0_USART5
#ifdef CONFIG_STM32F0L0G0_USART5
/* Enable USART APB1 clock */
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN);

2
arch/arm/src/stm32f0l0/stm32_lowputc_v2.c → arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_lowputc_v2.c
* arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>

0
arch/arm/src/stm32f0l0/stm32_lse.c → arch/arm/src/stm32f0l0g0/stm32_lse.c
View File

8
arch/arm/src/stm32f0l0/stm32_pwr.c → arch/arm/src/stm32f0l0g0/stm32_pwr.c
View File

@ -49,7 +49,7 @@
#include "up_arch.h"
#include "stm32_pwr.h"
#if defined(CONFIG_STM32F0L0_PWR)
#if defined(CONFIG_STM32F0L0G0_PWR)
/************************************************************************************
* Private Data
@ -310,7 +310,7 @@ bool stm32_pwr_getwuf(void)
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_ENERGYLITE
#ifdef CONFIG_STM32F0L0G0_ENERGYLITE
void stm32_pwr_setvos(uint16_t vos)
{
uint16_t regval;
@ -401,6 +401,6 @@ void stm32_pwr_disablepvd(void)
stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, PWR_CR_PVDE, 0);
}
#endif /* CONFIG_STM32F0L0_ENERGYLITE */
#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */
#endif /* CONFIG_STM32F0L0_PWR */
#endif /* CONFIG_STM32F0L0G0_PWR */

12
arch/arm/src/stm32f0l0/stm32_pwr.h → arch/arm/src/stm32f0l0g0/stm32_pwr.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/stm32_pwr.h
* arch/arm/src/stm32f0l0g0/stm32_pwr.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_PWR_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_PWR_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H
/************************************************************************************
* Included Files
@ -181,7 +181,7 @@ bool stm32_pwr_getwuf(void);
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_ENERGYLITE
#ifdef CONFIG_STM32F0L0G0_ENERGYLITE
void stm32_pwr_setvos(uint16_t vos);
/************************************************************************************
@ -223,7 +223,7 @@ void stm32_pwr_enablepvd(void);
void stm32_pwr_disablepvd(void);
#endif /* CONFIG_STM32F0L0_ENERGYLITE */
#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */
#undef EXTERN
#if defined(__cplusplus)
@ -231,4 +231,4 @@ void stm32_pwr_disablepvd(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_PWR_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H */

10
arch/arm/src/stm32f0l0/stm32_rcc.c → arch/arm/src/stm32f0l0g0/stm32_rcc.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_rcc.c
* arch/arm/src/stm32f0l0g0/stm32_rcc.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
@ -58,12 +58,12 @@
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_STM32F0L0_RNG
#ifdef CONFIG_STM32F0L0G0_RNG
# ifndef STM32_USE_CLK48
# error RNG requires CLK48 enabled
# endif
#endif
#ifdef CONFIG_STM32F0L0_USB
#ifdef CONFIG_STM32F0L0G0_USB
# ifndef STM32_USE_CLK48
# error USB requires CLK48 enabled
# endif
@ -113,7 +113,7 @@
*
****************************************************************************/
#if defined(CONFIG_STM32F0L0_RTC) && defined(CONFIG_STM32F0L0_PWR)
#if defined(CONFIG_STM32F0L0G0_RTC) && defined(CONFIG_STM32F0L0G0_PWR)
static inline void rcc_resetbkp(void)
{
uint32_t regval;
@ -188,7 +188,7 @@ void stm32_clockconfig(void)
#endif
#ifdef CONFIG_STM32F0L0_SYSCFG_IOCOMPENSATION
#ifdef CONFIG_STM32F0L0G0_SYSCFG_IOCOMPENSATION
/* Enable I/O Compensation */
stm32_iocompensation();

8
arch/arm/src/stm32f0l0/stm32_rcc.h → arch/arm/src/stm32f0l0g0/stm32_rcc.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/stm32_rcc.h
* arch/arm/src/stm32f0l0g0/stm32_rcc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.orgr>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H
/************************************************************************************
* Included Files
@ -80,4 +80,4 @@ void stm32_clockconfig(void);
void stm32_rcc_enablelse(void);
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H */

6
arch/arm/src/stm32f0l0/stm32_rng.c → arch/arm/src/stm32f0l0g0/stm32_rng.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_rng.c
* arch/arm/src/stm32f0l0g0/stm32_rng.c
*
* Copyright (C) 2012 Max Holtzberg. All rights reserved.
* Author: Max Holtzberg <mh@uvc.de>
@ -54,7 +54,7 @@
#include "hardware/stm32_rng.h"
#include "up_internal.h"
#if defined(CONFIG_STM32F0L0_RNG)
#if defined(CONFIG_STM32F0L0G0_RNG)
#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
/****************************************************************************
@ -332,4 +332,4 @@ void devurandom_register(void)
#endif
#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */
#endif /* CONFIG_STM32F0L0_RNG */
#endif /* CONFIG_STM32F0L0G0_RNG */

6
arch/arm/src/stm32f0l0/stm32_serial.c → arch/arm/src/stm32f0l0g0/stm32_serial.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_serial.c
* arch/arm/src/stm32f0l0g0/stm32_serial.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -51,9 +51,9 @@
* - STM32 UART IP version 2 - G0
*/
#if defined(CONFIG_STM32F0L0_HAVE_IP_USART_V1)
#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1)
# include "stm32_serial_v1.c"
#elif defined(CONFIG_STM32F0L0_HAVE_IP_USART_V2)
#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2)
# include "stm32_serial_v2.c"
#else
# error "Unsupported STM32 M0 serial"

8
arch/arm/src/stm32f0l0/stm32_serial.h → arch/arm/src/stm32f0l0g0/stm32_serial.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/stm32_serial.h
* arch/arm/src/stm32f0l0g0/stm32_serial.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H
/************************************************************************************
* Included Files
@ -47,4 +47,4 @@
* Pre-processor Definitions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H */

78
arch/arm/src/stm32f0l0/stm32_serial_v1.c → arch/arm/src/stm32f0l0g0/stm32_serial_v1.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_serial_v1.c
* arch/arm/src/stm32f0l0g0/stm32_serial_v1.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -97,14 +97,14 @@
*/
# if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA)
# ifndef CONFIG_STM32F0L0_DMA1
# error STM32F0 USART2/3 receive DMA requires CONFIG_STM32F0L0_DMA1
# ifndef CONFIG_STM32F0L0G0_DMA1
# error STM32F0 USART2/3 receive DMA requires CONFIG_STM32F0L0G0_DMA1
# endif
# endif
# if defined(CONFIG_USART4_RXDMA) || defined(CONFIG_USART5_RXDMA)
# ifndef CONFIG_STM32F0L0_DMA2
# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32F0L0_DMA2
# ifndef CONFIG_STM32F0L0G0_DMA2
# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32F0L0G0_DMA2
# endif
# endif
@ -173,8 +173,8 @@
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY 10
#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY 10
#endif
#if defined(CONFIG_PM)
# define PM_IDLE_DOMAIN 0 /* Revisit */
@ -191,7 +191,7 @@
* See stm32serial_restoreusartint where the masking is done.
*/
#ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
#endif
@ -363,7 +363,7 @@ static const struct uart_ops_s g_uart_dma_ops =
/* I/O buffers */
#ifdef CONFIG_STM32F0L0_USART1
#ifdef CONFIG_STM32F0L0G0_USART1
static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
# ifdef CONFIG_USART1_RXDMA
@ -371,7 +371,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32F0L0_USART2
#ifdef CONFIG_STM32F0L0G0_USART2
static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
# ifdef CONFIG_USART2_RXDMA
@ -379,7 +379,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32F0L0_USART3
#ifdef CONFIG_STM32F0L0G0_USART3
static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE];
static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE];
# ifdef CONFIG_USART3_RXDMA
@ -387,7 +387,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32F0L0_USART4
#ifdef CONFIG_STM32F0L0G0_USART4
static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE];
static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE];
# ifdef CONFIG_USART4_RXDMA
@ -395,7 +395,7 @@ static char g_usart4rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32F0L0_USART5
#ifdef CONFIG_STM32F0L0G0_USART5
static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE];
static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE];
# ifdef CONFIG_USART5_RXDMA
@ -405,7 +405,7 @@ static char g_usart5rxfifo[RXDMA_BUFFER_SIZE];
/* This describes the state of the STM32 USART1 ports. */
#ifdef CONFIG_STM32F0L0_USART1
#ifdef CONFIG_STM32F0L0G0_USART1
static struct stm32_serial_s g_usart1priv =
{
.dev =
@ -466,7 +466,7 @@ static struct stm32_serial_s g_usart1priv =
/* This describes the state of the STM32 USART2 port. */
#ifdef CONFIG_STM32F0L0_USART2
#ifdef CONFIG_STM32F0L0G0_USART2
static struct stm32_serial_s g_usart2priv =
{
.dev =
@ -527,7 +527,7 @@ static struct stm32_serial_s g_usart2priv =
/* This describes the state of the STM32 USART3 port. */
#ifdef CONFIG_STM32F0L0_USART3
#ifdef CONFIG_STM32F0L0G0_USART3
static struct stm32_serial_s g_usart3priv =
{
.dev =
@ -588,7 +588,7 @@ static struct stm32_serial_s g_usart3priv =
/* This describes the state of the STM32 USART4 port. */
#ifdef CONFIG_STM32F0L0_USART4
#ifdef CONFIG_STM32F0L0G0_USART4
static struct stm32_serial_s g_usart4priv =
{
.dev =
@ -653,7 +653,7 @@ static struct stm32_serial_s g_usart4priv =
/* This describes the state of the STM32 USART5 port. */
#ifdef CONFIG_STM32F0L0_USART5
#ifdef CONFIG_STM32F0L0G0_USART5
static struct stm32_serial_s g_usart5priv =
{
.dev =
@ -720,19 +720,19 @@ static struct stm32_serial_s g_usart5priv =
FAR static struct stm32_serial_s * const g_uart_devs[STM32_NUSART] =
{
#ifdef CONFIG_STM32F0L0_USART1
#ifdef CONFIG_STM32F0L0G0_USART1
[0] = &g_usart1priv,
#endif
#ifdef CONFIG_STM32F0L0_USART2
#ifdef CONFIG_STM32F0L0G0_USART2
[1] = &g_usart2priv,
#endif
#ifdef CONFIG_STM32F0L0_USART3
#ifdef CONFIG_STM32F0L0G0_USART3
[2] = &g_usart3priv,
#endif
#ifdef CONFIG_STM32F0L0_USART4
#ifdef CONFIG_STM32F0L0G0_USART4
[3] = &g_usart4priv,
#endif
#ifdef CONFIG_STM32F0L0_USART5
#ifdef CONFIG_STM32F0L0G0_USART5
[4] = &g_usart5priv,
#endif
};
@ -1008,7 +1008,7 @@ static void stm32serial_setformat(FAR struct uart_dev_s *dev)
regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET);
regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE);
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32F0L0_FLOWCONTROL_BROKEN)
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
regval |= USART_CR3_RTSE;
@ -1050,31 +1050,31 @@ static void stm32serial_setapbclock(FAR struct uart_dev_s *dev, bool on)
{
default:
return;
#ifdef CONFIG_STM32F0L0_USART1
#ifdef CONFIG_STM32F0L0G0_USART1
case STM32_USART1_BASE:
rcc_en = RCC_APB2ENR_USART1EN;
regaddr = STM32_RCC_APB2ENR;
break;
#endif
#ifdef CONFIG_STM32F0L0_USART2
#ifdef CONFIG_STM32F0L0G0_USART2
case STM32_USART2_BASE:
rcc_en = RCC_APB1ENR_USART2EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32F0L0_USART3
#ifdef CONFIG_STM32F0L0G0_USART3
case STM32_USART3_BASE:
rcc_en = RCC_APB1ENR_USART3EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32F0L0_USART4
#ifdef CONFIG_STM32F0L0G0_USART4
case STM32_USART4_BASE:
rcc_en = RCC_APB1ENR_USART4EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32F0L0_USART5
#ifdef CONFIG_STM32F0L0G0_USART5
case STM32_USART5_BASE:
rcc_en = RCC_APB1ENR_USART5EN;
regaddr = STM32_RCC_APB1ENR;
@ -1135,7 +1135,7 @@ static int stm32serial_setup(FAR struct uart_dev_s *dev)
{
uint32_t config = priv->rts_gpio;
#ifdef CONFIG_STM32F0L0_FLOWCONTROL_BROKEN
#ifdef CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN
/* Instead of letting hw manage this pin, we will bitbang */
config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT;
@ -1460,8 +1460,8 @@ static int up_interrupt(int irq, FAR void *context, FAR void *arg)
/* Report serial activity to the power management logic */
#if defined(CONFIG_PM) && CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY);
#if defined(CONFIG_PM) && CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY);
#endif
/* Loop until there are no characters to be transferred or,
@ -1592,7 +1592,7 @@ static int stm32serial_ioctl(FAR struct file *filep, int cmd,
break;
#endif
#ifdef CONFIG_STM32F0L0_USART_SINGLEWIRE
#ifdef CONFIG_STM32F0L0G0_USART_SINGLEWIRE
#warning please review the potential use of ALTERNATE_FUNCTION_OPENDRAIN
case TIOCSSINGLEWIRE:
{
@ -1713,8 +1713,8 @@ static int stm32serial_ioctl(FAR struct file *filep, int cmd,
break;
#endif /* CONFIG_SERIAL_TERMIOS */
#ifdef CONFIG_STM32F0L0_USART_BREAKS
# ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32F0L0G0_USART_BREAKS
# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
{
irqstate_t flags;
@ -1927,7 +1927,7 @@ static bool stm32serial_rxflowcontrol(FAR struct uart_dev_s *dev,
FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv;
#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \
defined(CONFIG_STM32F0L0_FLOWCONTROL_BROKEN)
defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
/* Assert/de-assert nRTS set it high resume/stop sending */
@ -2173,7 +2173,7 @@ static void stm32serial_txint(FAR struct uart_dev_s *dev, bool enable)
}
# endif
# ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT
# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
{
return;
@ -2426,7 +2426,7 @@ void up_serialinit(void)
#if CONSOLE_USART > 0
(void)uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev);
#ifndef CONFIG_STM32F0L0_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING
/* If not disabled, register the console USART to ttyS0 and exclude
* it from initializing it further down
*/
@ -2455,7 +2455,7 @@ void up_serialinit(void)
continue;
}
#ifndef CONFIG_STM32F0L0_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING
/* Don't create a device for the console - we did that above */
if (g_uart_devs[i]->dev.isconsole)

68
arch/arm/src/stm32f0l0/stm32_serial_v2.c → arch/arm/src/stm32f0l0g0/stm32_serial_v2.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_serial.c
* arch/arm/src/stm32f0l0g0/stm32_serial.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
@ -70,10 +70,10 @@
#include <arch/board/board.h>
#ifdef CONFIG_STM32F0L0_USART3
#ifdef CONFIG_STM32F0L0G0_USART3
# error not supported yet
#endif
#ifdef CONFIG_STM32F0L0_USART4
#ifdef CONFIG_STM32F0L0G0_USART4
# error not supported yet
#endif
@ -88,8 +88,8 @@
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY 10
#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY 10
#endif
#if defined(CONFIG_PM)
# define PM_IDLE_DOMAIN 0 /* Revisit */
@ -106,7 +106,7 @@
* See up_restoreusartint where the masking is done.
*/
#ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
#endif
@ -116,9 +116,9 @@
/* Warnings for potentially unsafe configuration combinations. */
#if defined(CONFIG_STM32F0L0_FLOWCONTROL_BROKEN) && \
#if defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) && \
!defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS)
# error "CONFIG_STM32F0L0_FLOWCONTROL_BROKEN requires \
# error "CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN requires \
CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled."
#endif
@ -237,29 +237,29 @@ static const struct uart_ops_s g_uart_ops =
/* Receive/Transmit buffers */
#ifdef CONFIG_STM32F0L0_USART1
#ifdef CONFIG_STM32F0L0G0_USART1
static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
#endif
#ifdef CONFIG_STM32F0L0_USART2
#ifdef CONFIG_STM32F0L0G0_USART2
static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
#endif
#ifdef CONFIG_STM32F0L0_USART3
#ifdef CONFIG_STM32F0L0G0_USART3
static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE];
static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE];
#endif
#ifdef CONFIG_STM32F0L0_USART4
#ifdef CONFIG_STM32F0L0G0_USART4
static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE];
static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE];
#endif
/* This describes the state of the STM32 USART1 ports. */
#ifdef CONFIG_STM32F0L0_USART1
#ifdef CONFIG_STM32F0L0G0_USART1
static struct up_dev_s g_usart1priv =
{
.dev =
@ -313,7 +313,7 @@ static struct up_dev_s g_usart1priv =
/* This describes the state of the STM32 USART2 port. */
#ifdef CONFIG_STM32F0L0_USART2
#ifdef CONFIG_STM32F0L0G0_USART2
static struct up_dev_s g_usart2priv =
{
.dev =
@ -373,16 +373,16 @@ static struct up_dev_s g_usart2priv =
static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] =
{
#ifdef CONFIG_STM32F0L0_USART1
#ifdef CONFIG_STM32F0L0G0_USART1
[0] = &g_usart1priv,
#endif
#ifdef CONFIG_STM32F0L0_USART2
#ifdef CONFIG_STM32F0L0G0_USART2
[1] = &g_usart2priv,
#endif
#ifdef CONFIG_STM32F0L0_USART3
#ifdef CONFIG_STM32F0L0G0_USART3
[2] = &g_usart3priv,
#endif
#ifdef CONFIG_STM32F0L0_USART4
#ifdef CONFIG_STM32F0L0G0_USART4
[3] = &g_usart4priv
#endif
};
@ -655,7 +655,7 @@ static void up_set_format(struct uart_dev_s *dev)
regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE);
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && \
!defined(CONFIG_STM32F0L0_FLOWCONTROL_BROKEN)
!defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
regval |= USART_CR3_RTSE;
@ -699,25 +699,25 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on)
{
default:
return;
#ifdef CONFIG_STM32F0L0_USART1
#ifdef CONFIG_STM32F0L0G0_USART1
case STM32_USART1_BASE:
rcc_en = RCC_APB2ENR_USART1EN;
regaddr = STM32_RCC_APB2ENR;
break;
#endif
#ifdef CONFIG_STM32F0L0_USART2
#ifdef CONFIG_STM32F0L0G0_USART2
case STM32_USART2_BASE:
rcc_en = RCC_APB1ENR_USART2EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32F0L0_USART3
#ifdef CONFIG_STM32F0L0G0_USART3
case STM32_USART3_BASE:
rcc_en = RCC_APB1ENR_USART3EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32F0L0_USART4
#ifdef CONFIG_STM32F0L0G0_USART4
case STM32_USART4_BASE:
rcc_en = RCC_APB1ENR_USART4EN;
regaddr = STM32_RCC_APB1ENR;
@ -782,7 +782,7 @@ static int up_setup(struct uart_dev_s *dev)
{
uint32_t config = priv->rts_gpio;
#ifdef CONFIG_STM32F0L0_FLOWCONTROL_BROKEN
#ifdef CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN
/* Instead of letting hw manage this pin, we will bitbang */
config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT;
@ -1001,8 +1001,8 @@ static int up_interrupt(int irq, void *context, FAR void *arg)
/* Report serial activity to the power management logic */
#if defined(CONFIG_PM) && CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY);
#if defined(CONFIG_PM) && CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY);
#endif
/* Loop until there are no characters to be transferred or,
@ -1106,11 +1106,11 @@ static int up_interrupt(int irq, void *context, FAR void *arg)
static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
{
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \
|| defined(CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT)
|| defined(CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT)
struct inode *inode = filep->f_inode;
struct uart_dev_s *dev = inode->i_private;
#endif
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT)
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT)
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
#endif
int ret = OK;
@ -1133,7 +1133,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
break;
#endif
#ifdef CONFIG_STM32F0L0_USART_SINGLEWIRE
#ifdef CONFIG_STM32F0L0G0_USART_SINGLEWIRE
case TIOCSSINGLEWIRE:
{
uint32_t cr1;
@ -1274,8 +1274,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
break;
#endif /* CONFIG_SERIAL_TERMIOS */
#ifdef CONFIG_STM32F0L0_USART_BREAKS
# ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32F0L0G0_USART_BREAKS
# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
{
irqstate_t flags;
@ -1481,7 +1481,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev,
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \
defined(CONFIG_STM32F0L0_FLOWCONTROL_BROKEN)
defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
/* Assert/de-assert nRTS set it high resume/stop sending */
@ -1856,7 +1856,7 @@ void up_serialinit(void)
#if CONSOLE_USART > 0
(void)uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev);
#ifndef CONFIG_STM32F0L0_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING
/* If not disabled, register the console UART to ttyS0 and exclude
* it from initializing it further down
*/
@ -1880,7 +1880,7 @@ void up_serialinit(void)
continue;
}
#ifndef CONFIG_STM32F0L0_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING
/* Don't create a device for the console - we did that above */
if (g_uart_devs[i]->dev.isconsole)

70
arch/arm/src/stm32f0l0/stm32_spi.c → arch/arm/src/stm32f0l0g0/stm32_spi.c
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/stm32_spi.c
* arch/arm/src/stm32f0l0g0/stm32_spi.c
* copied from arch/arm/src/stm32
*
* Copyright (C) 2009-2013, 2016 Gregory Nutt. All rights reserved.
@ -93,7 +93,7 @@
#include <arch/board/board.h>
#ifdef CONFIG_STM32F0L0_SPI
#ifdef CONFIG_STM32F0L0G0_SPI
/************************************************************************************
* Pre-processor Definitions
@ -102,19 +102,19 @@
/* Configuration ********************************************************************/
/* SPI interrupts */
#ifdef CONFIG_STM32F0L0_SPI_INTERRUPTS
#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
# error "Interrupt driven SPI not yet supported"
#endif
/* Can't have both interrupt driven SPI and SPI DMA */
#if defined(CONFIG_STM32F0L0_SPI_INTERRUPTS) && defined(CONFIG_STM32F0L0_SPI_DMA)
#if defined(CONFIG_STM32F0L0G0_SPI_INTERRUPTS) && defined(CONFIG_STM32F0L0G0_SPI_DMA)
# error "Cannot enable both interrupt mode and DMA mode for SPI"
#endif
/* SPI DMA priority */
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
# if defined(CONFIG_SPI_DMAPRIO)
# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
@ -148,10 +148,10 @@ struct stm32_spidev_s
struct spi_dev_s spidev; /* Externally visible part of the SPI interface */
uint32_t spibase; /* SPIn base address */
uint32_t spiclock; /* Clocking for the SPI module */
#ifdef CONFIG_STM32F0L0_SPI_INTERRUPTS
#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
uint8_t spiirq; /* SPI IRQ number */
#endif
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
volatile uint8_t rxresult; /* Result of the RX DMA */
volatile uint8_t txresult; /* Result of the RX DMA */
#ifdef CONFIG_SPI_TRIGGER
@ -193,7 +193,7 @@ static inline bool spi_16bitmode(FAR struct stm32_spidev_s *priv);
/* DMA support */
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
static void spi_dmarxwait(FAR struct stm32_spidev_s *priv);
static void spi_dmatxwait(FAR struct stm32_spidev_s *priv);
static inline void spi_dmarxwakeup(FAR struct stm32_spidev_s *priv);
@ -246,7 +246,7 @@ static int spi_pm_prepare(FAR struct pm_callback_s *cb, int domain,
* Private Data
************************************************************************************/
#ifdef CONFIG_STM32F0L0_SPI1
#ifdef CONFIG_STM32F0L0G0_SPI1
static const struct spi_ops_s g_spi1ops =
{
.lock = spi_lock,
@ -283,10 +283,10 @@ static struct stm32_spidev_s g_spi1dev =
.spidev = { &g_spi1ops },
.spibase = STM32_SPI1_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
#ifdef CONFIG_STM32F0L0_SPI_INTERRUPTS
#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
.spiirq = STM32_IRQ_SPI1,
#endif
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
/* lines must be configured in board.h */
.rxch = DMACHAN_SPI1_RX,
.txch = DMACHAN_SPI1_TX,
@ -297,7 +297,7 @@ static struct stm32_spidev_s g_spi1dev =
};
#endif
#ifdef CONFIG_STM32F0L0_SPI2
#ifdef CONFIG_STM32F0L0G0_SPI2
static const struct spi_ops_s g_spi2ops =
{
.lock = spi_lock,
@ -334,10 +334,10 @@ static struct stm32_spidev_s g_spi2dev =
.spidev = { &g_spi2ops },
.spibase = STM32_SPI2_BASE,
.spiclock = STM32_PCLK1_FREQUENCY,
#ifdef CONFIG_STM32F0L0_SPI_INTERRUPTS
#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
.spiirq = STM32_IRQ_SPI2,
#endif
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
.rxch = DMACHAN_SPI2_RX,
.txch = DMACHAN_SPI2_TX,
#endif
@ -567,7 +567,7 @@ static inline bool spi_16bitmode(FAR struct stm32_spidev_s *priv)
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
static void spi_dmarxwait(FAR struct stm32_spidev_s *priv)
{
int ret;
@ -598,7 +598,7 @@ static void spi_dmarxwait(FAR struct stm32_spidev_s *priv)
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
static void spi_dmatxwait(FAR struct stm32_spidev_s *priv)
{
int ret;
@ -629,7 +629,7 @@ static void spi_dmatxwait(FAR struct stm32_spidev_s *priv)
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
static inline void spi_dmarxwakeup(FAR struct stm32_spidev_s *priv)
{
(void)nxsem_post(&priv->rxsem);
@ -644,7 +644,7 @@ static inline void spi_dmarxwakeup(FAR struct stm32_spidev_s *priv)
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
static inline void spi_dmatxwakeup(FAR struct stm32_spidev_s *priv)
{
(void)nxsem_post(&priv->txsem);
@ -659,7 +659,7 @@ static inline void spi_dmatxwakeup(FAR struct stm32_spidev_s *priv)
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
{
FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)arg;
@ -679,7 +679,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
{
FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)arg;
@ -699,7 +699,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
static void spi_dmarxsetup(FAR struct stm32_spidev_s *priv, FAR void *rxbuffer,
FAR void *rxdummy, size_t nwords)
{
@ -749,7 +749,7 @@ static void spi_dmarxsetup(FAR struct stm32_spidev_s *priv, FAR void *rxbuffer,
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
static void spi_dmatxsetup(FAR struct stm32_spidev_s *priv, FAR const void *txbuffer,
FAR const void *txdummy, size_t nwords)
{
@ -799,7 +799,7 @@ static void spi_dmatxsetup(FAR struct stm32_spidev_s *priv, FAR const void *txbu
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
static inline void spi_dmarxstart(FAR struct stm32_spidev_s *priv)
{
priv->rxresult = 0;
@ -815,7 +815,7 @@ static inline void spi_dmarxstart(FAR struct stm32_spidev_s *priv)
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
static inline void spi_dmatxstart(FAR struct stm32_spidev_s *priv)
{
priv->txresult = 0;
@ -1285,8 +1285,8 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
*
************************************************************************************/
#if !defined(CONFIG_STM32F0L0_SPI_DMA) || defined(CONFIG_STM32F0L0_DMACAPABLE)
#if !defined(CONFIG_STM32F0L0_SPI_DMA)
#if !defined(CONFIG_STM32F0L0G0_SPI_DMA) || defined(CONFIG_STM32F0L0G0_DMACAPABLE)
#if !defined(CONFIG_STM32F0L0G0_SPI_DMA)
static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
FAR void *rxbuffer, size_t nwords)
#else
@ -1368,7 +1368,7 @@ static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuff
}
}
}
#endif /* !CONFIG_STM32F0L0_SPI_DMA || CONFIG_STM32F0L0_DMACAPABLE */
#endif /* !CONFIG_STM32F0L0G0_SPI_DMA || CONFIG_STM32F0L0G0_DMACAPABLE */
/****************************************************************************
* Name: spi_exchange (with DMA capability)
@ -1390,13 +1390,13 @@ static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuff
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
FAR void *rxbuffer, size_t nwords)
{
FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev;
#ifdef CONFIG_STM32F0L0_DMACAPABLE
#ifdef CONFIG_STM32F0L0G0_DMACAPABLE
if ((txbuffer && !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) ||
(rxbuffer && !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr)))
{
@ -1451,7 +1451,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
#endif
}
}
#endif /* CONFIG_STM32F0L0_SPI_DMA */
#endif /* CONFIG_STM32F0L0G0_SPI_DMA */
/****************************************************************************
* Name: spi_trigger
@ -1472,7 +1472,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
#ifdef CONFIG_SPI_TRIGGER
static int spi_trigger(FAR struct spi_dev_s *dev)
{
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev;
if (!priv->trigarmed)
@ -1691,7 +1691,7 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
nxsem_init(&priv->exclsem, 0, 1);
#ifdef CONFIG_STM32F0L0_SPI_DMA
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
/* Initialize the SPI semaphores that is used to wait for DMA completion */
nxsem_init(&priv->rxsem, 0, 0);
@ -1756,7 +1756,7 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus)
irqstate_t flags = enter_critical_section();
#ifdef CONFIG_STM32F0L0_SPI1
#ifdef CONFIG_STM32F0L0G0_SPI1
if (bus == 1)
{
/* Select SPI1 */
@ -1781,7 +1781,7 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus)
}
else
#endif
#ifdef CONFIG_STM32F0L0_SPI2
#ifdef CONFIG_STM32F0L0G0_SPI2
if (bus == 2)
{
/* Select SPI2 */
@ -1815,4 +1815,4 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus)
return (FAR struct spi_dev_s *)priv;
}
#endif /* CONFIG_STM32F0L0_SPI */
#endif /* CONFIG_STM32F0L0G0_SPI */

10
arch/arm/src/stm32f0l0/stm32_spi.h → arch/arm/src/stm32f0l0g0/stm32_spi.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/stm32_spi.h
* arch/arm/src/stm32f0l0g0/stm32_spi.h
*
* Copyright (C) 2009, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -115,13 +115,13 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus);
*
************************************************************************************/
#ifdef CONFIG_STM32F0L0_SPI1
#ifdef CONFIG_STM32F0L0G0_SPI1
void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid);
int stm32_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32F0L0_SPI2
#ifdef CONFIG_STM32F0L0G0_SPI2
void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid);
int stm32_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
@ -148,12 +148,12 @@ int stm32_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_STM32F0L0_SPI1
#ifdef CONFIG_STM32F0L0G0_SPI1
int stm32_spi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_STM32F0L0_SPI2
#ifdef CONFIG_STM32F0L0G0_SPI2
int stm32_spi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif

2
arch/arm/src/stm32f0l0/stm32_start.c → arch/arm/src/stm32f0l0g0/stm32_start.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_start.c
* arch/arm/src/stm32f0l0g0/stm32_start.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>

8
arch/arm/src/stm32f0l0/stm32_start.h → arch/arm/src/stm32f0l0g0/stm32_start.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/stm32_start.h
* arch/arm/src/stm32f0l0g0/stm32_start.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_START_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_START_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H
/************************************************************************************
* Included Files
@ -73,4 +73,4 @@ void stm32_boardinitialize(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_START_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H */

8
arch/arm/src/stm32f0l0/stm32_timerisr.c → arch/arm/src/stm32f0l0g0/stm32_timerisr.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_timerisr.c
* arch/arm/src/stm32f0l0g0/stm32_timerisr.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -62,9 +62,9 @@
* (when CLKSOURCE = 0). ..."
*/
#if defined(CONFIG_STM32F0L0_SYSTICK_CORECLK)
#if defined(CONFIG_STM32F0L0G0_SYSTICK_CORECLK)
# define SYSTICK_CLOCK STM32_SYSCLK_FREQUENCY /* Core clock */
#elif defined(CONFIG_STM32F0L0_SYSTICK_CORECLK_DIV16)
#elif defined(CONFIG_STM32F0L0G0_SYSTICK_CORECLK_DIV16)
# define SYSTICK_CLOCK (STM32_SYSCLK_FREQUENCY / 16) /* Core clock divided by 16 */
#endif
@ -152,7 +152,7 @@ void arm_timer_initialize(void)
* a divide-by-16 of the core clock (when CLKSOURCE = 0). ..."
*/
#ifdef CONFIG_STM32F0L0_SYSTICK_CORECLK
#ifdef CONFIG_STM32F0L0G0_SYSTICK_CORECLK
putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE),
ARMV6M_SYSTICK_CSR);
#else

244
arch/arm/src/stm32f0l0/stm32_uart.h → arch/arm/src/stm32f0l0g0/stm32_uart.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/stm32_uart.h
* arch/arm/src/stm32f0l0g0/stm32_uart.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H
/************************************************************************************
* Included Files
@ -54,29 +54,29 @@
* device.
*/
#if STM32_NUSART < 8 || !defined(CONFIG_STM32F0L0_HAVE_USART8)
# undef CONFIG_STM32F0L0_USART8
#if STM32_NUSART < 8 || !defined(CONFIG_STM32F0L0G0_HAVE_USART8)
# undef CONFIG_STM32F0L0G0_USART8
#endif
#if STM32_NUSART < 7 || !defined(CONFIG_STM32F0L0_HAVE_USART7)
# undef CONFIG_STM32F0L0_USART7
#if STM32_NUSART < 7 || !defined(CONFIG_STM32F0L0G0_HAVE_USART7)
# undef CONFIG_STM32F0L0G0_USART7
#endif
#if STM32_NUSART < 6 || !defined(CONFIG_STM32F0L0_HAVE_USART6)
# undef CONFIG_STM32F0L0_USART6
#if STM32_NUSART < 6 || !defined(CONFIG_STM32F0L0G0_HAVE_USART6)
# undef CONFIG_STM32F0L0G0_USART6
#endif
#if STM32_NUSART < 5 || !defined(CONFIG_STM32F0L0_HAVE_USART5)
# undef CONFIG_STM32F0L0_USART5
#if STM32_NUSART < 5 || !defined(CONFIG_STM32F0L0G0_HAVE_USART5)
# undef CONFIG_STM32F0L0G0_USART5
#endif
#if STM32_NUSART < 4 || !defined(CONFIG_STM32F0L0_HAVE_USART4)
# undef CONFIG_STM32F0L0_USART4
#if STM32_NUSART < 4 || !defined(CONFIG_STM32F0L0G0_HAVE_USART4)
# undef CONFIG_STM32F0L0G0_USART4
#endif
#if STM32_NUSART < 3 || !defined(CONFIG_STM32F0L0_HAVE_USART3)
# undef CONFIG_STM32F0L0_USART3
#if STM32_NUSART < 3 || !defined(CONFIG_STM32F0L0G0_HAVE_USART3)
# undef CONFIG_STM32F0L0G0_USART3
#endif
#if STM32_NUSART < 2
# undef CONFIG_STM32F0L0_USART2
# undef CONFIG_STM32F0L0G0_USART2
#endif
#if STM32_NUSART < 1
# undef CONFIG_STM32F0L0_USART1
# undef CONFIG_STM32F0L0G0_USART1
#endif
/* USART 3-8 are multiplexed to the same interrupt. Current interrupt
@ -85,128 +85,128 @@
* issue in the future.
*/
#if defined(CONFIG_STM32F0L0_USART3)
# undef CONFIG_STM32F0L0_USART4
# undef CONFIG_STM32F0L0_USART5
# undef CONFIG_STM32F0L0_USART6
# undef CONFIG_STM32F0L0_USART7
# undef CONFIG_STM32F0L0_USART8
#elif defined(CONFIG_STM32F0L0_USART4)
# undef CONFIG_STM32F0L0_USART5
# undef CONFIG_STM32F0L0_USART6
# undef CONFIG_STM32F0L0_USART7
# undef CONFIG_STM32F0L0_USART8
#elif defined(CONFIG_STM32F0L0_USART5)
# undef CONFIG_STM32F0L0_USART6
# undef CONFIG_STM32F0L0_USART7
# undef CONFIG_STM32F0L0_USART8
#elif defined(CONFIG_STM32F0L0_USART6)
# undef CONFIG_STM32F0L0_USART7
# undef CONFIG_STM32F0L0_USART8
#elif defined(CONFIG_STM32F0L0_USART7)
# undef CONFIG_STM32F0L0_USART8
#if defined(CONFIG_STM32F0L0G0_USART3)
# undef CONFIG_STM32F0L0G0_USART4
# undef CONFIG_STM32F0L0G0_USART5
# undef CONFIG_STM32F0L0G0_USART6
# undef CONFIG_STM32F0L0G0_USART7
# undef CONFIG_STM32F0L0G0_USART8
#elif defined(CONFIG_STM32F0L0G0_USART4)
# undef CONFIG_STM32F0L0G0_USART5
# undef CONFIG_STM32F0L0G0_USART6
# undef CONFIG_STM32F0L0G0_USART7
# undef CONFIG_STM32F0L0G0_USART8
#elif defined(CONFIG_STM32F0L0G0_USART5)
# undef CONFIG_STM32F0L0G0_USART6
# undef CONFIG_STM32F0L0G0_USART7
# undef CONFIG_STM32F0L0G0_USART8
#elif defined(CONFIG_STM32F0L0G0_USART6)
# undef CONFIG_STM32F0L0G0_USART7
# undef CONFIG_STM32F0L0G0_USART8
#elif defined(CONFIG_STM32F0L0G0_USART7)
# undef CONFIG_STM32F0L0G0_USART8
#endif
/* Is there a USART enabled? */
#if defined(CONFIG_STM32F0L0_USART1) || defined(CONFIG_STM32F0L0_USART2) || \
defined(CONFIG_STM32F0L0_USART3) || defined(CONFIG_STM32F0L0_USART4) || \
defined(CONFIG_STM32F0L0_USART5) || defined(CONFIG_STM32F0L0_USART6) || \
defined(CONFIG_STM32F0L0_USART7) || defined(CONFIG_STM32F0L0_USART8)
#if defined(CONFIG_STM32F0L0G0_USART1) || defined(CONFIG_STM32F0L0G0_USART2) || \
defined(CONFIG_STM32F0L0G0_USART3) || defined(CONFIG_STM32F0L0G0_USART4) || \
defined(CONFIG_STM32F0L0G0_USART5) || defined(CONFIG_STM32F0L0G0_USART6) || \
defined(CONFIG_STM32F0L0G0_USART7) || defined(CONFIG_STM32F0L0G0_USART8)
# define HAVE_USART 1
#endif
/* Sanity checks */
#if !defined(CONFIG_STM32F0L0_USART1)
# undef CONFIG_STM32F0L0_USART1_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART1_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0G0_USART1)
# undef CONFIG_STM32F0L0G0_USART1_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0L0_USART2)
# undef CONFIG_STM32F0L0_USART2_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART2_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0G0_USART2)
# undef CONFIG_STM32F0L0G0_USART2_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART2_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0L0_USART3)
# undef CONFIG_STM32F0L0_USART3_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART3_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0G0_USART3)
# undef CONFIG_STM32F0L0G0_USART3_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART3_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0L0_USART4)
# undef CONFIG_STM32F0L0_USART4_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART4_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0G0_USART4)
# undef CONFIG_STM32F0L0G0_USART4_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART4_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0L0_USART5)
# undef CONFIG_STM32F0L0_USART5_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART5_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0G0_USART5)
# undef CONFIG_STM32F0L0G0_USART5_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART5_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0L0_USART6)
# undef CONFIG_STM32F0L0_USART6_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART6_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0G0_USART6)
# undef CONFIG_STM32F0L0G0_USART6_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART6_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0L0_USART7)
# undef CONFIG_STM32F0L0_USART7_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART7_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0G0_USART7)
# undef CONFIG_STM32F0L0G0_USART7_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART7_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0L0_USART8)
# undef CONFIG_STM32F0L0_USART8_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART8_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0G0_USART8)
# undef CONFIG_STM32F0L0G0_USART8_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART8_1WIREDRIVER
#endif
/* Check 1-Wire and U(S)ART conflicts */
#if defined(CONFIG_STM32F0L0_USART1_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART1_1WIREDRIVER and CONFIG_STM32F0L0_USART1_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART1_1WIREDRIVER
#if defined(CONFIG_STM32F0L0G0_USART1_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART1_1WIREDRIVER and CONFIG_STM32F0L0G0_USART1_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART1_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0L0_USART2_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART2_1WIREDRIVER and CONFIG_STM32F0L0_USART2_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART2_1WIREDRIVER
#if defined(CONFIG_STM32F0L0G0_USART2_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART2_1WIREDRIVER and CONFIG_STM32F0L0G0_USART2_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART2_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0L0_USART3_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART3_1WIREDRIVER and CONFIG_STM32F0L0_USART3_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART3_1WIREDRIVER
#if defined(CONFIG_STM32F0L0G0_USART3_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART3_1WIREDRIVER and CONFIG_STM32F0L0G0_USART3_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART3_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0L0_USART4_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART4_1WIREDRIVER and CONFIG_STM32F0L0_USART4_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART4_1WIREDRIVER
#if defined(CONFIG_STM32F0L0G0_USART4_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART4_1WIREDRIVER and CONFIG_STM32F0L0G0_USART4_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART4_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0L0_USART5_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART5_1WIREDRIVER and CONFIG_STM32F0L0_USART5_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART5_1WIREDRIVER
#if defined(CONFIG_STM32F0L0G0_USART5_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART5_1WIREDRIVER and CONFIG_STM32F0L0G0_USART5_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART5_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0L0_USART6_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART6_1WIREDRIVER and CONFIG_STM32F0L0_USART6_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART6_1WIREDRIVER
#if defined(CONFIG_STM32F0L0G0_USART6_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART6_1WIREDRIVER and CONFIG_STM32F0L0G0_USART6_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART6_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0L0_USART7_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART7_1WIREDRIVER and CONFIG_STM32F0L0_USART7_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART7_1WIREDRIVER
#if defined(CONFIG_STM32F0L0G0_USART7_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART7_1WIREDRIVER and CONFIG_STM32F0L0G0_USART7_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART7_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0L0_USART8_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART8_1WIREDRIVER and CONFIG_STM32F0L0_USART8_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART8_1WIREDRIVER
#if defined(CONFIG_STM32F0L0G0_USART8_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART8_1WIREDRIVER and CONFIG_STM32F0L0G0_USART8_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART8_1WIREDRIVER
#endif
/* Is the serial driver enabled? */
#if defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER) || \
defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER) || \
defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER) || \
defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER)
#if defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) || \
defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) || \
defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) || \
defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER)
# define HAVE_SERIALDRIVER 1
#endif
/* Is the 1-Wire driver? */
#if defined(CONFIG_STM32F0L0_USART1_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART2_1WIREDRIVER) || \
defined(CONFIG_STM32F0L0_USART3_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART4_1WIREDRIVER) || \
defined(CONFIG_STM32F0L0_USART5_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART6_1WIREDRIVER) || \
defined(CONFIG_STM32F0L0_USART7_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART8_1WIREDRIVER)
#if defined(CONFIG_STM32F0L0G0_USART1_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART2_1WIREDRIVER) || \
defined(CONFIG_STM32F0L0G0_USART3_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART4_1WIREDRIVER) || \
defined(CONFIG_STM32F0L0G0_USART5_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART6_1WIREDRIVER) || \
defined(CONFIG_STM32F0L0G0_USART7_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART8_1WIREDRIVER)
# define HAVE_1WIREDRIVER 1
#endif
/* Is there a serial console? */
#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER)
#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER)
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
@ -216,7 +216,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 1
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER)
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
@ -226,7 +226,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 2
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER)
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
@ -236,7 +236,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 3
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER)
#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -246,7 +246,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 4
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER)
#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -256,7 +256,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 5
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER)
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -266,7 +266,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 6
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER)
#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -277,7 +277,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 7
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER)
#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -315,35 +315,35 @@
/* Disable the DMA configuration on all unused USARTs */
#ifndef CONFIG_STM32F0L0_USART1_SERIALDRIVER
#ifndef CONFIG_STM32F0L0G0_USART1_SERIALDRIVER
# undef CONFIG_USART1_RXDMA
#endif
#ifndef CONFIG_STM32F0L0_USART2_SERIALDRIVER
#ifndef CONFIG_STM32F0L0G0_USART2_SERIALDRIVER
# undef CONFIG_USART2_RXDMA
#endif
#ifndef CONFIG_STM32F0L0_USART3_SERIALDRIVER
#ifndef CONFIG_STM32F0L0G0_USART3_SERIALDRIVER
# undef CONFIG_USART3_RXDMA
#endif
#ifndef CONFIG_STM32F0L0_USART4_SERIALDRIVER
#ifndef CONFIG_STM32F0L0G0_USART4_SERIALDRIVER
# undef CONFIG_USART4_RXDMA
#endif
#ifndef CONFIG_STM32F0L0_USART5_SERIALDRIVER
#ifndef CONFIG_STM32F0L0G0_USART5_SERIALDRIVER
# undef CONFIG_USART5_RXDMA
#endif
#ifndef CONFIG_STM32F0L0_USART6_SERIALDRIVER
#ifndef CONFIG_STM32F0L0G0_USART6_SERIALDRIVER
# undef CONFIG_USART6_RXDMA
#endif
#ifndef CONFIG_STM32F0L0_USART7_SERIALDRIVER
#ifndef CONFIG_STM32F0L0G0_USART7_SERIALDRIVER
# undef CONFIG_USART7_RXDMA
#endif
#ifndef CONFIG_STM32F0L0_USART8_SERIALDRIVER
#ifndef CONFIG_STM32F0L0G0_USART8_SERIALDRIVER
# undef CONFIG_USART8_RXDMA
#endif
@ -381,21 +381,21 @@
/* Is DMA used on all (enabled) USARTs */
#define SERIAL_HAVE_ONLY_DMA 1
#if defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
#if defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
#elif defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
#elif defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA)
#elif defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA)
#elif defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA)
#elif defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA)
#elif defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA)
#elif defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#endif
@ -460,4 +460,4 @@ void stm32_serial_dma_poll(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H */

16
arch/arm/src/stm32f0l0/stm32_usbdev.c → arch/arm/src/stm32f0l0g0/stm32_usbdev.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32_usbdev.c
* arch/arm/src/stm32f0l0g0/stm32_usbdev.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.orgr>
@ -66,7 +66,7 @@
#include "stm32_gpio.h"
#include "stm32_usbdev.h"
#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32F0L0_USB)
#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32F0L0G0_USB)
/****************************************************************************
* Pre-processor Definitions
@ -87,7 +87,7 @@
*/
#ifndef CONFIG_DEBUG_USB_INFO
# undef CONFIG_STM32F0L0_USBDEV_REGDEBUG
# undef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
#endif
/* Initial interrupt mask: Reset + Suspend + Correct Transfer */
@ -370,7 +370,7 @@ struct stm32_usbdev_s
/* Register operations ******************************************************/
#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG
#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
static uint16_t stm32_getreg(uint32_t addr);
static void stm32_putreg(uint16_t val, uint32_t addr);
static void stm32_dumpep(int epno);
@ -631,7 +631,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
* Name: stm32_getreg
****************************************************************************/
#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG
#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
static uint16_t stm32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@ -689,7 +689,7 @@ static uint16_t stm32_getreg(uint32_t addr)
* Name: stm32_putreg
****************************************************************************/
#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG
#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
static void stm32_putreg(uint16_t val, uint32_t addr)
{
/* Show the register value being written */
@ -706,7 +706,7 @@ static void stm32_putreg(uint16_t val, uint32_t addr)
* Name: stm32_dumpep
****************************************************************************/
#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG
#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
static void stm32_dumpep(int epno)
{
uint32_t addr;
@ -3861,4 +3861,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
return OK;
}
#endif /* CONFIG_USBDEV && CONFIG_STM32F0L0_USB */
#endif /* CONFIG_USBDEV && CONFIG_STM32F0L0G0_USB */

8
arch/arm/src/stm32f0l0/stm32_usbdev.h → arch/arm/src/stm32f0l0g0/stm32_usbdev.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/stm32_usbdev.h
* arch/arm/src/stm32f0l0g0/stm32_usbdev.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H
/************************************************************************************
* Included Files
@ -93,4 +93,4 @@ void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H */

114
arch/arm/src/stm32f0l0/stm32f0_rcc.c → arch/arm/src/stm32f0l0g0/stm32f0_rcc.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0/stm32f0_rcc.c
* arch/arm/src/stm32f0l0g0/stm32f0_rcc.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -59,7 +59,7 @@
/* Determine if board wants to use HSI48 as 48 MHz oscillator. */
#if defined(CONFIG_STM32F0L0_HAVE_HSI48) && defined(STM32_USE_CLK48)
#if defined(CONFIG_STM32F0L0G0_HAVE_HSI48) && defined(STM32_USE_CLK48)
# if STM32_CLK48_SEL == RCC_CFGR3_CLK48_HSI48
# define STM32_USE_HSI48
# endif
@ -121,25 +121,25 @@ static inline void rcc_enableahb(void)
regval = getreg32(STM32_RCC_AHBENR);
#ifdef CONFIG_STM32F0L0_DMA1
#ifdef CONFIG_STM32F0L0G0_DMA1
/* DMA 1 clock enable */
regval |= RCC_AHBENR_DMA1EN;
#endif
#ifdef CONFIG_STM32F0L0_DMA2
#ifdef CONFIG_STM32F0L0G0_DMA2
/* DMA 2 clock enable */
regval |= RCC_AHBENR_DMA2EN;
#endif
#ifdef CONFIG_STM32F0L0_CRC
#ifdef CONFIG_STM32F0L0G0_CRC
/* CRC clock enable */
regval |= RCC_AHBENR_CRCEN;
#endif
#ifdef CONFIG_STM32F0L0_TSC
#ifdef CONFIG_STM32F0L0G0_TSC
/* TSC clock enable */
regval |= RCC_AHBENR_TSCEN;
@ -166,145 +166,145 @@ static inline void rcc_enableapb1(void)
regval = getreg32(STM32_RCC_APB1ENR);
#ifdef CONFIG_STM32F0L0_TIM2
#ifdef CONFIG_STM32F0L0G0_TIM2
/* Timer 2 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM2EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_TIM3
#ifdef CONFIG_STM32F0L0G0_TIM3
/* Timer 3 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM3EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_TIM4
#ifdef CONFIG_STM32F0L0G0_TIM4
/* Timer 4 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM4EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_TIM6
#ifdef CONFIG_STM32F0L0G0_TIM6
/* Timer 6 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM6EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_TIM7
#ifdef CONFIG_STM32F0L0G0_TIM7
/* Timer 7 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM7EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_TIM14
#ifdef CONFIG_STM32F0L0G0_TIM14
/* Timer 14 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM14EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_WWDG
#ifdef CONFIG_STM32F0L0G0_WWDG
/* Window Watchdog clock enable */
regval |= RCC_APB1ENR_WWDGEN;
#endif
#ifdef CONFIG_STM32F0L0_SPI2
#ifdef CONFIG_STM32F0L0G0_SPI2
/* SPI 2 clock enable */
regval |= RCC_APB1ENR_SPI2EN;
#endif
#ifdef CONFIG_STM32F0L0_USART2
#ifdef CONFIG_STM32F0L0G0_USART2
/* USART 2 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART2EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_USART3
#ifdef CONFIG_STM32F0L0G0_USART3
/* USART 3 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART3EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_USART4
#ifdef CONFIG_STM32F0L0G0_USART4
/* USART 4 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART4EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_USART5
#ifdef CONFIG_STM32F0L0G0_USART5
/* USART 5 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART5EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_I2C1
#ifdef CONFIG_STM32F0L0G0_I2C1
/* I2C 1 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_I2C1EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_I2C2
#ifdef CONFIG_STM32F0L0G0_I2C2
/* I2C 2 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_I2C2EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_USB
#ifdef CONFIG_STM32F0L0G0_USB
/* USB clock enable */
regval |= RCC_APB1ENR_USBEN;
#endif
#ifdef CONFIG_STM32F0L0_CAN1
#ifdef CONFIG_STM32F0L0G0_CAN1
/* CAN1 clock enable */
regval |= RCC_APB1ENR_CAN1EN;
#endif
#ifdef CONFIG_STM32F0L0_CRS
#ifdef CONFIG_STM32F0L0G0_CRS
/* Clock recovery system clock enable */
regval |= RCC_APB1ENR_CRSEN;
#endif
#ifdef CONFIG_STM32F0L0_PWR
#ifdef CONFIG_STM32F0L0G0_PWR
/* Power interface clock enable */
regval |= RCC_APB1ENR_PWREN;
#endif
#ifdef CONFIG_STM32F0L0_DAC1
#ifdef CONFIG_STM32F0L0G0_DAC1
/* DAC 1 interface clock enable */
regval |= RCC_APB1ENR_DAC1EN;
#endif
#ifdef CONFIG_STM32F0L0_CEC
#ifdef CONFIG_STM32F0L0G0_CEC
/* CEC interface clock enable */
regval |= RCC_APB1ENR_CECEN;
@ -331,84 +331,84 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32_RCC_APB2ENR);
#ifdef CONFIG_STM32F0L0_SYSCFG
#ifdef CONFIG_STM32F0L0G0_SYSCFG
/* SYSCFG clock */
regval |= RCC_APB2ENR_SYSCFGCOMPEN;
#endif
#ifdef CONFIG_STM32F0L0_USART6
#ifdef CONFIG_STM32F0L0G0_USART6
/* USART 6 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_USART6EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_USART7
#ifdef CONFIG_STM32F0L0G0_USART7
/* USART 7 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_USART7EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_USART8
#ifdef CONFIG_STM32F0L0G0_USART8
/* USART 8 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_USART8EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_ADC1
#ifdef CONFIG_STM32F0L0G0_ADC1
/* ADC 1 clock enable */
regval |= RCC_APB2ENR_ADC1EN;
#endif
#ifdef CONFIG_STM32F0L0_TIM1
#ifdef CONFIG_STM32F0L0G0_TIM1
/* Timer 1 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM1EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_SPI1
#ifdef CONFIG_STM32F0L0G0_SPI1
/* SPI 1 clock enable */
regval |= RCC_APB2ENR_SPI1EN;
#endif
#ifdef CONFIG_STM32F0L0_USART1
#ifdef CONFIG_STM32F0L0G0_USART1
/* USART1 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_USART1EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_TIM15
#ifdef CONFIG_STM32F0L0G0_TIM15
/* Timer 15 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM15EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_TIM16
#ifdef CONFIG_STM32F0L0G0_TIM16
/* Timer 16 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM16EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0_TIM17
#ifdef CONFIG_STM32F0L0G0_TIM17
/* Timer 17 clock enable */
#ifdef CONFIG_STM32F0L0_FORCEPOWER
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM17EN;
#endif
#endif

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