diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c0cd7e3dee..99ec0e7025 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -684,7 +684,7 @@ config ARCH_CHIP default "sam34" if ARCH_CHIP_SAM34 default "samv7" if ARCH_CHIP_SAMV7 default "stm32" if ARCH_CHIP_STM32 - default "stm32f0l0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 + default "stm32f0l0g0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 default "stm32f7" if ARCH_CHIP_STM32F7 default "stm32h7" if ARCH_CHIP_STM32H7 default "stm32l4" if ARCH_CHIP_STM32L4 @@ -917,7 +917,7 @@ if ARCH_CHIP_STM32 source arch/arm/src/stm32/Kconfig endif if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 -source arch/arm/src/stm32f0l0/Kconfig +source arch/arm/src/stm32f0l0g0/Kconfig endif if ARCH_CHIP_STM32F7 source arch/arm/src/stm32f7/Kconfig diff --git a/arch/arm/include/stm32f0l0/chip.h b/arch/arm/include/stm32f0l0g0/chip.h similarity index 99% rename from arch/arm/include/stm32f0l0/chip.h rename to arch/arm/include/stm32f0l0g0/chip.h index be1dc05a6d..b05fc7eb28 100644 --- a/arch/arm/include/stm32f0l0/chip.h +++ b/arch/arm/include/stm32f0l0g0/chip.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/include/stm32f0l0/chip.h + * arch/arm/include/stm32f0l0g0/chip.h * * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H -#define __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H +#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H /************************************************************************************ * Included Files @@ -552,4 +552,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H */ diff --git a/arch/arm/include/stm32f0l0/irq.h b/arch/arm/include/stm32f0l0g0/irq.h similarity index 93% rename from arch/arm/include/stm32f0l0/irq.h rename to arch/arm/include/stm32f0l0g0/irq.h index adb46bc455..61c63c4f80 100644 --- a/arch/arm/include/stm32f0l0/irq.h +++ b/arch/arm/include/stm32f0l0g0/irq.h @@ -38,8 +38,8 @@ * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H /**************************************************************************** * Included Files @@ -48,7 +48,7 @@ #ifndef __ASSEMBLY__ # include #endif -#include +#include /**************************************************************************** * Pre-processor Definitions @@ -79,11 +79,11 @@ /* Include MCU-specific external interrupt definitions */ #if defined(CONFIG_ARCH_CHIP_STM32F0) -# include +# include #elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include +# include #elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include +# include #else # error Unrecognized STM32 Cortex M0 family #endif @@ -119,4 +119,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H */ diff --git a/arch/arm/include/stm32f0l0/stm32f0_irq.h b/arch/arm/include/stm32f0l0g0/stm32f0_irq.h similarity index 96% rename from arch/arm/include/stm32f0l0/stm32f0_irq.h rename to arch/arm/include/stm32f0l0g0/stm32f0_irq.h index f04da690a8..3ba8a1eef0 100644 --- a/arch/arm/include/stm32f0l0/stm32f0_irq.h +++ b/arch/arm/include/stm32f0l0g0/stm32f0_irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32f0l0/stm32f0_irq.h + * arch/arm/include/stm32f0l0g0/stm32f0_irq.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -38,8 +38,8 @@ * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H /**************************************************************************** * Included Files @@ -47,7 +47,7 @@ #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions @@ -58,7 +58,7 @@ * to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be found - * in nuttx/arch/arm/include/stm32f0l0/irq.h + * in nuttx/arch/arm/include/stm32f0l0g0/irq.h */ #define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: WWDG */ @@ -142,4 +142,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H */ diff --git a/arch/arm/include/stm32f0l0/stm32g0_irq.h b/arch/arm/include/stm32f0l0g0/stm32g0_irq.h similarity index 96% rename from arch/arm/include/stm32f0l0/stm32g0_irq.h rename to arch/arm/include/stm32f0l0g0/stm32g0_irq.h index c5c6b40267..0b646f33d6 100644 --- a/arch/arm/include/stm32f0l0/stm32g0_irq.h +++ b/arch/arm/include/stm32f0l0g0/stm32g0_irq.h @@ -1,5 +1,5 @@ /**************************************************************************************************** - * arch/arm/include/stm32f0l0/stm32g0_irq.h + * arch/arm/include/stm32f0l0g0/stm32g0_irq.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -35,8 +35,8 @@ /* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32G0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32G0_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H /**************************************************************************************************** * Included Files @@ -44,7 +44,7 @@ #include #include -#include +#include /**************************************************************************************************** * Pre-processor Definitions @@ -55,7 +55,7 @@ * to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be found - * in nuttx/arch/arm/include/stm32f0l0/irq.h + * in nuttx/arch/arm/include/stm32f0l0g0/irq.h */ #define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */ @@ -139,4 +139,4 @@ extern "C" #endif #endif -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32G0_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H */ diff --git a/arch/arm/include/stm32f0l0/stm32l0_irq.h b/arch/arm/include/stm32f0l0g0/stm32l0_irq.h similarity index 96% rename from arch/arm/include/stm32f0l0/stm32l0_irq.h rename to arch/arm/include/stm32f0l0g0/stm32l0_irq.h index a7bf235c7c..236d10d334 100644 --- a/arch/arm/include/stm32f0l0/stm32l0_irq.h +++ b/arch/arm/include/stm32f0l0g0/stm32l0_irq.h @@ -1,5 +1,5 @@ /**************************************************************************************************** - * arch/arm/include/stm32f0l0/stm32l0_irq.h + * arch/arm/include/stm32f0l0g0/stm32l0_irq.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -35,8 +35,8 @@ /* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H /**************************************************************************************************** * Included Files @@ -44,7 +44,7 @@ #include #include -#include +#include /**************************************************************************************************** * Pre-processor Definitions @@ -55,7 +55,7 @@ * to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be found - * in nuttx/arch/arm/include/stm32f0l0/irq.h + * in nuttx/arch/arm/include/stm32f0l0g0/irq.h */ #define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */ @@ -129,4 +129,4 @@ extern "C" #endif #endif -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H */ diff --git a/arch/arm/src/stm32f0l0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig similarity index 57% rename from arch/arm/src/stm32f0l0/Kconfig rename to arch/arm/src/stm32f0l0g0/Kconfig index be6d115074..47e19558f4 100644 --- a/arch/arm/src/stm32f0l0/Kconfig +++ b/arch/arm/src/stm32f0l0g0/Kconfig @@ -14,505 +14,505 @@ choice config ARCH_CHIP_STM32F030C6 bool "STM32F030C6" - select STM32F0L0_STM32F03X - select STM32F0L0_VALUELINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030C8 bool "STM32F030C8" - select STM32F0L0_STM32F03X - select STM32F0L0_VALUELINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030CC bool "STM32F030CC" - select STM32F0L0_STM32F03X - select STM32F0L0_VALUELINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030F4 bool "STM32F030F4" - select STM32F0L0_STM32F03X - select STM32F0L0_VALUELINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030K6 bool "STM32F030K6" - select STM32F0L0_STM32F03X - select STM32F0L0_VALUELINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030R8 bool "STM32F030R8" - select STM32F0L0_STM32F03X - select STM32F0L0_VALUELINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030RC bool "STM32F030RC" - select STM32F0L0_STM32F03X - select STM32F0L0_VALUELINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031C4 bool "STM32F031C4" - select STM32F0L0_STM32F03X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031C6 bool "STM32F031C6" - select STM32F0L0_STM32F03X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031E6 bool "STM32F031E6" - select STM32F0L0_STM32F03X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031F4 bool "STM32F031F4" - select STM32F0L0_STM32F03X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031F6 bool "STM32F031F6" - select STM32F0L0_STM32F03X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031G4 bool "STM32F031G4" - select STM32F0L0_STM32F03X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031G6 bool "STM32F031G6" - select STM32F0L0_STM32F03X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031K4 bool "STM32F031K4" - select STM32F0L0_STM32F03X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031K6 bool "STM32F031K6" - select STM32F0L0_STM32F03X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038C6 bool "STM32F038C6" - select STM32F0L0_STM32F03X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038E6 bool "STM32F038E6" - select STM32F0L0_STM32F03X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038F6 bool "STM32F038F6" - select STM32F0L0_STM32F03X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038G6 bool "STM32F038G6" - select STM32F0L0_STM32F03X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038K6 bool "STM32F038K6" - select STM32F0L0_STM32F03X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F03X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042C4 bool "STM32F042C4" - select STM32F0L0_STM32F04X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F04X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042C6 bool "STM32F042C6" - select STM32F0L0_STM32F04X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F04X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042F4 bool "STM32F042F4" - select STM32F0L0_STM32F04X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F04X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042F6 bool "STM32F042F6" - select STM32F0L0_STM32F04X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F04X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042G4 bool "STM32F042G4" - select STM32F0L0_STM32F04X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F04X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042G6 bool "STM32F042G6" - select STM32F0L0_STM32F04X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F04X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042K4 bool "STM32F042K4" - select STM32F0L0_STM32F04X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F04X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042K6 bool "STM32F042K6" - select STM32F0L0_STM32F04X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F04X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042T6 bool "STM32F042T6" - select STM32F0L0_STM32F04X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F04X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F048C6 bool "STM32F048C6" - select STM32F0L0_STM32F04X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F04X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F048G6 bool "STM32F048G6" - select STM32F0L0_STM32F04X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F04X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F048T6 bool "STM32F048T6" - select STM32F0L0_STM32F04X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F04X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051C4 bool "STM32F051C4" - select STM32F0L0_STM32F05X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F05X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051C6 bool "STM32F051C6" - select STM32F0L0_STM32F05X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F05X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051C8 bool "STM32F051C8" - select STM32F0L0_STM32F05X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F05X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051K4 bool "STM32F051K4" - select STM32F0L0_STM32F05X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F05X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051K6 bool "STM32F051K6" - select STM32F0L0_STM32F05X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F05X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051K8 bool "STM32F051K8" - select STM32F0L0_STM32F05X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F05X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051R4 bool "STM32F051R4" - select STM32F0L0_STM32F05X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F05X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051R6 bool "STM32F051R6" - select STM32F0L0_STM32F05X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F05X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051R8 bool "STM32F051R8" - select STM32F0L0_STM32F05X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F05X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051T8 bool "STM32F051T8" - select STM32F0L0_STM32F05X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F05X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F058C8 bool "STM32F058C8" - select STM32F0L0_STM32F05X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F05X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F058R8 bool "STM32F058R8" - select STM32F0L0_STM32F05X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F05X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F058T8 bool "STM32F058T8" - select STM32F0L0_STM32F05X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F05X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F070C6 bool "STM32F070C6" - select STM32F0L0_STM32F07X - select STM32F0L0_VALUELINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F070CB bool "STM32F070CB" - select STM32F0L0_STM32F07X - select STM32F0L0_VALUELINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F070F6 bool "STM32F070F6" - select STM32F0L0_STM32F07X - select STM32F0L0_VALUELINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F070RB bool "STM32F070RB" - select STM32F0L0_STM32F07X - select STM32F0L0_VALUELINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071C8 bool "STM32F071C8" - select STM32F0L0_STM32F07X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071CB bool "STM32F071CB" - select STM32F0L0_STM32F07X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071RB bool "STM32F071RB" - select STM32F0L0_STM32F07X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071V8 bool "STM32F071V8" - select STM32F0L0_STM32F07X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071VB bool "STM32F071VB" - select STM32F0L0_STM32F07X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072C8 bool "STM32F072C8" - select STM32F0L0_STM32F07X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072CB bool "STM32F072CB" - select STM32F0L0_STM32F07X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072R8 bool "STM32F072R8" - select STM32F0L0_STM32F07X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072RB bool "STM32F072RB" - select STM32F0L0_STM32F07X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072V8 bool "STM32F072V8" - select STM32F0L0_STM32F07X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072VB bool "STM32F072VB" - select STM32F0L0_STM32F07X - select STM32F0L0_USBLINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F078CB bool "STM32F078CB" - select STM32F0L0_STM32F07X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F078RB bool "STM32F078RB" - select STM32F0L0_STM32F07X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F078VB bool "STM32F078VB" - select STM32F0L0_STM32F07X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F07X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091CB bool "STM32F091CB" - select STM32F0L0_STM32F09X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F09X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091CC bool "STM32F091CC" - select STM32F0L0_STM32F09X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F09X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091RB bool "STM32F091RB" - select STM32F0L0_STM32F09X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F09X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091RC bool "STM32F091RC" - select STM32F0L0_STM32F09X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F09X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091VB bool "STM32F091VB" - select STM32F0L0_STM32F09X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F09X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091VC bool "STM32F091VC" - select STM32F0L0_STM32F09X - select STM32F0L0_ACCESSLINE + select STM32F0L0G0_STM32F09X + select STM32F0L0G0_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F098CC bool "STM32F098CC" - select STM32F0L0_STM32F09X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F09X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F098RC bool "STM32F098RC" - select STM32F0L0_STM32F09X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F09X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F098VC bool "STM32F098VC" - select STM32F0L0_STM32F09X - select STM32F0L0_LOWVOLTLINE + select STM32F0L0G0_STM32F09X + select STM32F0L0G0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32G071EB bool "STM32G071EB" - select STM32F0L0_STM32G0 + select STM32F0L0G0_STM32G0 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071G8 bool "STM32G071G8" - select STM32F0L0_STM32G0 + select STM32F0L0G0_STM32G0 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071GB bool "STM32G071GB" - select STM32F0L0_STM32G0 + select STM32F0L0G0_STM32G0 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071G8XN bool "STM32G071G8XN" - select STM32F0L0_STM32G0 + select STM32F0L0G0_STM32G0 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071GBXN bool "STM32G071GBXN" - select STM32F0L0_STM32G0 + select STM32F0L0G0_STM32G0 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071K8 bool "STM32G071K8" - select STM32F0L0_STM32G0 + select STM32F0L0G0_STM32G0 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071KB bool "STM32G071KB" - select STM32F0L0_STM32G0 + select STM32F0L0G0_STM32G0 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071K8XN bool "STM32G071K8XN" - select STM32F0L0_STM32G0 + select STM32F0L0G0_STM32G0 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071KBXN bool "STM32G071KBXN" - select STM32F0L0_STM32G0 + select STM32F0L0G0_STM32G0 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071C8 bool "STM32G071C8" - select STM32F0L0_STM32G0 + select STM32F0L0G0_STM32G0 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071CB bool "STM32G071CB" - select STM32F0L0_STM32G0 + select STM32F0L0G0_STM32G0 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071R8 bool "STM32G071R8" - select STM32F0L0_STM32G0 + select STM32F0L0G0_STM32G0 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071RB bool "STM32G071RB" - select STM32F0L0_STM32G0 + select STM32F0L0G0_STM32G0 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32L071K8 @@ -533,86 +533,86 @@ config ARCH_CHIP_STM32L071KZ config ARCH_CHIP_STM32L071C8 bool "STM32L071C8" select ARCH_CHIP_STM32L071XX - select STM32F0L0_HAVE_USART5 - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_USART5 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071CB bool "STM32L071CB" select ARCH_CHIP_STM32L071XX - select STM32F0L0_HAVE_USART5 - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_USART5 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071CZ bool "STM32L071CZ" select ARCH_CHIP_STM32L071XX - select STM32F0L0_HAVE_USART5 - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_USART5 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071V8 bool "STM32L071V8" select ARCH_CHIP_STM32L071XX - select STM32F0L0_HAVE_USART5 - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_USART5 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071VB bool "STM32L071VB" select ARCH_CHIP_STM32L071XX - select STM32F0L0_HAVE_USART5 - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_USART5 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071VZ bool "STM32L071VZ" select ARCH_CHIP_STM32L071XX - select STM32F0L0_HAVE_USART5 - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_USART5 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071RB bool "STM32L071RB" select ARCH_CHIP_STM32L071XX - select STM32F0L0_HAVE_USART5 - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_USART5 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071RZ bool "STM32L071RZ" select ARCH_CHIP_STM32L071XX - select STM32F0L0_HAVE_USART5 - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_USART5 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072V8 bool "STM32L072V8" select ARCH_CHIP_STM32L072XX - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072VB bool "STM32L072VB" select ARCH_CHIP_STM32L072XX - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072VZ bool "STM32L072VZ" select ARCH_CHIP_STM32L072XX - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072KB @@ -628,29 +628,29 @@ config ARCH_CHIP_STM32L072KZ config ARCH_CHIP_STM32L072CB bool "STM32L072CB" select ARCH_CHIP_STM32L072XX - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072CZ bool "STM32L072CZ" select ARCH_CHIP_STM32L072XX - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072RB bool "STM32L072RB" select ARCH_CHIP_STM32L072XX - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072RZ bool "STM32L072RZ" select ARCH_CHIP_STM32L072XX - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C3 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073V8 @@ -692,7 +692,7 @@ endchoice # ST STM32F0/L0 Chip Selection choice prompt "Override Flash Size Designator" - default STM32F0L0_FLASH_CONFIG_DEFAULT + default STM32F0L0G0_FLASH_CONFIG_DEFAULT depends on ARCH_CHIP_STM32 ---help--- STM32F series parts numbering (sans the package type) ends with a number or letter @@ -722,183 +722,183 @@ choice If an STM32F42xxx or Series parts is chosen the default Flash configuration will be 'G' and can be set herein to 'I' to choose the larger FLASH part. -config STM32F0L0_FLASH_CONFIG_DEFAULT +config STM32F0L0G0_FLASH_CONFIG_DEFAULT bool "Default" -config STM32F0L0_FLASH_CONFIG_4 +config STM32F0L0G0_FLASH_CONFIG_4 bool "4 16KiB" -config STM32F0L0_FLASH_CONFIG_6 +config STM32F0L0G0_FLASH_CONFIG_6 bool "6 32KiB" -config STM32F0L0_FLASH_CONFIG_8 +config STM32F0L0G0_FLASH_CONFIG_8 bool "8 64KiB" -config STM32F0L0_FLASH_CONFIG_B +config STM32F0L0G0_FLASH_CONFIG_B bool "B 128KiB" -config STM32F0L0_FLASH_CONFIG_C +config STM32F0L0G0_FLASH_CONFIG_C bool "C 256KiB" -config STM32F0L0_FLASH_CONFIG_D +config STM32F0L0G0_FLASH_CONFIG_D bool "D 384KiB" -config STM32F0L0_FLASH_CONFIG_E +config STM32F0L0G0_FLASH_CONFIG_E bool "E 512KiB" -config STM32F0L0_FLASH_CONFIG_F +config STM32F0L0G0_FLASH_CONFIG_F bool "F 768KiB" -config STM32F0L0_FLASH_CONFIG_G +config STM32F0L0G0_FLASH_CONFIG_G bool "G 1024KiB" -config STM32F0L0_FLASH_CONFIG_I +config STM32F0L0G0_FLASH_CONFIG_I bool "I 2048KiB" endchoice -config STM32F0L0_STM32F0 +config STM32F0L0G0_STM32F0 bool default n - select STM32F0L0_HAVE_USART3 - select STM32F0L0_HAVE_USART4 - select STM32F0L0_HAVE_TIM1 - select STM32F0L0_HAVE_TIM2 - select STM32F0L0_HAVE_TIM3 - select STM32F0L0_HAVE_TIM6 - select STM32F0L0_HAVE_TIM7 - select STM32F0L0_HAVE_TIM14 - select STM32F0L0_HAVE_TIM15 - select STM32F0L0_HAVE_TIM16 - select STM32F0L0_HAVE_TIM17 - select STM32F0L0_HAVE_ADC1_DMA - select STM32F0L0_HAVE_IP_USART_V1 - select STM32F0L0_HAVE_IP_EXTI_V1 + select STM32F0L0G0_HAVE_USART3 + select STM32F0L0G0_HAVE_USART4 + select STM32F0L0G0_HAVE_TIM1 + select STM32F0L0G0_HAVE_TIM2 + select STM32F0L0G0_HAVE_TIM3 + select STM32F0L0G0_HAVE_TIM6 + select STM32F0L0G0_HAVE_TIM7 + select STM32F0L0G0_HAVE_TIM14 + select STM32F0L0G0_HAVE_TIM15 + select STM32F0L0G0_HAVE_TIM16 + select STM32F0L0G0_HAVE_TIM17 + select STM32F0L0G0_HAVE_ADC1_DMA + select STM32F0L0G0_HAVE_IP_USART_V1 + select STM32F0L0G0_HAVE_IP_EXTI_V1 -config STM32F0L0_STM32G0 +config STM32F0L0G0_STM32G0 bool default n - select STM32F0L0_HAVE_DMAMUX - select STM32F0L0_HAVE_IP_USART_V2 - select STM32F0L0_HAVE_IP_EXTI_V2 + select STM32F0L0G0_HAVE_DMAMUX + select STM32F0L0G0_HAVE_IP_USART_V2 + select STM32F0L0G0_HAVE_IP_EXTI_V2 -config STM32F0L0_STM32L0 +config STM32F0L0G0_STM32L0 bool default n - select STM32F0L0_ENERGYLITE - select STM32F0L0_HAVE_VREFINT - select STM32F0L0_HAVE_ADC1_DMA - select STM32F0L0_HAVE_IP_USART_V1 - select STM32F0L0_HAVE_IP_EXTI_V1 + select STM32F0L0G0_ENERGYLITE + select STM32F0L0G0_HAVE_VREFINT + select STM32F0L0G0_HAVE_ADC1_DMA + select STM32F0L0G0_HAVE_IP_USART_V1 + select STM32F0L0G0_HAVE_IP_EXTI_V1 -config STM32F0L0_STM32F03X +config STM32F0L0G0_STM32F03X bool default n - select STM32F0L0_STM32F0 + select STM32F0L0G0_STM32F0 -config STM32F0L0_STM32F04X +config STM32F0L0G0_STM32F04X bool default n - select STM32F0L0_STM32F0 + select STM32F0L0G0_STM32F0 -config STM32F0L0_STM32F05X +config STM32F0L0G0_STM32F05X bool default n - select STM32F0L0_STM32F0 + select STM32F0L0G0_STM32F0 -config STM32F0L0_STM32F07X +config STM32F0L0G0_STM32F07X bool default n - select STM32F0L0_STM32F0 + select STM32F0L0G0_STM32F0 -config STM32F0L0_STM32F09X +config STM32F0L0G0_STM32F09X bool default n - select STM32F0L0_STM32F0 - select STM32F0L0_HAVE_HSI48 - select STM32F0L0_HAVE_DMA2 + select STM32F0L0G0_STM32F0 + select STM32F0L0G0_HAVE_HSI48 + select STM32F0L0G0_HAVE_DMA2 -config STM32F0L0_VALUELINE +config STM32F0L0G0_VALUELINE bool default n - select STM32F0L0_HAVE_USART5 - select STM32F0L0_HAVE_SPI2 if STM32F0L0_HIGHDENSITY - select STM32F0L0_HAVE_SPI3 if STM32F0L0_HIGHDENSITY + select STM32F0L0G0_HAVE_USART5 + select STM32F0L0G0_HAVE_SPI2 if STM32F0L0G0_HIGHDENSITY + select STM32F0L0G0_HAVE_SPI3 if STM32F0L0G0_HIGHDENSITY -config STM32F0L0_ACCESSLINE +config STM32F0L0G0_ACCESSLINE bool default n - select STM32F0L0_HAVE_USART5 - select STM32F0L0_HAVE_CAN1 - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_SPI3 + select STM32F0L0G0_HAVE_USART5 + select STM32F0L0G0_HAVE_CAN1 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_SPI3 -config STM32F0L0_LOWVOLTLINE +config STM32F0L0G0_LOWVOLTLINE bool default n - select STM32F0L0_HAVE_USART5 - select STM32F0L0_HAVE_CAN1 - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_SPI3 + select STM32F0L0G0_HAVE_USART5 + select STM32F0L0G0_HAVE_CAN1 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_SPI3 -config STM32F0L0_USBLINE +config STM32F0L0G0_USBLINE bool default n - select STM32F0L0_HAVE_HSI48 - select STM32F0L0_HAVE_CAN1 - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_SPI3 - select STM32F0L0_HAVE_USBDEV + select STM32F0L0G0_HAVE_HSI48 + select STM32F0L0G0_HAVE_CAN1 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_SPI3 + select STM32F0L0G0_HAVE_USBDEV -config STM32F0L0_ENERGYLITE +config STM32F0L0G0_ENERGYLITE bool default n config ARCH_CHIP_STM32L071XX bool - select STM32F0L0_STM32L0 - select STM32F0L0_HAVE_RNG - select STM32F0L0_HAVE_HSI48 - select STM32F0L0_HAVE_USART4 + select STM32F0L0G0_STM32L0 + select STM32F0L0G0_HAVE_RNG + select STM32F0L0G0_HAVE_HSI48 + select STM32F0L0G0_HAVE_USART4 config ARCH_CHIP_STM32L072XX bool - select STM32F0L0_STM32L0 - select STM32F0L0_HAVE_RNG - select STM32F0L0_HAVE_HSI48 - select STM32F0L0_HAVE_USART4 - select STM32F0L0_HAVE_USART5 - select STM32F0L0_HAVE_I2C2 - select STM32F0L0_HAVE_USBDEV + select STM32F0L0G0_STM32L0 + select STM32F0L0G0_HAVE_RNG + select STM32F0L0G0_HAVE_HSI48 + select STM32F0L0G0_HAVE_USART4 + select STM32F0L0G0_HAVE_USART5 + select STM32F0L0G0_HAVE_I2C2 + select STM32F0L0G0_HAVE_USBDEV config ARCH_CHIP_STM32L073XX bool - select STM32F0L0_STM32L0 - select STM32F0L0_HAVE_RNG - select STM32F0L0_HAVE_HSI48 - select STM32F0L0_HAVE_USART4 - select STM32F0L0_HAVE_USART5 - select STM32F0L0_HAVE_SPI2 - select STM32F0L0_HAVE_I2C2 - select STM32F0L0_HAVE_I2C3 - select STM32F0L0_HAVE_USBDEV + select STM32F0L0G0_STM32L0 + select STM32F0L0G0_HAVE_RNG + select STM32F0L0G0_HAVE_HSI48 + select STM32F0L0G0_HAVE_USART4 + select STM32F0L0G0_HAVE_USART5 + select STM32F0L0G0_HAVE_SPI2 + select STM32F0L0G0_HAVE_I2C2 + select STM32F0L0G0_HAVE_I2C3 + select STM32F0L0G0_HAVE_USBDEV -config STM32F0L0_DFU +config STM32F0L0G0_DFU bool "DFU bootloader" default n - depends on !STM32F0L0_VALUELINE + depends on !STM32F0L0G0_VALUELINE ---help--- Configure and position code for use with the STMicro DFU bootloader. Do not select this option if you will load code using JTAG/SWM. choice prompt "SysTick clock source" - default STM32F0L0_SYSTICK_CORECLK + default STM32F0L0G0_SYSTICK_CORECLK -config STM32F0L0_SYSTICK_CORECLK +config STM32F0L0G0_SYSTICK_CORECLK bool "Cortex-M0 core clock" -config STM32F0L0_SYSTICK_CORECLK_DIV16 +config STM32F0L0G0_SYSTICK_CORECLK_DIV16 bool "Cortex-M0 core clock divided by 16" endchoice @@ -908,554 +908,554 @@ menu "STM32 Peripheral Support" # These "hidden" settings determine is a peripheral option is available for the # selection MCU -config STM32F0L0_HAVE_AES +config STM32F0L0G0_HAVE_AES bool default n -config STM32F0L0_HAVE_VREFINT +config STM32F0L0G0_HAVE_VREFINT bool default n -config STM32F0L0_HAVE_CCM +config STM32F0L0G0_HAVE_CCM bool default n -config STM32F0L0_HAVE_HSI48 +config STM32F0L0G0_HAVE_HSI48 bool default n -config STM32F0L0_HAVE_LCD +config STM32F0L0G0_HAVE_LCD bool default n -config STM32F0L0_HAVE_USBDEV +config STM32F0L0G0_HAVE_USBDEV bool default n -config STM32F0L0_HAVE_FSMC +config STM32F0L0G0_HAVE_FSMC bool default n -config STM32F0L0_HAVE_USART3 +config STM32F0L0G0_HAVE_USART3 bool default n -config STM32F0L0_HAVE_USART4 +config STM32F0L0G0_HAVE_USART4 bool default n -config STM32F0L0_HAVE_USART5 +config STM32F0L0G0_HAVE_USART5 bool default n -config STM32F0L0_HAVE_USART6 +config STM32F0L0G0_HAVE_USART6 bool default n -config STM32F0L0_HAVE_USART7 +config STM32F0L0G0_HAVE_USART7 bool default n -config STM32F0L0_HAVE_USART8 +config STM32F0L0G0_HAVE_USART8 bool default n -config STM32F0L0_HAVE_TIM1 +config STM32F0L0G0_HAVE_TIM1 bool default n -config STM32F0L0_HAVE_TIM2 +config STM32F0L0G0_HAVE_TIM2 bool default n -config STM32F0L0_HAVE_TIM3 +config STM32F0L0G0_HAVE_TIM3 bool default n -config STM32F0L0_HAVE_TIM6 +config STM32F0L0G0_HAVE_TIM6 bool default n -config STM32F0L0_HAVE_TIM7 +config STM32F0L0G0_HAVE_TIM7 bool default n -config STM32F0L0_HAVE_TIM14 +config STM32F0L0G0_HAVE_TIM14 bool default n -config STM32F0L0_HAVE_TIM15 +config STM32F0L0G0_HAVE_TIM15 bool default n -config STM32F0L0_HAVE_TIM16 +config STM32F0L0G0_HAVE_TIM16 bool default n -config STM32F0L0_HAVE_TIM17 +config STM32F0L0G0_HAVE_TIM17 bool default n -config STM32F0L0_HAVE_TSC +config STM32F0L0G0_HAVE_TSC bool default n -config STM32F0L0_HAVE_ADC1_DMA +config STM32F0L0G0_HAVE_ADC1_DMA bool default n -config STM32F0L0_HAVE_CEC +config STM32F0L0G0_HAVE_CEC bool default n -config STM32F0L0_HAVE_CAN1 +config STM32F0L0G0_HAVE_CAN1 bool default n -config STM32F0L0_HAVE_COMP1 +config STM32F0L0G0_HAVE_COMP1 bool default n -config STM32F0L0_HAVE_COMP2 +config STM32F0L0G0_HAVE_COMP2 bool default n -config STM32F0L0_HAVE_DAC1 +config STM32F0L0G0_HAVE_DAC1 bool default n -config STM32F0L0_HAVE_DMAMUX +config STM32F0L0G0_HAVE_DMAMUX bool default n -config STM32F0L0_HAVE_DMA2 +config STM32F0L0G0_HAVE_DMA2 bool default n -config STM32F0L0_HAVE_RNG +config STM32F0L0G0_HAVE_RNG bool default n -config STM32F0L0_HAVE_I2C2 +config STM32F0L0G0_HAVE_I2C2 bool default n -config STM32F0L0_HAVE_I2C3 +config STM32F0L0G0_HAVE_I2C3 bool default n -config STM32F0L0_HAVE_SPI2 +config STM32F0L0G0_HAVE_SPI2 bool default n -config STM32F0L0_HAVE_SPI3 +config STM32F0L0G0_HAVE_SPI3 bool default n -config STM32F0L0_HAVE_SPI4 +config STM32F0L0G0_HAVE_SPI4 bool default n -config STM32F0L0_HAVE_SPI5 +config STM32F0L0G0_HAVE_SPI5 bool default n -config STM32F0L0_HAVE_SPI6 +config STM32F0L0G0_HAVE_SPI6 bool default n -config STM32F0L0_HAVE_SAIPLL +config STM32F0L0G0_HAVE_SAIPLL bool default n -config STM32F0L0_HAVE_SDIO +config STM32F0L0G0_HAVE_SDIO bool default n -config STM32F0L0_HAVE_I2SPLL +config STM32F0L0G0_HAVE_I2SPLL bool default n -config STM32F0L0_HAVE_OPAMP1 +config STM32F0L0G0_HAVE_OPAMP1 bool default n -config STM32F0L0_HAVE_OPAMP2 +config STM32F0L0G0_HAVE_OPAMP2 bool default n -config STM32F0L0_HAVE_OPAMP3 +config STM32F0L0G0_HAVE_OPAMP3 bool default n -config STM32F0L0_HAVE_OPAMP4 +config STM32F0L0G0_HAVE_OPAMP4 bool default n # These are STM32 peripherals IP blocks -config STM32F0L0_HAVE_IP_USART_V1 +config STM32F0L0G0_HAVE_IP_USART_V1 bool default n -config STM32F0L0_HAVE_IP_USART_V2 +config STM32F0L0G0_HAVE_IP_USART_V2 bool default n -config STM32F0L0_HAVE_IP_EXTI_V1 +config STM32F0L0G0_HAVE_IP_EXTI_V1 bool default n -config STM32F0L0_HAVE_IP_EXTI_V2 +config STM32F0L0G0_HAVE_IP_EXTI_V2 bool default n # These are the peripheral selections proper -config STM32F0L0_ADC1 +config STM32F0L0G0_ADC1 bool "ADC1" default n depends on EXPERIMENTAL - select STM32F0L0_ADC + select STM32F0L0G0_ADC -config STM32F0L0_COMP1 +config STM32F0L0G0_COMP1 bool "COMP1" default n - depends on STM32F0L0_HAVE_COMP1 + depends on STM32F0L0G0_HAVE_COMP1 -config STM32F0L0_COMP2 +config STM32F0L0G0_COMP2 bool "COMP2" default n - depends on STM32F0L0_HAVE_COMP2 + depends on STM32F0L0G0_HAVE_COMP2 -config STM32F0L0_BKP +config STM32F0L0G0_BKP bool "BKP" default n -config STM32F0L0_BKPSRAM +config STM32F0L0G0_BKPSRAM bool "Enable BKP RAM Domain" default n -config STM32F0L0_CAN1 +config STM32F0L0G0_CAN1 bool "CAN1" default n select CAN - select STM32F0L0_CAN - depends on STM32F0L0_HAVE_CAN1 + select STM32F0L0G0_CAN + depends on STM32F0L0G0_HAVE_CAN1 -config STM32F0L0_AES +config STM32F0L0G0_AES bool "128-bit AES" default n - depends on STM32F0L0_HAVE_AES + depends on STM32F0L0G0_HAVE_AES select CRYPTO_AES192_DISABLE if CRYPTO_ALGTEST select CRYPTO_AES256_DISABLE if CRYPTO_ALGTEST -config STM32F0L0_VREFINT +config STM32F0L0G0_VREFINT bool "Enable VREFINT" default n - depends on STM32F0L0_HAVE_VREFINT + depends on STM32F0L0G0_HAVE_VREFINT -config STM32F0L0_CEC +config STM32F0L0G0_CEC bool "CEC" default n - depends on STM32F0L0_HAVE_CEC + depends on STM32F0L0G0_HAVE_CEC -config STM32F0L0_CRC +config STM32F0L0G0_CRC bool "CRC" default n -config STM32F0L0_CRYP +config STM32F0L0G0_CRYP bool "CRYP" default n - depends on STM32F0L0_HAVE_HASH + depends on STM32F0L0G0_HAVE_HASH -config STM32F0L0_DMA1 +config STM32F0L0G0_DMA1 bool "DMA1" default n select ARCH_DMA - select STM32F0L0_DMA + select STM32F0L0G0_DMA -config STM32F0L0_DMA2 +config STM32F0L0G0_DMA2 bool "DMA2" default n - depends on STM32F0L0_HAVE_DMA2 + depends on STM32F0L0G0_HAVE_DMA2 select ARCH_DMA - select STM32F0L0_DMA + select STM32F0L0G0_DMA -config STM32F0L0_DAC1 +config STM32F0L0G0_DAC1 bool "DAC1" default n - depends on STM32F0L0_HAVE_DAC1 - select STM32F0L0_DAC + depends on STM32F0L0G0_HAVE_DAC1 + select STM32F0L0G0_DAC -config STM32F0L0_FSMC +config STM32F0L0G0_FSMC bool "FSMC" default n - depends on STM32F0L0_HAVE_FSMC + depends on STM32F0L0G0_HAVE_FSMC -config STM32F0L0_HASH +config STM32F0L0G0_HASH bool "HASH" default n - depends on STM32F0L0_HAVE_HASH + depends on STM32F0L0G0_HAVE_HASH -config STM32F0L0_I2C1 +config STM32F0L0G0_I2C1 bool "I2C1" default n - select STM32F0L0_I2C + select STM32F0L0G0_I2C -config STM32F0L0_I2C2 +config STM32F0L0G0_I2C2 bool "I2C2" default n - depends on STM32F0L0_HAVE_I2C2 - select STM32F0L0_I2C + depends on STM32F0L0G0_HAVE_I2C2 + select STM32F0L0G0_I2C -config STM32F0L0_I2C3 +config STM32F0L0G0_I2C3 bool "I2C3" default n - depends on STM32F0L0_HAVE_I2C3 - select STM32F0L0_I2C + depends on STM32F0L0G0_HAVE_I2C3 + select STM32F0L0G0_I2C -config STM32F0L0_PWR +config STM32F0L0G0_PWR bool "PWR" default n -config STM32F0L0_RNG +config STM32F0L0G0_RNG bool "RNG" default n - depends on STM32F0L0_HAVE_RNG + depends on STM32F0L0G0_HAVE_RNG select ARCH_HAVE_RNG -config STM32F0L0_SDIO +config STM32F0L0G0_SDIO bool "SDIO" default n - depends on STM32F0L0_HAVE_SDIO + depends on STM32F0L0G0_HAVE_SDIO select ARCH_HAVE_SDIO select ARCH_HAVE_SDIOWAIT_WRCOMPLETE select ARCH_HAVE_SDIO_PREFLIGHT -config STM32F0L0_SPI1 +config STM32F0L0G0_SPI1 bool "SPI1" default n select SPI - select STM32F0L0_SPI + select STM32F0L0G0_SPI -config STM32F0L0_SPI2 +config STM32F0L0G0_SPI2 bool "SPI2" default n - depends on STM32F0L0_HAVE_SPI2 + depends on STM32F0L0G0_HAVE_SPI2 select SPI - select STM32F0L0_SPI + select STM32F0L0G0_SPI -config STM32F0L0_SPI3 +config STM32F0L0G0_SPI3 bool "SPI3" default n - depends on STM32F0L0_HAVE_SPI3 + depends on STM32F0L0G0_HAVE_SPI3 select SPI - select STM32F0L0_SPI + select STM32F0L0G0_SPI -config STM32F0L0_SPI4 +config STM32F0L0G0_SPI4 bool "SPI4" default n - depends on STM32F0L0_HAVE_SPI4 + depends on STM32F0L0G0_HAVE_SPI4 select SPI - select STM32F0L0_SPI + select STM32F0L0G0_SPI -config STM32F0L0_SPI5 +config STM32F0L0G0_SPI5 bool "SPI5" default n - depends on STM32F0L0_HAVE_SPI5 + depends on STM32F0L0G0_HAVE_SPI5 select SPI - select STM32F0L0_SPI + select STM32F0L0G0_SPI -config STM32F0L0_SPI6 +config STM32F0L0G0_SPI6 bool "SPI6" default n - depends on STM32F0L0_HAVE_SPI6 + depends on STM32F0L0G0_HAVE_SPI6 select SPI - select STM32F0L0_SPI + select STM32F0L0G0_SPI -config STM32F0L0_SYSCFG +config STM32F0L0G0_SYSCFG bool "SYSCFG" default y -config STM32F0L0_TIM1 +config STM32F0L0G0_TIM1 bool "TIM1" default n - depends on STM32F0L0_HAVE_TIM1 + depends on STM32F0L0G0_HAVE_TIM1 -config STM32F0L0_TIM2 +config STM32F0L0G0_TIM2 bool "TIM2" default n -config STM32F0L0_TIM3 +config STM32F0L0G0_TIM3 bool "TIM3" default n - depends on STM32F0L0_HAVE_TIM3 + depends on STM32F0L0G0_HAVE_TIM3 -config STM32F0L0_TIM6 +config STM32F0L0G0_TIM6 bool "TIM6" default n - depends on STM32F0L0_HAVE_TIM6 + depends on STM32F0L0G0_HAVE_TIM6 -config STM32F0L0_TIM7 +config STM32F0L0G0_TIM7 bool "TIM7" default n - depends on STM32F0L0_HAVE_TIM7 + depends on STM32F0L0G0_HAVE_TIM7 -config STM32F0L0_TIM14 +config STM32F0L0G0_TIM14 bool "TIM14" default n - depends on STM32F0L0_HAVE_TIM14 + depends on STM32F0L0G0_HAVE_TIM14 -config STM32F0L0_TIM15 +config STM32F0L0G0_TIM15 bool "TIM15" default n - depends on STM32F0L0_HAVE_TIM15 + depends on STM32F0L0G0_HAVE_TIM15 -config STM32F0L0_TIM16 +config STM32F0L0G0_TIM16 bool "TIM16" default n - depends on STM32F0L0_HAVE_TIM16 + depends on STM32F0L0G0_HAVE_TIM16 -config STM32F0L0_TIM17 +config STM32F0L0G0_TIM17 bool "TIM17" default n - depends on STM32F0L0_HAVE_TIM17 + depends on STM32F0L0G0_HAVE_TIM17 -config STM32F0L0_TSC +config STM32F0L0G0_TSC bool "TSC" default n - depends on STM32F0L0_HAVE_TSC + depends on STM32F0L0G0_HAVE_TSC -config STM32F0L0_USART1 +config STM32F0L0G0_USART1 bool "USART1" default n - select STM32F0L0_USART + select STM32F0L0G0_USART -config STM32F0L0_USART2 +config STM32F0L0G0_USART2 bool "USART2" default n - select STM32F0L0_USART + select STM32F0L0G0_USART -config STM32F0L0_USART3 +config STM32F0L0G0_USART3 bool "USART3" default n - depends on STM32F0L0_HAVE_USART3 - select STM32F0L0_USART + depends on STM32F0L0G0_HAVE_USART3 + select STM32F0L0G0_USART -config STM32F0L0_USART4 +config STM32F0L0G0_USART4 bool "USART4" default n - depends on STM32F0L0_HAVE_USART4 - select STM32F0L0_USART + depends on STM32F0L0G0_HAVE_USART4 + select STM32F0L0G0_USART -config STM32F0L0_USART5 +config STM32F0L0G0_USART5 bool "USART5" default n - depends on STM32F0L0_HAVE_USART5 - select STM32F0L0_USART + depends on STM32F0L0G0_HAVE_USART5 + select STM32F0L0G0_USART -config STM32F0L0_USART6 +config STM32F0L0G0_USART6 bool "USART6" default n - depends on STM32F0L0_HAVE_USART6 - select STM32F0L0_USART + depends on STM32F0L0G0_HAVE_USART6 + select STM32F0L0G0_USART -config STM32F0L0_USART7 +config STM32F0L0G0_USART7 bool "USART7" default n - depends on STM32F0L0_HAVE_USART7 - select STM32F0L0_USART + depends on STM32F0L0G0_HAVE_USART7 + select STM32F0L0G0_USART -config STM32F0L0_USART8 +config STM32F0L0G0_USART8 bool "USART8" default n - depends on STM32F0L0_HAVE_USART8 - select STM32F0L0_USART + depends on STM32F0L0G0_HAVE_USART8 + select STM32F0L0G0_USART -config STM32F0L0_USB +config STM32F0L0G0_USB bool "USB Device" default n - depends on STM32F0L0_HAVE_USBDEV + depends on STM32F0L0G0_HAVE_USBDEV select USBDEV -config STM32F0L0_LCD +config STM32F0L0G0_LCD bool "Segment LCD" default n - depends on STM32F0L0_HAVE_LCD + depends on STM32F0L0G0_HAVE_LCD select USBDEV -config STM32F0L0_IWDG +config STM32F0L0G0_IWDG bool "IWDG" default n select WATCHDOG -config STM32F0L0_WWDG +config STM32F0L0G0_WWDG bool "WWDG" default n select WATCHDOG endmenu -config STM32F0L0_COMP +config STM32F0L0G0_COMP bool -config STM32F0L0_ADC +config STM32F0L0G0_ADC bool -config STM32F0L0_DAC +config STM32F0L0G0_DAC bool -config STM32F0L0_DMA +config STM32F0L0G0_DMA bool -config STM32F0L0_SPI +config STM32F0L0G0_SPI bool -config STM32F0L0_I2C +config STM32F0L0G0_I2C bool -config STM32F0L0_CAN +config STM32F0L0G0_CAN bool -config STM32F0L0_USART +config STM32F0L0G0_USART bool -config STM32F0L0_SERIALDRIVER +config STM32F0L0G0_SERIALDRIVER bool -config STM32F0L0_1WIREDRIVER +config STM32F0L0G0_1WIREDRIVER bool menu "U[S]ART Configuration" - depends on STM32F0L0_USART + depends on STM32F0L0G0_USART comment "U[S]ART Device Configuration" choice prompt "USART1 Driver Configuration" - default STM32F0L0_USART1_SERIALDRIVER - depends on STM32F0L0_USART1 + default STM32F0L0G0_USART1_SERIALDRIVER + depends on STM32F0L0G0_USART1 -config STM32F0L0_USART1_SERIALDRIVER +config STM32F0L0G0_USART1_SERIALDRIVER bool "Standard serial driver" select USART1_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0_SERIALDRIVER + select STM32F0L0G0_SERIALDRIVER -config STM32F0L0_USART1_1WIREDRIVER +config STM32F0L0G0_USART1_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0_1WIREDRIVER + select STM32F0L0G0_1WIREDRIVER endchoice # USART1 Driver Configuration -if STM32F0L0_USART1_SERIALDRIVER +if STM32F0L0G0_USART1_SERIALDRIVER config USART1_RXFIFO_THRES int "USART1 Rx FIFO Threshold" default 3 range 0 5 - depends on STM32F0L0_HAVE_IP_USART_V2 + depends on STM32F0L0G0_HAVE_IP_USART_V2 ---help--- Select the Rx FIFO threshold: @@ -1486,32 +1486,32 @@ config USART1_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0_USART1_SERIALDRIVER +endif # STM32F0L0G0_USART1_SERIALDRIVER choice prompt "USART2 Driver Configuration" - default STM32F0L0_USART2_SERIALDRIVER - depends on STM32F0L0_USART2 + default STM32F0L0G0_USART2_SERIALDRIVER + depends on STM32F0L0G0_USART2 -config STM32F0L0_USART2_SERIALDRIVER +config STM32F0L0G0_USART2_SERIALDRIVER bool "Standard serial driver" select USART2_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0_SERIALDRIVER + select STM32F0L0G0_SERIALDRIVER -config STM32F0L0_USART2_1WIREDRIVER +config STM32F0L0G0_USART2_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0_1WIREDRIVER + select STM32F0L0G0_1WIREDRIVER endchoice # USART2 Driver Configuration -if STM32F0L0_USART2_SERIALDRIVER +if STM32F0L0G0_USART2_SERIALDRIVER config USART2_RXFIFO_THRES int "USART2 Rx FIFO Threshold" default 3 range 0 5 - depends on STM32F0L0_HAVE_IP_USART_V2 + depends on STM32F0L0G0_HAVE_IP_USART_V2 ---help--- Select the Rx FIFO threshold: @@ -1542,26 +1542,26 @@ config USART2_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0_USART2_SERIALDRIVER +endif # STM32F0L0G0_USART2_SERIALDRIVER choice prompt "USART3 Driver Configuration" - default STM32F0L0_USART3_SERIALDRIVER - depends on STM32F0L0_USART3 + default STM32F0L0G0_USART3_SERIALDRIVER + depends on STM32F0L0G0_USART3 -config STM32F0L0_USART3_SERIALDRIVER +config STM32F0L0G0_USART3_SERIALDRIVER bool "Standard serial driver" select USART3_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0_SERIALDRIVER + select STM32F0L0G0_SERIALDRIVER -config STM32F0L0_USART3_1WIREDRIVER +config STM32F0L0G0_USART3_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0_1WIREDRIVER + select STM32F0L0G0_1WIREDRIVER endchoice # USART3 Driver Configuration -if STM32F0L0_USART3_SERIALDRIVER +if STM32F0L0G0_USART3_SERIALDRIVER config USART3_RS485 bool "RS-485 on USART3" @@ -1579,26 +1579,26 @@ config USART3_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0_USART3_SERIALDRIVER +endif # STM32F0L0G0_USART3_SERIALDRIVER choice prompt "USART4 Driver Configuration" - default STM32F0L0_USART4_SERIALDRIVER - depends on STM32F0L0_USART4 + default STM32F0L0G0_USART4_SERIALDRIVER + depends on STM32F0L0G0_USART4 -config STM32F0L0_USART4_SERIALDRIVER +config STM32F0L0G0_USART4_SERIALDRIVER bool "Standard serial driver" select USART4_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0_SERIALDRIVER + select STM32F0L0G0_SERIALDRIVER -config STM32F0L0_USART4_1WIREDRIVER +config STM32F0L0G0_USART4_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0_1WIREDRIVER + select STM32F0L0G0_1WIREDRIVER endchoice # USART4 Driver Configuration -if STM32F0L0_USART4_SERIALDRIVER +if STM32F0L0G0_USART4_SERIALDRIVER config USART4_RS485 bool "RS-485 on USART4" @@ -1616,26 +1616,26 @@ config USART4_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART4. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0_USART4_SERIALDRIVER +endif # STM32F0L0G0_USART4_SERIALDRIVER choice prompt "USART5 Driver Configuration" - default STM32F0L0_USART5_SERIALDRIVER - depends on STM32F0L0_USART5 + default STM32F0L0G0_USART5_SERIALDRIVER + depends on STM32F0L0G0_USART5 -config STM32F0L0_USART5_SERIALDRIVER +config STM32F0L0G0_USART5_SERIALDRIVER bool "Standard serial driver" select USART5_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0_SERIALDRIVER + select STM32F0L0G0_SERIALDRIVER -config STM32F0L0_USART5_1WIREDRIVER +config STM32F0L0G0_USART5_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0_1WIREDRIVER + select STM32F0L0G0_1WIREDRIVER endchoice # USART5 Driver Configuration -if STM32F0L0_USART5_SERIALDRIVER +if STM32F0L0G0_USART5_SERIALDRIVER config USART5_RS485 bool "RS-485 on USART5" @@ -1653,27 +1653,27 @@ config USART5_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART5. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0_USART5_SERIALDRIVER +endif # STM32F0L0G0_USART5_SERIALDRIVER choice prompt "USART6 Driver Configuration" - default STM32F0L0_USART6_SERIALDRIVER - depends on STM32F0L0_USART6 + default STM32F0L0G0_USART6_SERIALDRIVER + depends on STM32F0L0G0_USART6 -config STM32F0L0_USART6_SERIALDRIVER +config STM32F0L0G0_USART6_SERIALDRIVER bool "Standard serial driver" select USART6_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0_SERIALDRIVER + select STM32F0L0G0_SERIALDRIVER -config STM32F0L0_USART6_1WIREDRIVER +config STM32F0L0G0_USART6_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0_1WIREDRIVER + select STM32F0L0G0_1WIREDRIVER endchoice # USART6 Driver Configuration -if STM32F0L0_USART6_SERIALDRIVER +if STM32F0L0G0_USART6_SERIALDRIVER config USART6_RS485 bool "RS-485 on USART6" @@ -1691,26 +1691,26 @@ config USART6_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0_USART6_SERIALDRIVER +endif # STM32F0L0G0_USART6_SERIALDRIVER choice prompt "USART7 Driver Configuration" - default STM32F0L0_USART7_SERIALDRIVER - depends on STM32F0L0_USART7 + default STM32F0L0G0_USART7_SERIALDRIVER + depends on STM32F0L0G0_USART7 -config STM32F0L0_USART7_SERIALDRIVER +config STM32F0L0G0_USART7_SERIALDRIVER bool "Standard serial driver" select USART7_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0_SERIALDRIVER + select STM32F0L0G0_SERIALDRIVER -config STM32F0L0_USART7_1WIREDRIVER +config STM32F0L0G0_USART7_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0_1WIREDRIVER + select STM32F0L0G0_1WIREDRIVER endchoice # USART7 Driver Configuration -if STM32F0L0_USART7_SERIALDRIVER +if STM32F0L0G0_USART7_SERIALDRIVER config USART7_RS485 bool "RS-485 on USART7" @@ -1728,26 +1728,26 @@ config USART7_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART7. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0_USART7_SERIALDRIVER +endif # STM32F0L0G0_USART7_SERIALDRIVER choice prompt "USART8 Driver Configuration" - default STM32F0L0_USART8_SERIALDRIVER - depends on STM32F0L0_USART8 + default STM32F0L0G0_USART8_SERIALDRIVER + depends on STM32F0L0G0_USART8 -config STM32F0L0_USART8_SERIALDRIVER +config STM32F0L0G0_USART8_SERIALDRIVER bool "Standard serial driver" select USART8_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0_SERIALDRIVER + select STM32F0L0G0_SERIALDRIVER -config STM32F0L0_USART8_1WIREDRIVER +config STM32F0L0G0_USART8_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0_1WIREDRIVER + select STM32F0L0G0_1WIREDRIVER endchoice # USART8 Driver Configuration -if STM32F0L0_USART8_SERIALDRIVER +if STM32F0L0G0_USART8_SERIALDRIVER config USART8_RS485 bool "RS-485 on USART8" @@ -1765,12 +1765,12 @@ config USART8_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART8. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0_USART8_SERIALDRIVER +endif # STM32F0L0G0_USART8_SERIALDRIVER menu "Serial Driver Configuration" - depends on STM32F0L0_SERIALDRIVER + depends on STM32F0L0G0_SERIALDRIVER -config STM32F0L0_SERIAL_DISABLE_REORDERING +config STM32F0L0G0_SERIAL_DISABLE_REORDERING bool "Disable reordering of ttySx devices." default n ---help--- @@ -1783,10 +1783,10 @@ config STM32F0L0_SERIAL_DISABLE_REORDERING want the side effect of having all serial port names change when just the console is moved from serial to USB. -config STM32F0L0_USART_SINGLEWIRE +config STM32F0L0G0_USART_SINGLEWIRE bool "Single Wire Support" default n - depends on STM32F0L0_USART + depends on STM32F0L0G0_USART ---help--- Enable single wire UART support. The option enables support for the TIOCSSINGLEWIRE ioctl in the STM32F0 serial driver. @@ -1795,7 +1795,7 @@ endmenu # Serial Driver Configuration if PM -config STM32F0L0_PM_SERIAL_ACTIVITY +config STM32F0L0G0_PM_SERIAL_ACTIVITY int "PM serial activity" default 10 ---help--- @@ -1807,53 +1807,53 @@ endif endmenu menu "ADC Configuration" - depends on STM32F0L0_ADC + depends on STM32F0L0G0_ADC -config STM32F0L0_ADC1_RESOLUTION +config STM32F0L0G0_ADC1_RESOLUTION int "ADC1 resolution" - depends on STM32F0L0_ADC1 + depends on STM32F0L0G0_ADC1 default 0 range 0 3 ---help--- ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit -config STM32F0L0_ADC_NO_STARTUP_CONV +config STM32F0L0G0_ADC_NO_STARTUP_CONV bool "Do not start conversion when opening ADC device" default n ---help--- Do not start conversion when opening ADC device. -config STM32F0L0_ADC_NOIRQ +config STM32F0L0G0_ADC_NOIRQ bool "Do not use default ADC interrupts" default n ---help--- Do not use default ADC interrupts handlers. -config STM32F0L0_ADC_LL_OPS +config STM32F0L0G0_ADC_LL_OPS bool "ADC low-level operations" default n ---help--- Enable low-level ADC ops. -config STM32F0L0_ADC_CHANGE_SAMPLETIME +config STM32F0L0G0_ADC_CHANGE_SAMPLETIME bool "ADC sample time configuration" default n - depends on STM32F0L0_ADC_LL_OPS + depends on STM32F0L0G0_ADC_LL_OPS ---help--- Enable ADC sample time configuration (SMPRx registers). -config STM32F0L0_ADC1_DMA +config STM32F0L0G0_ADC1_DMA bool "ADC1 DMA" - depends on STM32F0L0_ADC1 && STM32F0L0_HAVE_ADC1_DMA + depends on STM32F0L0G0_ADC1 && STM32F0L0G0_HAVE_ADC1_DMA default n ---help--- If DMA is selected, then the ADC may be configured to support DMA transfer, which is necessary if multiple channels are read or if very high trigger frequencies are used. -config STM32F0L0_ADC1_DMA_CFG +config STM32F0L0G0_ADC1_DMA_CFG int "ADC1 DMA configuration" - depends on STM32F0L0_ADC1_DMA && !STM32F0L0_HAVE_IP_ADC_V1_BASIC + depends on STM32F0L0G0_ADC1_DMA && !STM32F0L0G0_HAVE_IP_ADC_V1_BASIC range 0 1 default 0 ---help--- @@ -1862,9 +1862,9 @@ config STM32F0L0_ADC1_DMA_CFG endmenu menu "SPI Configuration" - depends on STM32F0L0_SPI + depends on STM32F0L0G0_SPI -config STM32F0L0_SPI_INTERRUPTS +config STM32F0L0G0_SPI_INTERRUPTS bool "Interrupt driver SPI" default n ---help--- @@ -1872,59 +1872,59 @@ config STM32F0L0_SPI_INTERRUPTS poll-waiting is recommended if the interrupt rate would be to high in the interrupt driven case. -config STM32F0L0_SPI_DMA +config STM32F0L0G0_SPI_DMA bool "SPI DMA" default n ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32F0L0_SPI_INTERRUPT. + Use DMA to improve SPI transfer performance. Cannot be used with STM32F0L0G0_SPI_INTERRUPT. -config STM32F0L0_SPI1_DMA +config STM32F0L0G0_SPI1_DMA bool "SPI1 DMA" default n - depends on STM32F0L0_SPI1 && STM32F0L0_SPI_DMA + depends on STM32F0L0G0_SPI1 && STM32F0L0G0_SPI_DMA ---help--- Use DMA to improve SPI1 transfer performance. -config STM32F0L0_SPI2_DMA +config STM32F0L0G0_SPI2_DMA bool "SPI2 DMA" default n - depends on STM32F0L0_SPI2 && STM32F0L0_SPI_DMA + depends on STM32F0L0G0_SPI2 && STM32F0L0G0_SPI_DMA ---help--- Use DMA to improve SPI2 transfer performance. endmenu # SPI Configuration menu "I2C Configuration" - depends on STM32F0L0_I2C + depends on STM32F0L0G0_I2C -config STM32F0L0_I2C_DYNTIMEO +config STM32F0L0G0_I2C_DYNTIMEO bool "Use dynamic timeouts" default n - depends on STM32F0L0_I2C + depends on STM32F0L0G0_I2C -config STM32F0L0_I2C_DYNTIMEO_USECPERBYTE +config STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE int "Timeout Microseconds per Byte" default 500 - depends on STM32F0L0_I2C_DYNTIMEO + depends on STM32F0L0G0_I2C_DYNTIMEO -config STM32F0L0_I2C_DYNTIMEO_STARTSTOP +config STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP int "Timeout for Start/Stop (Milliseconds)" default 1000 - depends on STM32F0L0_I2C_DYNTIMEO + depends on STM32F0L0G0_I2C_DYNTIMEO -config STM32F0L0_I2CTIMEOSEC +config STM32F0L0G0_I2CTIMEOSEC int "Timeout seconds" default 0 - depends on STM32F0L0_I2C + depends on STM32F0L0G0_I2C -config STM32F0L0_I2CTIMEOMS +config STM32F0L0G0_I2CTIMEOMS int "Timeout Milliseconds" default 500 - depends on STM32F0L0_I2C && !STM32F0L0_I2C_DYNTIMEO + depends on STM32F0L0G0_I2C && !STM32F0L0G0_I2C_DYNTIMEO -config STM32F0L0_I2CTIMEOTICKS +config STM32F0L0G0_I2CTIMEOTICKS int "Timeout for Done and Stop (ticks)" default 500 - depends on STM32F0L0_I2C && !STM32F0L0_I2C_DYNTIMEO + depends on STM32F0L0G0_I2C && !STM32F0L0G0_I2C_DYNTIMEO endmenu #I2C Configuration diff --git a/arch/arm/src/stm32f0l0/Make.defs b/arch/arm/src/stm32f0l0g0/Make.defs similarity index 89% rename from arch/arm/src/stm32f0l0/Make.defs rename to arch/arm/src/stm32f0l0g0/Make.defs index 06069a634f..7047383c62 100644 --- a/arch/arm/src/stm32f0l0/Make.defs +++ b/arch/arm/src/stm32f0l0g0/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# arch/arm/src/stm32f0l0/Make.defs +# arch/arm/src/stm32f0l0g0/Make.defs # # Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. # Author: Gregory Nutt @@ -66,11 +66,11 @@ CHIP_ASRCS = CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c CHIP_CSRCS += stm32_lse.c stm32_lowputc.c stm32_serial.c stm32_rcc.c -ifeq ($(CONFIG_STM32F0L0_DMA),y) +ifeq ($(CONFIG_STM32F0L0G0_DMA),y) CHIP_CSRCS += stm32_dma_v1.c endif -ifeq ($(CONFIG_STM32F0L0_PWR),y) +ifeq ($(CONFIG_STM32F0L0G0_PWR),y) CHIP_CSRCS += stm32_pwr.c endif @@ -86,7 +86,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c endif -ifeq ($(CONFIG_STM32F0L0_GPIOIRQ),y) +ifeq ($(CONFIG_STM32F0L0G0_GPIOIRQ),y) CHIP_CSRCS += stm32_gpioint.c endif @@ -94,34 +94,34 @@ ifeq ($(CONFIG_ARCH_IRQPRIO),y) CHIP_CSRCS += stm32_irqprio.c endif -ifeq ($(CONFIG_STM32F0L0_HAVE_HSI48),y) +ifeq ($(CONFIG_STM32F0L0G0_HAVE_HSI48),y) CHIP_CSRCS += stm32_hsi48.c endif -ifeq ($(CONFIG_STM32F0L0_USB),y) +ifeq ($(CONFIG_STM32F0L0G0_USB),y) CHIP_CSRCS += stm32_usbdev.c endif -ifeq ($(CONFIG_STM32F0L0_I2C),y) +ifeq ($(CONFIG_STM32F0L0G0_I2C),y) CHIP_CSRCS += stm32_i2c.c endif -ifeq ($(CONFIG_STM32F0L0_SPI),y) +ifeq ($(CONFIG_STM32F0L0G0_SPI),y) CHIP_CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32F0L0_PWM),y) +ifeq ($(CONFIG_STM32F0L0G0_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32F0L0_ADC),y) +ifeq ($(CONFIG_STM32F0L0G0_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32F0L0_AES),y) +ifeq ($(CONFIG_STM32F0L0G0_AES),y) CHIP_CSRCS += stm32_aes.c endif -ifeq ($(CONFIG_STM32F0L0_RNG),y) +ifeq ($(CONFIG_STM32F0L0G0_RNG),y) CHIP_CSRCS += stm32_rng.c endif diff --git a/arch/arm/src/stm32f0l0/chip.h b/arch/arm/src/stm32f0l0g0/chip.h similarity index 92% rename from arch/arm/src/stm32f0l0/chip.h rename to arch/arm/src/stm32f0l0g0/chip.h index dae04640ce..a8382541a7 100644 --- a/arch/arm/src/stm32f0l0/chip.h +++ b/arch/arm/src/stm32f0l0g0/chip.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/chip.h + * arch/arm/src/stm32f0l0g0/chip.h * * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_H -#define __ARCH_ARM_SRC_STM32F0L0_CHIP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H +#define __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H /************************************************************************************ * Included Files @@ -46,7 +46,7 @@ /* Include the chip capabilities file */ -#include +#include #define ARMV6M_PERIPHERAL_INTERRUPTS 32 @@ -56,4 +56,4 @@ #include "hardware/stm32_memorymap.h" -#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_adc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h similarity index 97% rename from arch/arm/src/stm32f0l0/hardware/stm32_adc.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h index 8dd587ab33..240fc528ad 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_adc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h @@ -1,5 +1,5 @@ /******************************************************************************** - * arch/arm/src/stm32f0l0/hardware/stm32_adc.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ********************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H /******************************************************************************** * Included Files @@ -62,7 +62,7 @@ /* Support for ADC clock prescaler */ -#if defined(CONFIG_STM32F0L0_STM32L0) || defined(CONFIG_STM32F0L0_STM32G0) +#if defined(CONFIG_STM32F0L0G0_STM32L0) || defined(CONFIG_STM32F0L0G0_STM32G0) # define HAVE_ADC_PRE #else # undef HAVE_ADC_PRE @@ -70,7 +70,7 @@ /* Support for LCD voltage */ -#ifdef CONFIG_STM32F0L0_HAVE_LCD +#ifdef CONFIG_STM32F0L0G0_HAVE_LCD # define HAVE_ADC_VLCD #else # undef HAVE_ADC_VLCD @@ -78,7 +78,7 @@ /* Supprot for Low frequency mode */ -#ifdef CONFIG_STM32F0L0_ENERGYLITE +#ifdef CONFIG_STM32F0L0G0_ENERGYLITE # define HAVE_ADC_LFM #else # undef HAVE_ADC_LFM @@ -268,4 +268,4 @@ # define ADC_CCR_LFMEN (1 << 25) /* Bit 25: Low Frequency Mode enable */ #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_aes.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h similarity index 96% rename from arch/arm/src/stm32f0l0/hardware/stm32_aes.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h index 2d583056bd..fa60d0bd29 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_aes.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h @@ -1,5 +1,5 @@ /******************************************************************************************** - * arch/arm/src/stm32f0l0/hardware/stm32_aes.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h * * Copyright (C) 2015 Haltian Ltd. All rights reserved. * Author: Juha Niskanen @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_AES_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_AES_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H /******************************************************************************************** * Included Files @@ -111,4 +111,4 @@ #define AES_SR_RDERR (1 << 1) /* Read Error Flag */ #define AES_SR_WRERR (1 << 2) /* Write Error Flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_AES_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_can.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h similarity index 99% rename from arch/arm/src/stm32f0l0/hardware/stm32_can.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_can.h index 7e82c3e15b..92cec1782f 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_can.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_can.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_can.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CAN_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CAN_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H /************************************************************************************ * Included Files @@ -466,4 +466,4 @@ #define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ #define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CAN_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_comp.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h similarity index 97% rename from arch/arm/src/stm32f0l0/hardware/stm32_comp.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h index b59648d1f3..380f0cde55 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_comp.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_comp.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_COMP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H /************************************************************************************ * Included Files @@ -135,4 +135,4 @@ #define COMP_CSR_COMP2OUT (1 << 14) /* Bit 14: Comparator 1 output */ #define COMP_CSR_COMP2LOCK (1 << 15) /* Bit 15: Comparator 1 lock */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_COMP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_crc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h similarity index 95% rename from arch/arm/src/stm32f0l0/hardware/stm32_crc.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h index d1a81841b4..4e360dc707 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_crc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_crc.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRC_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H /************************************************************************************ * Included Files @@ -87,4 +87,4 @@ # define CRC_CR_REVIN_WORD (3 << CRC_CR_REVIN_SHIFT) /* 11: reversal done by word */ #define CRC_CR_REVOUT (1 << 7) /* This bit controls the reversal of the bit order of the output data */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_crs.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h similarity index 96% rename from arch/arm/src/stm32f0l0/hardware/stm32_crs.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h index 8df33f4d53..1699d6b5cb 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_crs.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_crs.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRS_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRS_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H /************************************************************************************ * Pre-processor Definitions @@ -112,4 +112,4 @@ #define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */ #define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRS_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_dac.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h similarity index 98% rename from arch/arm/src/stm32f0l0/hardware/stm32_dac.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h index cbf23506bb..74e1bbfc72 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_dac.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_dac.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DAC_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DAC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H /************************************************************************************ * Included Files @@ -215,4 +215,4 @@ #define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ #define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DAC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h similarity index 99% rename from arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h index 1ee0fa0ad0..46a921637d 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMA_V1_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMA_V1_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H /************************************************************************************ * Pre-processor Definitions @@ -550,4 +550,4 @@ # error "Unknown DMA channel assignments" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMA_V1_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_dmamux.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h similarity index 96% rename from arch/arm/src/stm32f0l0/hardware/stm32_dmamux.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h index 7b89c73450..1294463efe 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_dmamux.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_dmamux.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMAMUX_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMAMUX_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H /************************************************************************************ * Included Files @@ -153,10 +153,10 @@ /* Import DMAMUX map */ -#if defined(CONFIG_STM32F0L0_STM32G0) +#if defined(CONFIG_STM32F0L0G0_STM32G0) # include "chip/stm32g0_dmamux.h" #else # error "Unsupported STM32 M0 sub family" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_exti.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h similarity index 91% rename from arch/arm/src/stm32f0l0/hardware/stm32_exti.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h index 489fe42783..2baf8cec34 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_exti.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_exti.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h * * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H /************************************************************************************ * Included Files @@ -54,4 +54,4 @@ # error "Unrecognized STM32 M0 EXTI" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_flash.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h similarity index 90% rename from arch/arm/src/stm32f0l0/hardware/stm32_flash.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h index f88ffcb00b..652308369a 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_flash.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_flash.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h * * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H /************************************************************************************ * Included Files @@ -53,4 +53,4 @@ # error "Unsupported STM32 M0 FLASH" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_gpio.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h similarity index 98% rename from arch/arm/src/stm32f0l0/hardware/stm32_gpio.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h index 53a16de083..a5906407e4 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_gpio.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_gpio.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H /************************************************************************************ * Pre-processor Definitions @@ -355,4 +355,4 @@ #define GPIO_BRR(n) (1 << (n)) -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_i2c.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h similarity index 98% rename from arch/arm/src/stm32f0l0/hardware/stm32_i2c.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h index e5f2c1a838..1f0bf66e27 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_i2c.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_I2C_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H /************************************************************************************ * Pre-processor Definitions @@ -235,4 +235,4 @@ #define I2C_TXDR_MASK (0xff) -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_I2C_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h similarity index 86% rename from arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h index fdac75815b..ca15936ce2 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h * * Copyright (C) 2017, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H /************************************************************************************ * Included Files @@ -44,8 +44,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0L0_STM32F05X) || defined(CONFIG_STM32F0L0_STM32F07X) || \ - defined(CONFIG_STM32F0L0_STM32F09X) +#if defined(CONFIG_STM32F0L0G0_STM32F05X) || defined(CONFIG_STM32F0L0G0_STM32F07X) || \ + defined(CONFIG_STM32F0L0G0_STM32F09X) # include "hardware/stm32f05xf07xf09x_memorymap.h" #elif defined(CONFIG_ARCH_CHIP_STM32L0) # include "hardware/stm32l0_memorymap.h" @@ -55,4 +55,4 @@ # error "Unsupported STM32 M0 memory map" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h similarity index 86% rename from arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h index cfc26f0081..63270d7cbb 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H /************************************************************************************ * Included Files @@ -43,11 +43,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0L0_STM32F05X) +#if defined(CONFIG_STM32F0L0G0_STM32F05X) # include "hardware/stm32f05x_pinmap.h" -#elif defined(CONFIG_STM32F0L0_STM32F07X) +#elif defined(CONFIG_STM32F0L0G0_STM32F07X) # include "hardware/stm32f07x_pinmap.h" -#elif defined(CONFIG_STM32F0L0_STM32F09X) +#elif defined(CONFIG_STM32F0L0G0_STM32F09X) # include "hardware/stm32f09x_pinmap.h" #elif defined(CONFIG_ARCH_CHIP_STM32L0) # include "hardware/stm32l0_pinmap.h" @@ -57,4 +57,4 @@ # error "Unsupported STM32 M0 pin map" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_pwr.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h similarity index 91% rename from arch/arm/src/stm32f0l0/hardware/stm32_pwr.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h index 05835f431c..3cd05ce057 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_pwr.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h * * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H /************************************************************************************ * Included Files @@ -54,5 +54,5 @@ # error "Unsupported STM32 M0 PWR" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_rcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h similarity index 91% rename from arch/arm/src/stm32f0l0/hardware/stm32_rcc.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h index 69a1bfc6f7..df37deec4d 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_rcc.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h * * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H /************************************************************************************ * Included Files @@ -54,4 +54,4 @@ # error "Unsupported STM32 M0 RCC" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_rng.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h similarity index 94% rename from arch/arm/src/stm32f0l0/hardware/stm32_rng.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h index dc93252637..c2caa80bf4 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_rng.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_rng.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h * * Copyright (C) 2012 Max Holtzberg. All rights reserved. * Author: Max Holtzberg @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RNG_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RNG_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H /************************************************************************************ * Included Files @@ -75,4 +75,4 @@ #define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ #define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RNG_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h similarity index 98% rename from arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h index c5eb492a64..014da6be5e 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RTCC_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RTCC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H /************************************************************************************ * Pre-processor Definitions @@ -321,4 +321,4 @@ #define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */ #define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RTCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_spi.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h similarity index 98% rename from arch/arm/src/stm32f0l0/hardware/stm32_spi.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h index 651a10567f..3328bd6e9d 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_spi.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_spi.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SPI_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H /************************************************************************************ * Included Files @@ -45,9 +45,9 @@ /* Select STM32 SPI IP core */ -#if defined(CONFIG_STM32F0L0_STM32F0) +#if defined(CONFIG_STM32F0L0G0_STM32F0) # define HAVE_IP_SPI_V2 -#elif defined(CONFIG_STM32F0L0_STM32L0) +#elif defined(CONFIG_STM32F0L0G0_STM32L0) # define HAVE_IP_SPI_V1 #else # error Unsupported family @@ -269,4 +269,4 @@ #define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ #define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h similarity index 91% rename from arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h index da971d0300..8fded4c195 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************************************** - * arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h * * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ****************************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H /**************************************************************************************************** * Included Files @@ -54,4 +54,4 @@ # error "Unsupported STM32 M0 SYSCFG" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_tim.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h similarity index 91% rename from arch/arm/src/stm32f0l0/hardware/stm32_tim.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h index 00e8171cee..11e684630a 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_tim.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h @@ -1,5 +1,5 @@ /**************************************************************************************************** - * arch/arm/src/stm32f0l0/hardware/stm32_tim.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ****************************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H /**************************************************************************************************** * Pre-processor Definitions @@ -49,4 +49,4 @@ /* Register Bitfield Definitions ********************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_uart.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h similarity index 87% rename from arch/arm/src/stm32f0l0/hardware/stm32_uart.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h index 420c40bd6d..390f0adcbe 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_uart.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_uart.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h * * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H /************************************************************************************ * Included Files @@ -44,12 +44,12 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0L0_HAVE_IP_USART_V1) +#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1) # include "hardware/stm32_uart_v1.h" -#elif defined(CONFIG_STM32F0L0_HAVE_IP_USART_V2) +#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2) # include "hardware/stm32_uart_v2.h" #else # error "Unsupported STM32 M0 USART" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_uart_v1.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h similarity index 98% rename from arch/arm/src/stm32f0l0/hardware/stm32_uart_v1.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h index 4a5f7a02c0..839a3f1c15 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_uart_v1.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_uart_v1.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h * * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_UART_V1_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_UART_V1_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V1_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V1_H /************************************************************************************ * Included Files @@ -313,4 +313,4 @@ #define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */ #define USART_TDR_MASK (0xff << USART_TDR_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_V1_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_uart_v2.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h similarity index 98% rename from arch/arm/src/stm32f0l0/hardware/stm32_uart_v2.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h index e956deb327..9529afcec7 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_uart_v2.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_uart_v2.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_UART_V2_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_UART_V2_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V2_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V2_H /************************************************************************************ * Included Files @@ -360,4 +360,4 @@ # define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ # define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_V2_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h similarity index 98% rename from arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h index f0a06bb441..55bc7cc4a9 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_USBDEV_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H /************************************************************************************ * Included Files @@ -43,7 +43,7 @@ #include #include -#ifdef CONFIG_STM32F0L0_HAVE_USBDEV +#ifdef CONFIG_STM32F0L0G0_HAVE_USBDEV /************************************************************************************ * Pre-processor Definitions @@ -260,5 +260,5 @@ #define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */ #define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) -#endif /* CONFIG_STM32F0L0_HAVE_USBDEV */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_USBDEV_H */ +#endif /* CONFIG_STM32F0L0G0_HAVE_USBDEV */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_wdt.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h similarity index 96% rename from arch/arm/src/stm32f0l0/hardware/stm32_wdt.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h index dc6ebef315..0f122ad223 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_wdt.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_wdt.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_WDG_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H /************************************************************************************ * Included Files @@ -139,4 +139,4 @@ #define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_WDG_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h similarity index 96% rename from arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h index 05883195c5..a1b7b9cfab 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h + * arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F05X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F05X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H /************************************************************************************ * Included Files @@ -133,4 +133,4 @@ #define GPIO_I2C2_SCL (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN10) #define GPIO_I2C2_SDA (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN11) -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F05X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h similarity index 97% rename from arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h index 841097b97d..26b0f8e750 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h + * arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H /************************************************************************************ * Pre-processor Definitions @@ -154,4 +154,4 @@ #define STM32_SCS_BASE 0xe000e000 #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h similarity index 99% rename from arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h index 86dfff58ed..d25a4992cd 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h + * arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F07X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F07X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H /************************************************************************************ * Included Files @@ -397,4 +397,4 @@ #define GPIO_USB_NOE (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN13) -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F07X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h similarity index 99% rename from arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h index a136099cf3..3c1c149aa9 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h + * arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F09X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F09X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H /************************************************************************************ * Included Files @@ -427,4 +427,4 @@ #define GPIO_USART8_RX_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN13) #define GPIO_USART8_CK_RST (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN14) -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F09X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f0_exti.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h similarity index 96% rename from arch/arm/src/stm32f0l0/hardware/stm32f0_exti.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h index 1597710463..cbd8dd8593 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32f0_exti.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_exti.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h * * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H /************************************************************************************ * Included Files @@ -128,4 +128,4 @@ #define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ #define EXTI_PR_MASK STM32_EXTI_MASK -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f0_flash.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h similarity index 95% rename from arch/arm/src/stm32f0l0/hardware/stm32f0_flash.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h index 38bed16eb3..6e3534693a 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32f0_flash.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32f0_flash.h + * arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H /************************************************************************************ * Included Files @@ -105,4 +105,4 @@ #define FLASH_OBR_ /* To be provided */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f0_pwr.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h similarity index 95% rename from arch/arm/src/stm32f0l0/hardware/stm32f0_pwr.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h index d28979805a..17eda3ccbd 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32f0_pwr.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32f0_pwr.h + * arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h * * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H /************************************************************************************ * Included Files @@ -97,4 +97,4 @@ #define PWR_CSR_EWUP7 (1 << 14) /* Bit 14: Enable WKUP7 pin */ #define PWR_CSR_EWUP8 (1 << 15) /* Bit 15: Enable WKUP8 pin */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h index ea9dce5bc4..35df2a34c1 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h + * arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H /************************************************************************************ * Pre-processor Definitions @@ -393,4 +393,4 @@ #define RCC_CR2_HSI48CAL_SHIFT (24) /* Bits 24-31: HSI48 factory clock calibration */ #define RCC_CR2_HSI48CAL_MASK (0xff << RCC_CR2_HSI48CAL_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f0_syscfg.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h similarity index 99% rename from arch/arm/src/stm32f0l0/hardware/stm32f0_syscfg.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h index a554d053ec..a3314f6d12 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32f0_syscfg.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************************************** - * arch/arm/src/stm32f0l0/hardware/stm32f0_syscfg.h + * arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h * * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ****************************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H /**************************************************************************************************** * Included Files @@ -388,4 +388,4 @@ #define SYSCFG_ITLINE30_CEC (1 << 0) /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */ #define SYSCFG_ITLINE30_CAN (1 << 1) /* Bit 1: CAN interrupt request pending */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32g0_dmamux.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h similarity index 92% rename from arch/arm/src/stm32f0l0/hardware/stm32g0_dmamux.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h index a4c0aa68bc..60d1019c81 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32g0_dmamux.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32g0_dmamux.h + * arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_DMAMUX_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_DMAMUX_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H /************************************************************************************ * Included Files @@ -71,4 +71,4 @@ /* TODO: ... */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32g0_exti.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h similarity index 95% rename from arch/arm/src/stm32f0l0/hardware/stm32g0_exti.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h index ad7ac9e64c..7031badc2c 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32g0_exti.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32g0_exti.h + * arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H /************************************************************************************ * Included Files @@ -100,4 +100,4 @@ /* TODO */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32g0_flash.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h similarity index 95% rename from arch/arm/src/stm32f0l0/hardware/stm32g0_flash.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h index 328bb48267..c01bab4149 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32g0_flash.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32g0_flash.h + * arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H /************************************************************************************ * Included Files @@ -104,4 +104,4 @@ /* TODO */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32g0_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h similarity index 97% rename from arch/arm/src/stm32f0l0/hardware/stm32g0_memorymap.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h index e621356459..cea5c70f79 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32g0_memorymap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32g0_memorymap.h + * arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32G0_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32G0_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32G0_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32G0_MEMORYMAP_H /************************************************************************************ * Pre-processor Definitions @@ -137,4 +137,4 @@ #define STM32_SCS_BASE 0xe000e000 #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32G0_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32G0_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32g0_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h similarity index 95% rename from arch/arm/src/stm32f0l0/hardware/stm32g0_pinmap.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h index 6f0121a90c..d482b3b95e 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32g0_pinmap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32g0_pinmap.h + * arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H /************************************************************************************ * Included Files @@ -119,4 +119,4 @@ /* TODO: CEC */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32g0_pwr.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h similarity index 97% rename from arch/arm/src/stm32f0l0/hardware/stm32g0_pwr.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h index c172bc2d3f..ad8acfce5a 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32g0_pwr.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32g0_pwr.h + * arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H /************************************************************************************ * Included Files @@ -183,4 +183,4 @@ #define PWR_SCR_CWUF5 (1 << 4) /* Bit 4: Clear wakeup flag 5 */ #define PWR_SCR_CSBF (1 << 8) /* Bit 8: Clear standby flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32g0_rcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0/hardware/stm32g0_rcc.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h index 9b2b15756c..d86139325a 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32g0_rcc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32g0_rcc.h + * arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H /************************************************************************************ * Pre-processor Definitions @@ -359,4 +359,4 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32g0_syscfg.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h similarity index 98% rename from arch/arm/src/stm32f0l0/hardware/stm32g0_syscfg.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h index 610c55010d..a78bd7d303 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32g0_syscfg.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************************************** - * arch/arm/src/stm32f0l0/hardware/stm32g0_syscfg.h + * arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -33,8 +33,8 @@ * ****************************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H /**************************************************************************************************** * Included Files @@ -313,4 +313,4 @@ #define SYSCFG_ITLINE30_RNG (1 << 0) /* Bit 0: RNG interrupt request pending */ #define SYSCFG_ITLINE30_AES (1 << 1) /* Bit 1: AES interrupt request pending */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_exti.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h similarity index 96% rename from arch/arm/src/stm32f0l0/hardware/stm32l0_exti.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h index 8b2e3130bd..c810affae1 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32l0_exti.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32_exti.h + * arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H /************************************************************************************ * Included Files @@ -126,4 +126,4 @@ #define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ #define EXTI_PR_MASK STM32_EXTI_MASK -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_flash.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h similarity index 96% rename from arch/arm/src/stm32f0l0/hardware/stm32l0_flash.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h index d987124ede..0ce7b63c00 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32l0_flash.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32l0_flash.h + * arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H /************************************************************************************ * Included Files @@ -114,4 +114,4 @@ #define FLASH_SR_OPTVERRUSR (1 << 12) /* Bit 12: Option UserValidity Error */ #define FLASH_SR_RDERR (1 << 13) /* Bit 13: Read protected error */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h index b401c40c9f..c38609e0c1 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h + * arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H /************************************************************************************ * Pre-processor Definitions @@ -127,4 +127,4 @@ #define STM32_GPIOE_BASE 0x50001000 /* 0x50001000-0x500013ff GPIO Port E */ #define STM32_GPIOH_BASE 0x50001c00 /* 0x50001c00-0x50001fff GPIO Port H */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h index d2d84f451f..2c90ebcae0 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h + * arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H /************************************************************************************ * Included Files @@ -339,4 +339,4 @@ /* TODO: LPUART */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h similarity index 95% rename from arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h index 672aebafee..b15936c315 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h + * arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H /************************************************************************************ * Included Files @@ -102,4 +102,4 @@ #define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ #define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h index 1cdd41a4f4..706a09756c 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h + * arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H /************************************************************************************ * Pre-processor Definitions @@ -551,4 +551,4 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_syscfg.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h similarity index 97% rename from arch/arm/src/stm32f0l0/hardware/stm32l0_syscfg.h rename to arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h index 60b4ff30c4..31898e76f9 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32l0_syscfg.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************************************** - * arch/arm/src/stm32f0l0/hardware/stm32l0_syscfg.h + * arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -33,8 +33,8 @@ * ****************************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H /**************************************************************************************************** * Included Files @@ -145,4 +145,4 @@ #define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 configuration */ #define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H */ diff --git a/arch/arm/src/stm32f0l0/stm32.h b/arch/arm/src/stm32f0l0g0/stm32.h similarity index 93% rename from arch/arm/src/stm32f0l0/stm32.h rename to arch/arm/src/stm32f0l0g0/stm32.h index f222df2555..13a0a2d666 100644 --- a/arch/arm/src/stm32f0l0/stm32.h +++ b/arch/arm/src/stm32f0l0g0/stm32.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/stm32.h + * arch/arm/src/stm32f0l0g0/stm32.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_H /************************************************************************************ * Included Files @@ -64,4 +64,4 @@ #include "stm32_lowputc.h" #include "stm32_adc.h" -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_adc.c b/arch/arm/src/stm32f0l0g0/stm32_adc.c similarity index 97% rename from arch/arm/src/stm32f0l0/stm32_adc.c rename to arch/arm/src/stm32f0l0g0/stm32_adc.c index c88237fbc5..2bcbe7bc51 100644 --- a/arch/arm/src/stm32f0l0/stm32_adc.c +++ b/arch/arm/src/stm32f0l0g0/stm32_adc.c @@ -67,13 +67,13 @@ /* STM32 ADC "lower-half" support must be enabled */ -#ifdef CONFIG_STM32F0L0_ADC +#ifdef CONFIG_STM32F0L0G0_ADC /* Some ADC peripheral must be enabled */ -#if defined(CONFIG_STM32F0L0_ADC1) +#if defined(CONFIG_STM32F0L0G0_ADC1) -#if !defined(CONFIG_STM32F0L0_STM32L0) +#if !defined(CONFIG_STM32F0L0G0_STM32L0) # error Only L0 supported for now #endif @@ -123,7 +123,7 @@ /* G0 support additional sample time selection 2 */ -#if defined(CONFIG_STM32F0L0_STM32G0) +#if defined(CONFIG_STM32F0L0G0_STM32G0) # define ADC_HAVE_SMPR_SMP2 #endif @@ -145,7 +145,7 @@ * NOTE: this value can be obtained from SMPRx register description (ST manual) */ -#if defined(CONFIG_STM32F0L0_STM32F0) || defined(CONFIG_STM32F0L0_STM32L0) +#if defined(CONFIG_STM32F0L0G0_STM32F0) || defined(CONFIG_STM32F0L0G0_STM32L0) # define ADC_CHANNELS_NUMBER 19 #else # error "Not supported" @@ -196,10 +196,10 @@ struct adccmn_data_s struct stm32_dev_s { -#ifdef CONFIG_STM32F0L0_ADC_LL_OPS +#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS FAR const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */ #endif -#if !defined(CONFIG_STM32F0L0_ADC_NOIRQ) | defined(ADC_HAVE_DMA) +#if !defined(CONFIG_STM32F0L0G0_ADC_NOIRQ) | defined(ADC_HAVE_DMA) FAR const struct adc_callback_s *cb; uint8_t irq; /* Interrupt generated by this ADC block */ #endif @@ -220,7 +220,7 @@ struct stm32_dev_s # endif bool hasdma; /* True: This channel supports DMA */ #endif -#ifdef CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME /* Sample time selection. These bits must be written only when ADON=0. * REVISIT: this takes too much space. We need only 3 bits per channel. */ @@ -295,10 +295,10 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ -#ifndef CONFIG_STM32F0L0_ADC_NOIRQ +#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ static int adc_interrupt(FAR struct adc_dev_s *dev); static int adc1_interrupt(int irq, FAR void *context, FAR void *arg); -#endif /* CONFIG_STM32F0L0_ADC_NOIRQ */ +#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */ /* ADC Driver Methods */ @@ -349,7 +349,7 @@ static int adc_extcfg_set(FAR struct adc_dev_s *dev, uint32_t extcfg); static void adc_dumpregs(FAR struct stm32_dev_s *priv); -#ifdef CONFIG_STM32F0L0_ADC_LL_OPS +#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS static void adc_llops_intack(FAR struct stm32_adc_dev_s *dev, uint32_t source); static void adc_llops_inten(FAR struct stm32_adc_dev_s *dev, uint32_t source); static void adc_llops_intdis(FAR struct stm32_adc_dev_s *dev, uint32_t source); @@ -360,7 +360,7 @@ static void adc_llops_reg_startconv(FAR struct stm32_adc_dev_s *dev, bool enable static int adc_llops_regbufregister(FAR struct stm32_adc_dev_s *dev, uint16_t *buffer, uint8_t len); # endif -# ifdef CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME +# ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME static void adc_sampletime_set(FAR struct stm32_adc_dev_s *dev, FAR struct adc_sample_time_s *time_samples); static void adc_sampletime_write(FAR struct stm32_adc_dev_s *dev); @@ -386,7 +386,7 @@ static const struct adc_ops_s g_adcops = /* Publicly visible ADC lower-half operations */ -#ifdef CONFIG_STM32F0L0_ADC_LL_OPS +#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS static const struct stm32_adc_ops_s g_adc_llops = { .int_ack = adc_llops_intack, @@ -398,7 +398,7 @@ static const struct stm32_adc_ops_s g_adc_llops = # ifdef ADC_HAVE_DMA .regbuf_reg = adc_llops_regbufregister, # endif -# ifdef CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME +# ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME .stime_set = adc_sampletime_set, .stime_write = adc_sampletime_write, # endif @@ -408,37 +408,37 @@ static const struct stm32_adc_ops_s g_adc_llops = /* ADC1 state */ -#ifdef CONFIG_STM32F0L0_ADC1 +#ifdef CONFIG_STM32F0L0G0_ADC1 static struct stm32_dev_s g_adcpriv1 = { -#ifdef CONFIG_STM32F0L0_ADC_LL_OPS +#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F0L0_ADC_NOIRQ +#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc1_interrupt, -#endif /* CONFIG_STM32F0L0_ADC_NOIRQ */ +#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */ #ifdef HAVE_ADC_CMN_DATA .cmn = &ADC1CMN_DATA, #endif .intf = 1, #ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32F0L0_ADC1_RESOLUTION, + .resolution = CONFIG_STM32F0L0G0_ADC1_RESOLUTION, #endif .base = STM32_ADC1_BASE, #ifdef ADC1_HAVE_EXTCFG .extcfg = ADC1_EXTCFG_VALUE, #endif #ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32F0L0_ADC1_TIMTRIG, + .trigger = CONFIG_STM32F0L0G0_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F0L0_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY, #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, # ifdef ADC_HAVE_DMACFG - .dmacfg = CONFIG_STM32F0L0_ADC1_DMA_CFG, + .dmacfg = CONFIG_STM32F0L0G0_ADC1_DMA_CFG, # endif .hasdma = true, #endif @@ -886,7 +886,7 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset) switch (priv->intf) { -#if defined(CONFIG_STM32F0L0_ADC1) +#if defined(CONFIG_STM32F0L0G0_ADC1) case 1: { adcbit = RCC_RSTR_ADC1RST; @@ -1028,7 +1028,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) static int adc_bind(FAR struct adc_dev_s *dev, FAR const struct adc_callback_s *callback) { -#ifndef CONFIG_STM32F0L0_ADC_NOIRQ +#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; DEBUGASSERT(priv != NULL); @@ -1131,7 +1131,7 @@ static void adc_sampletime_cfg(FAR struct adc_dev_s *dev) * During sample cycles channel selection bits must remain unchanged. */ -#ifdef CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME adc_sampletime_write((FAR struct stm32_adc_dev_s *)dev); #else FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; @@ -1398,15 +1398,15 @@ static void adc_reset(FAR struct adc_dev_s *dev) static int adc_setup(FAR struct adc_dev_s *dev) { -#if !defined(CONFIG_STM32F0L0_ADC_NOIRQ) || defined(HAVE_ADC_CMN_DATA) || \ - defined(ADC_HAVE_TIMER) || !defined(CONFIG_STM32F0L0_ADC_NO_STARTUP_CONV) +#if !defined(CONFIG_STM32F0L0G0_ADC_NOIRQ) || defined(HAVE_ADC_CMN_DATA) || \ + defined(ADC_HAVE_TIMER) || !defined(CONFIG_STM32F0L0G0_ADC_NO_STARTUP_CONV) FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; #endif int ret = OK; /* Attach the ADC interrupt */ -#ifndef CONFIG_STM32F0L0_ADC_NOIRQ +#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ ret = irq_attach(priv->irq, priv->isr, NULL); if (ret < 0) { @@ -1444,7 +1444,7 @@ static int adc_setup(FAR struct adc_dev_s *dev) * or later with ANIOC_TRIGGER ioctl call. */ -#ifndef CONFIG_STM32F0L0_ADC_NO_STARTUP_CONV +#ifndef CONFIG_STM32F0L0G0_ADC_NO_STARTUP_CONV /* Start regular conversion */ adc_reg_startconv(priv, true); @@ -1453,7 +1453,7 @@ static int adc_setup(FAR struct adc_dev_s *dev) /* Enable the ADC interrupt */ -#ifndef CONFIG_STM32F0L0_ADC_NOIRQ +#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); up_enable_irq(priv->irq); #endif @@ -1490,7 +1490,7 @@ static void adc_shutdown(FAR struct adc_dev_s *dev) adc_enable(priv, false); -#ifndef CONFIG_STM32F0L0_ADC_NOIRQ +#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ /* Disable ADC interrupts and detach the ADC interrupt handler */ up_disable_irq(priv->irq); @@ -2051,7 +2051,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) return ret; } -#ifndef CONFIG_STM32F0L0_ADC_NOIRQ +#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ /**************************************************************************** * Name: adc_interrupt @@ -2158,9 +2158,9 @@ static int adc1_interrupt(int irq, FAR void *context, FAR void *arg) return OK; } -#endif /* CONFIG_STM32F0L0_ADC_NOIRQ */ +#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */ -#ifdef CONFIG_STM32F0L0_ADC_LL_OPS +#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS /**************************************************************************** * Name: adc_llops_intack @@ -2283,7 +2283,7 @@ static int adc_llops_regbufregister(FAR struct stm32_adc_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME static void adc_sampletime_write(FAR struct stm32_adc_dev_s *dev) { #error TODO adc_sampletime_write @@ -2315,7 +2315,7 @@ void adc_sampletime_set(FAR struct stm32_adc_dev_s *dev, { #error TODO adc_sampletime_write } -#endif /* CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME */ +#endif /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */ /**************************************************************************** * Name: adc_llops_dumpregs @@ -2328,7 +2328,7 @@ static void adc_llops_dumpregs(FAR struct stm32_adc_dev_s *dev) adc_dumpregs(priv); } -#endif /* CONFIG_STM32F0L0_ADC_LL_OPS */ +#endif /* CONFIG_STM32F0L0G0_ADC_LL_OPS */ /**************************************************************************** * Public Functions @@ -2360,7 +2360,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist, switch (intf) { -#ifdef CONFIG_STM32F0L0_ADC1 +#ifdef CONFIG_STM32F0L0G0_ADC1 case 1: { ainfo("ADC1 selected\n"); @@ -2396,5 +2396,5 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist, return dev; } -#endif /* CONFIG_STM32F0L0_ADC1 */ -#endif /* CONFIG_STM32F0L0_ADC */ +#endif /* CONFIG_STM32F0L0G0_ADC1 */ +#endif /* CONFIG_STM32F0L0G0_ADC */ diff --git a/arch/arm/src/stm32f0l0/stm32_adc.h b/arch/arm/src/stm32f0l0g0/stm32_adc.h similarity index 93% rename from arch/arm/src/stm32f0l0/stm32_adc.h rename to arch/arm/src/stm32f0l0g0/stm32_adc.h index a996b09290..b18d4900e3 100644 --- a/arch/arm/src/stm32f0l0/stm32_adc.h +++ b/arch/arm/src/stm32f0l0g0/stm32_adc.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H /************************************************************************************ * Included Files @@ -61,19 +61,19 @@ /* Up to 1 ADC interfaces are supported */ #if STM32_NADC < 1 -# undef CONFIG_STM32F0L0_ADC1 +# undef CONFIG_STM32F0L0G0_ADC1 #endif -#if defined(CONFIG_STM32F0L0_ADC1) +#if defined(CONFIG_STM32F0L0G0_ADC1) /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32F0L0_ADC1_DMA) +#if defined(CONFIG_STM32F0L0G0_ADC1_DMA) # define ADC_HAVE_DMA 1 #endif -#ifdef CONFIG_STM32F0L0_ADC1_DMA +#ifdef CONFIG_STM32F0L0G0_ADC1_DMA # define ADC1_HAVE_DMA 1 #else # undef ADC1_HAVE_DMA @@ -81,7 +81,7 @@ /* EXTSEL */ -#if defined(CONFIG_STM32F0L0_STM32F0) +#if defined(CONFIG_STM32F0L0G0_STM32F0) # define ADC1_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_TRG0 # define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 # define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 @@ -90,7 +90,7 @@ /* TRG5 reserved */ /* TRG6 reserved */ /* TRG7 reserved */ -#elif defined(CONFIG_STM32F0L0_STM32L0) +#elif defined(CONFIG_STM32F0L0G0_STM32L0) /* TRG0 reserved */ # define ADC1_EXTSEL_T21CC2 ADC12_CFGR1_EXTSEL_TRG1 # define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 @@ -99,7 +99,7 @@ # define ADC1_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_TRG5 /* TRG6 reserved */ # define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 -#elif defined(CONFIG_STM32F0L0_STM32G0) +#elif defined(CONFIG_STM32F0L0G0_STM32G0) # define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_TRG0 # define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 # define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 @@ -203,9 +203,9 @@ enum stm32_adc_resoluton_e ADC_RESOLUTION_6BIT = 3 /* 6 bit */ }; -#ifdef CONFIG_STM32F0L0_ADC_LL_OPS +#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS -#ifdef CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME /* Channel and sample time pair */ @@ -230,7 +230,7 @@ struct adc_sample_time_s * same value of the sample time */ uint8_t all_ch_sample_time:3; /* Sample time for all channels */ }; -#endif /* CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME */ +#endif /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */ /* This structure provides the publicly visable representation of the * "lower-half" ADC driver structure. @@ -277,7 +277,7 @@ struct stm32_adc_ops_s void (*reg_startconv)(FAR struct stm32_adc_dev_s *dev, bool state); -#ifdef CONFIG_STM32F0L0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME /* Set ADC sample time */ void (*stime_set)(FAR struct stm32_adc_dev_s *dev, @@ -291,7 +291,7 @@ struct stm32_adc_ops_s void (*dump_regs)(FAR struct stm32_adc_dev_s *dev); }; -#endif /* CONFIG_STM32F0L0_ADC_LL_OPS */ +#endif /* CONFIG_STM32F0L0G0_ADC_LL_OPS */ /************************************************************************************ * Public Function Prototypes @@ -330,7 +330,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist, * Name: stm32_adc_llops_get ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_ADC_LL_OPS +#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS FAR const struct stm32_adc_ops_s *stm32_adc_llops_get(FAR struct adc_dev_s *dev); #endif @@ -340,5 +340,5 @@ FAR const struct stm32_adc_ops_s *stm32_adc_llops_get(FAR struct adc_dev_s *dev) #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F0L0_ADC1 */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_ADC_H */ +#endif /* CONFIG_STM32F0L0G0_ADC1 */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_aes.c b/arch/arm/src/stm32f0l0g0/stm32_aes.c similarity index 99% rename from arch/arm/src/stm32f0l0/stm32_aes.c rename to arch/arm/src/stm32f0l0g0/stm32_aes.c index d5d892ba50..2a5281f01e 100644 --- a/arch/arm/src/stm32f0l0/stm32_aes.c +++ b/arch/arm/src/stm32f0l0g0/stm32_aes.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_aes.c + * arch/arm/src/stm32f0l0g0/stm32_aes.c * * Copyright (C) 2015 Haltian Ltd. All rights reserved. * Author: Juha Niskanen diff --git a/arch/arm/src/stm32f0l0/stm32_aes.h b/arch/arm/src/stm32f0l0g0/stm32_aes.h similarity index 93% rename from arch/arm/src/stm32f0l0/stm32_aes.h rename to arch/arm/src/stm32f0l0g0/stm32_aes.h index 07501b564f..64b6e841a5 100644 --- a/arch/arm/src/stm32f0l0/stm32_aes.h +++ b/arch/arm/src/stm32f0l0g0/stm32_aes.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/stm32_aes.h + * arch/arm/src/stm32f0l0g0/stm32_aes.h * * Copyright (C) 2014 Haltian Ltd. All rights reserved. * Author: Juha Niskanen @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_AES_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_AES_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H /************************************************************************************ * Included Files @@ -60,4 +60,4 @@ * Inline Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_AES_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_dma.h b/arch/arm/src/stm32f0l0g0/stm32_dma.h similarity index 98% rename from arch/arm/src/stm32f0l0/stm32_dma.h rename to arch/arm/src/stm32f0l0g0/stm32_dma.h index 2d5b0137cd..2744931924 100644 --- a/arch/arm/src/stm32f0l0/stm32_dma.h +++ b/arch/arm/src/stm32f0l0g0/stm32_dma.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_DMA_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_DMA_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H /************************************************************************************ * Included Files @@ -245,7 +245,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0_DMACAPABLE +#ifdef CONFIG_STM32F0L0G0_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else # define stm32_dmacapable(maddr, count, ccr) (true) @@ -331,4 +331,4 @@ uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_DMA_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_dma_v1.c b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0/stm32_dma_v1.c rename to arch/arm/src/stm32f0l0g0/stm32_dma_v1.c index ab8722f3bd..6740509c0c 100644 --- a/arch/arm/src/stm32f0l0/stm32_dma_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c @@ -64,7 +64,7 @@ * the DMA requests for each channel. */ -#ifdef CONFIG_STM32F0L0_HAVE_DMAMUX +#ifdef CONFIG_STM32F0L0G0_HAVE_DMAMUX # error DMAMUX not supported yet #endif @@ -655,7 +655,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0_DMACAPABLE +#ifdef CONFIG_STM32F0L0G0_DMACAPABLE bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; diff --git a/arch/arm/src/stm32f0l0/stm32_exti.h b/arch/arm/src/stm32f0l0g0/stm32_exti.h similarity index 96% rename from arch/arm/src/stm32f0l0/stm32_exti.h rename to arch/arm/src/stm32f0l0g0/stm32_exti.h index d83e4c725d..d708333feb 100644 --- a/arch/arm/src/stm32f0l0/stm32_exti.h +++ b/arch/arm/src/stm32f0l0g0/stm32_exti.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/stm32_exti.h + * arch/arm/src/stm32f0l0g0/stm32_exti.h * * Copyright (C) 2009, 2012, 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H /************************************************************************************ * Included Files @@ -140,4 +140,4 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_exti_gpio.c b/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c similarity index 97% rename from arch/arm/src/stm32f0l0/stm32_exti_gpio.c rename to arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c index 03c4fa8329..e841faef4c 100644 --- a/arch/arm/src/stm32f0l0/stm32_exti_gpio.c +++ b/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_exti_gpio.c + * arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c * * Copyright (C) 2009, 2011-2012, 2015, 2017 Gregory Nutt. All rights reserved. * Copyright (C) 2011 Uros Platise. All rights reserved. @@ -59,7 +59,7 @@ * Pre-processor Definitions ************************************************************************************/ -#if defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V2) +#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) # define STM32_EXTI_FTSR STM32_EXTI_FTSR1 # define STM32_EXTI_RTSR STM32_EXTI_RTSR1 # define STM32_EXTI_IMR STM32_EXTI_IMR1 @@ -92,7 +92,7 @@ static struct gpio_callback_s g_gpio_callbacks[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -#if defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V1) +#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1) static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { @@ -136,7 +136,7 @@ static int stm32_exti_multiisr(int irq, void *context, void *arg, return ret; } -#elif defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V2) +#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { diff --git a/arch/arm/src/stm32f0l0/stm32_gpio.c b/arch/arm/src/stm32f0l0g0/stm32_gpio.c similarity index 97% rename from arch/arm/src/stm32f0l0/stm32_gpio.c rename to arch/arm/src/stm32f0l0g0/stm32_gpio.c index 5c32964bf4..35d8d3cafa 100644 --- a/arch/arm/src/stm32f0l0/stm32_gpio.c +++ b/arch/arm/src/stm32f0l0g0/stm32_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_gpio.c + * arch/arm/src/stm32f0l0g0/stm32_gpio.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -47,16 +47,16 @@ #include #include -#include +#include #include "up_arch.h" #include "chip.h" #include "stm32_gpio.h" -#if defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V1) +#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1) # include "hardware/stm32_syscfg.h" -#elif defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V2) +#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) # include "hardware/stm32_exti.h" #endif @@ -321,7 +321,7 @@ int stm32_configgpio(uint32_t cfgset) uint32_t regaddr; int shift; -#if defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V1) +#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1) /* Set the bits in the SYSCFG EXTICR register */ regaddr = STM32_SYSCFG_EXTICR(pin); @@ -331,7 +331,7 @@ int stm32_configgpio(uint32_t cfgset) regval |= (((uint32_t)port) << shift); putreg32(regval, regaddr); -#elif defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V2) +#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) /* Set the bits in the EXTI EXTICR register */ regaddr = STM32_EXTI_EXTICR(pin); diff --git a/arch/arm/src/stm32f0l0/stm32_gpio.h b/arch/arm/src/stm32f0l0g0/stm32_gpio.h similarity index 98% rename from arch/arm/src/stm32f0l0/stm32_gpio.h rename to arch/arm/src/stm32f0l0g0/stm32_gpio.h index 563709f71f..d4c0969d0f 100644 --- a/arch/arm/src/stm32f0l0/stm32_gpio.h +++ b/arch/arm/src/stm32f0l0g0/stm32_gpio.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/stm32_gpio.h + * arch/arm/src/stm32f0l0g0/stm32_gpio.h * * Copyright (C) 2009, 2011-2012, 2015 Gregory Nutt. All rights reserved. * Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved. @@ -36,8 +36,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H /************************************************************************************ * Included Files @@ -51,7 +51,7 @@ #endif #include -#include +#include #include "chip.h" #include "hardware/stm32_gpio.h" @@ -370,4 +370,4 @@ void stm32_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_hsi48.c b/arch/arm/src/stm32f0l0g0/stm32_hsi48.c similarity index 99% rename from arch/arm/src/stm32f0l0/stm32_hsi48.c rename to arch/arm/src/stm32f0l0g0/stm32_hsi48.c index 928f1bab0c..6f1fc8929d 100644 --- a/arch/arm/src/stm32f0l0/stm32_hsi48.c +++ b/arch/arm/src/stm32f0l0g0/stm32_hsi48.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_hsi48.c + * arch/arm/src/stm32f0l0g0/stm32_hsi48.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/stm32f0l0/stm32_hsi48.h b/arch/arm/src/stm32f0l0g0/stm32_hsi48.h similarity index 94% rename from arch/arm/src/stm32f0l0/stm32_hsi48.h rename to arch/arm/src/stm32f0l0g0/stm32_hsi48.h index bbf8cd9c69..e638ca7f52 100644 --- a/arch/arm/src/stm32f0l0/stm32_hsi48.h +++ b/arch/arm/src/stm32f0l0g0/stm32_hsi48.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/stm32_hsi48.h + * arch/arm/src/stm32f0l0g0/stm32_hsi48.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H /************************************************************************************ * Included Files @@ -43,7 +43,7 @@ #include -#ifdef CONFIG_STM32F0L0_HAVE_HSI48 +#ifdef CONFIG_STM32F0L0G0_HAVE_HSI48 /************************************************************************************ * Public Types @@ -106,5 +106,5 @@ void stm32_enable_hsi48(enum syncsrc_e syncsrc); void stm32_disable_hsi48(void); -#endif /* CONFIG_STM32F0L0_HAVE_HSI48 */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H */ +#endif /* CONFIG_STM32F0L0G0_HAVE_HSI48 */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_i2c.c b/arch/arm/src/stm32f0l0g0/stm32_i2c.c similarity index 97% rename from arch/arm/src/stm32f0l0/stm32_i2c.c rename to arch/arm/src/stm32f0l0g0/stm32_i2c.c index ac61504072..1c725c8fdd 100644 --- a/arch/arm/src/stm32f0l0/stm32_i2c.c +++ b/arch/arm/src/stm32f0l0g0/stm32_i2c.c @@ -158,21 +158,21 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32F0L0_I2C1 - * CONFIG_STM32F0L0_I2C2 - * CONFIG_STM32F0L0_I2C3 - * CONFIG_STM32F0L0_I2C4 + * CONFIG_STM32F0L0G0_I2C1 + * CONFIG_STM32F0L0G0_I2C2 + * CONFIG_STM32F0L0G0_I2C3 + * CONFIG_STM32F0L0G0_I2C4 * - * To configure the ISR timeout using fixed values (CONFIG_STM32F0L0_I2C_DYNTIMEO=n): + * To configure the ISR timeout using fixed values (CONFIG_STM32F0L0G0_I2C_DYNTIMEO=n): * - * CONFIG_STM32F0L0_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32F0L0_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32F0L0_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32F0L0G0_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32F0L0G0_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32F0L0G0_I2CTIMEOTICKS (Timeout in ticks) * - * To configure the ISR timeout using dynamic values (CONFIG_STM32F0L0_I2C_DYNTIMEO=y): + * To configure the ISR timeout using dynamic values (CONFIG_STM32F0L0G0_I2C_DYNTIMEO=y): * - * CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE (Timeout in microseconds per byte) - * CONFIG_STM32F0L0_I2C_DYNTIMEO_STARTSTOP (Timeout for start/stop in milliseconds) + * CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE (Timeout in microseconds per byte) + * CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP (Timeout for start/stop in milliseconds) * * Debugging output enabled with: * @@ -243,8 +243,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32F0L0_I2C1) || defined(CONFIG_STM32F0L0_I2C2) || \ - defined(CONFIG_STM32F0L0_I2C3) || defined(CONFIG_STM32F0L0_I2C4) +#if defined(CONFIG_STM32F0L0G0_I2C1) || defined(CONFIG_STM32F0L0G0_I2C2) || \ + defined(CONFIG_STM32F0L0G0_I2C3) || defined(CONFIG_STM32F0L0G0_I2C4) /************************************************************************************ * Pre-processor Definitions @@ -260,25 +260,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32F0L0_I2CTIMEOSEC) && !defined(CONFIG_STM32F0L0_I2CTIMEOMS) -# define CONFIG_STM32F0L0_I2CTIMEOSEC 0 -# define CONFIG_STM32F0L0_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32F0L0G0_I2CTIMEOSEC) && !defined(CONFIG_STM32F0L0G0_I2CTIMEOMS) +# define CONFIG_STM32F0L0G0_I2CTIMEOSEC 0 +# define CONFIG_STM32F0L0G0_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32F0L0_I2CTIMEOSEC) -# define CONFIG_STM32F0L0_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32F0L0_I2CTIMEOMS) -# define CONFIG_STM32F0L0_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32F0L0G0_I2CTIMEOSEC) +# define CONFIG_STM32F0L0G0_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32F0L0G0_I2CTIMEOMS) +# define CONFIG_STM32F0L0G0_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32F0L0_I2CTIMEOTICKS -# define CONFIG_STM32F0L0_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32F0L0_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F0L0_I2CTIMEOMS)) +#ifndef CONFIG_STM32F0L0G0_I2CTIMEOTICKS +# define CONFIG_STM32F0L0G0_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32F0L0G0_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F0L0G0_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32F0L0_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32F0L0_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F0L0_I2CTIMEOTICKS) +#ifndef CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F0L0G0_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -445,9 +445,9 @@ static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); static inline void stm32_i2c_sem_wait(FAR struct i2c_master_s *dev); -#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO +#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32F0L0_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32F0L0G0_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_post(FAR struct i2c_master_s *dev); @@ -488,7 +488,7 @@ static int stm32_i2c_pm_prepare(FAR struct pm_callback_s *cb, int domain, * Private Data ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_I2C1 +#ifdef CONFIG_STM32F0L0G0_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -519,7 +519,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32F0L0_I2C2 +#ifdef CONFIG_STM32F0L0G0_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -550,7 +550,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32F0L0_I2C3 +#ifdef CONFIG_STM32F0L0G0_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -581,7 +581,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32F0L0_I2C4 +#ifdef CONFIG_STM32F0L0G0_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -733,7 +733,7 @@ static inline void stm32_i2c_sem_wait(FAR struct i2c_master_s *dev) * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO +#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -750,7 +750,7 @@ static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs) * factor. */ - return (useconds_t)(CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return (useconds_t)(CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -809,13 +809,13 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) /* Calculate a time in the future */ -#if CONFIG_STM32F0L0_I2CTIMEOSEC > 0 - abstime.tv_sec += CONFIG_STM32F0L0_I2CTIMEOSEC; +#if CONFIG_STM32F0L0G0_I2CTIMEOSEC > 0 + abstime.tv_sec += CONFIG_STM32F0L0G0_I2CTIMEOSEC; #endif /* Add a value proportional to the number of bytes in the transfer */ -#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO +#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO abstime.tv_nsec += 1000 * stm32_i2c_tousecs(priv->msgc, priv->msgv); if (abstime.tv_nsec >= 1000 * 1000 * 1000) { @@ -823,8 +823,8 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) abstime.tv_nsec -= 1000 * 1000 * 1000; } -#elif CONFIG_STM32F0L0_I2CTIMEOMS > 0 - abstime.tv_nsec += CONFIG_STM32F0L0_I2CTIMEOMS * 1000 * 1000; +#elif CONFIG_STM32F0L0G0_I2CTIMEOMS > 0 + abstime.tv_nsec += CONFIG_STM32F0L0G0_I2CTIMEOMS * 1000 * 1000; if (abstime.tv_nsec >= 1000 * 1000 * 1000) { abstime.tv_sec++; @@ -870,10 +870,10 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO +#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO timeout = USEC2TICK(stm32_i2c_tousecs(priv->msgc, priv->msgv)); #else - timeout = CONFIG_STM32F0L0_I2CTIMEOTICKS; + timeout = CONFIG_STM32F0L0G0_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -1012,10 +1012,10 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32F0L0_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32F0L0_I2CTIMEOTICKS; + timeout = CONFIG_STM32F0L0G0_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2751,22 +2751,22 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32F0L0_I2C1 +#ifdef CONFIG_STM32F0L0G0_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32F0L0_I2C2 +#ifdef CONFIG_STM32F0L0G0_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32F0L0_I2C3 +#ifdef CONFIG_STM32F0L0G0_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32F0L0_I2C4 +#ifdef CONFIG_STM32F0L0G0_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -2861,5 +2861,5 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s * dev) return OK; } -#endif /* CONFIG_STM32F0L0_I2C1 || CONFIG_STM32F0L0_I2C2 || \ - CONFIG_STM32F0L0_I2C3 || CONFIG_STM32F0L0_I2C4 */ +#endif /* CONFIG_STM32F0L0G0_I2C1 || CONFIG_STM32F0L0G0_I2C2 || \ + CONFIG_STM32F0L0G0_I2C3 || CONFIG_STM32F0L0G0_I2C4 */ diff --git a/arch/arm/src/stm32f0l0/stm32_i2c.h b/arch/arm/src/stm32f0l0g0/stm32_i2c.h similarity index 89% rename from arch/arm/src/stm32f0l0/stm32_i2c.h rename to arch/arm/src/stm32f0l0g0/stm32_i2c.h index 9a9d881dce..1d79133545 100644 --- a/arch/arm/src/stm32f0l0/stm32_i2c.h +++ b/arch/arm/src/stm32f0l0g0/stm32_i2c.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_i2c.h + * arch/arm/src/stm32f0l0g0/stm32_i2c.h * * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H /**************************************************************************** * Included Files @@ -54,10 +54,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO -# if CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32F0L0_I2C_DYNTIMEO because of CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32F0L0_I2C_DYNTIMEO +#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO +# if CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32F0L0G0_I2C_DYNTIMEO because of CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32F0L0G0_I2C_DYNTIMEO # endif #endif @@ -101,4 +101,4 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port); int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev); -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_idle.c b/arch/arm/src/stm32f0l0g0/stm32_idle.c similarity index 98% rename from arch/arm/src/stm32f0l0/stm32_idle.c rename to arch/arm/src/stm32f0l0g0/stm32_idle.c index 982bd0579c..c56ad593ad 100644 --- a/arch/arm/src/stm32f0l0/stm32_idle.c +++ b/arch/arm/src/stm32f0l0g0/stm32_idle.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_idle.c + * arch/arm/src/stm32f0l0g0/stm32_idle.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -97,7 +97,7 @@ void up_idle(void) * disabled in order to save power." */ -#ifdef CONFIG_STM32F0L0_GPDMA +#ifdef CONFIG_STM32F0L0G0_GPDMA if (g_dma_inprogress == 0) #endif { diff --git a/arch/arm/src/stm32f0l0/stm32_irq.c b/arch/arm/src/stm32f0l0g0/stm32_irq.c similarity index 99% rename from arch/arm/src/stm32f0l0/stm32_irq.c rename to arch/arm/src/stm32f0l0g0/stm32_irq.c index 3161352812..d2d70eb7fd 100644 --- a/arch/arm/src/stm32f0l0/stm32_irq.c +++ b/arch/arm/src/stm32f0l0g0/stm32_irq.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_irq.c + * arch/arm/src/stm32f0l0g0/stm32_irq.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -245,7 +245,7 @@ void up_irqinitialize(void) * configured pin interrupts. */ -#ifdef CONFIG_STM32F0L0_GPIOIRQ +#ifdef CONFIG_STM32F0L0G0_GPIOIRQ stm32_gpioirqinitialize(); #endif diff --git a/arch/arm/src/stm32f0l0/stm32_lowputc.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc.c similarity index 94% rename from arch/arm/src/stm32f0l0/stm32_lowputc.c rename to arch/arm/src/stm32f0l0g0/stm32_lowputc.c index 31f1356554..71ab893d4f 100644 --- a/arch/arm/src/stm32f0l0/stm32_lowputc.c +++ b/arch/arm/src/stm32f0l0g0/stm32_lowputc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_lowputc.c + * arch/arm/src/stm32f0l0g0/stm32_lowputc.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -44,9 +44,9 @@ * Public Functions ****************************************************************************/ -#if defined(CONFIG_STM32F0L0_HAVE_IP_USART_V1) +#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1) # include "stm32_lowputc_v1.c" -#elif defined(CONFIG_STM32F0L0_HAVE_IP_USART_V2) +#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2) # include "stm32_lowputc_v2.c" #else # error "Unsupported STM32 M0 serial" diff --git a/arch/arm/src/stm32f0l0/stm32_lowputc.h b/arch/arm/src/stm32f0l0g0/stm32_lowputc.h similarity index 93% rename from arch/arm/src/stm32f0l0/stm32_lowputc.h rename to arch/arm/src/stm32f0l0g0/stm32_lowputc.h index ee6a1723ec..25ba89c7b4 100644 --- a/arch/arm/src/stm32f0l0/stm32_lowputc.h +++ b/arch/arm/src/stm32f0l0g0/stm32_lowputc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/stm32_lowputc.h + * arch/arm/src/stm32f0l0g0/stm32_lowputc.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H /************************************************************************************ * Included Files @@ -77,4 +77,4 @@ void stm32_lowsetup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_lowputc_v1.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0/stm32_lowputc_v1.c rename to arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c index fd477fc0e4..a1e1cd158e 100644 --- a/arch/arm/src/stm32f0l0/stm32_lowputc_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_lowputc_v1.c + * arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c * * Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -280,7 +280,7 @@ void stm32_lowsetup(void) /* Setup clocking and GPIO pins for all configured USARTs */ -#ifdef CONFIG_STM32F0L0_USART1 +#ifdef CONFIG_STM32F0L0G0_USART1 /* Enable USART APB2 clock */ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN); @@ -296,7 +296,7 @@ void stm32_lowsetup(void) #endif #endif -#ifdef CONFIG_STM32F0L0_USART2 +#ifdef CONFIG_STM32F0L0G0_USART2 /* Enable USART APB1 clock */ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN); @@ -312,7 +312,7 @@ void stm32_lowsetup(void) #endif #endif -#ifdef CONFIG_STM32F0L0_USART3 +#ifdef CONFIG_STM32F0L0G0_USART3 /* Enable USART APB1 clock */ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN); @@ -328,7 +328,7 @@ void stm32_lowsetup(void) #endif #endif -#ifdef CONFIG_STM32F0L0_USART4 +#ifdef CONFIG_STM32F0L0G0_USART4 /* Enable USART APB1 clock */ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN); @@ -344,7 +344,7 @@ void stm32_lowsetup(void) #endif #endif -#ifdef CONFIG_STM32F0L0_USART5 +#ifdef CONFIG_STM32F0L0G0_USART5 /* Enable USART APB1 clock */ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN); diff --git a/arch/arm/src/stm32f0l0/stm32_lowputc_v2.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c similarity index 99% rename from arch/arm/src/stm32f0l0/stm32_lowputc_v2.c rename to arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c index 805c4e6929..3d731513e6 100644 --- a/arch/arm/src/stm32f0l0/stm32_lowputc_v2.c +++ b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_lowputc_v2.c + * arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/stm32f0l0/stm32_lse.c b/arch/arm/src/stm32f0l0g0/stm32_lse.c similarity index 100% rename from arch/arm/src/stm32f0l0/stm32_lse.c rename to arch/arm/src/stm32f0l0g0/stm32_lse.c diff --git a/arch/arm/src/stm32f0l0/stm32_pwr.c b/arch/arm/src/stm32f0l0g0/stm32_pwr.c similarity index 98% rename from arch/arm/src/stm32f0l0/stm32_pwr.c rename to arch/arm/src/stm32f0l0g0/stm32_pwr.c index fd7c8dfd84..18907f98e5 100644 --- a/arch/arm/src/stm32f0l0/stm32_pwr.c +++ b/arch/arm/src/stm32f0l0g0/stm32_pwr.c @@ -49,7 +49,7 @@ #include "up_arch.h" #include "stm32_pwr.h" -#if defined(CONFIG_STM32F0L0_PWR) +#if defined(CONFIG_STM32F0L0G0_PWR) /************************************************************************************ * Private Data @@ -310,7 +310,7 @@ bool stm32_pwr_getwuf(void) * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_ENERGYLITE +#ifdef CONFIG_STM32F0L0G0_ENERGYLITE void stm32_pwr_setvos(uint16_t vos) { uint16_t regval; @@ -401,6 +401,6 @@ void stm32_pwr_disablepvd(void) stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, PWR_CR_PVDE, 0); } -#endif /* CONFIG_STM32F0L0_ENERGYLITE */ +#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */ -#endif /* CONFIG_STM32F0L0_PWR */ +#endif /* CONFIG_STM32F0L0G0_PWR */ diff --git a/arch/arm/src/stm32f0l0/stm32_pwr.h b/arch/arm/src/stm32f0l0g0/stm32_pwr.h similarity index 96% rename from arch/arm/src/stm32f0l0/stm32_pwr.h rename to arch/arm/src/stm32f0l0g0/stm32_pwr.h index b137bc7a91..563ba4b37a 100644 --- a/arch/arm/src/stm32f0l0/stm32_pwr.h +++ b/arch/arm/src/stm32f0l0g0/stm32_pwr.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/stm32_pwr.h + * arch/arm/src/stm32f0l0g0/stm32_pwr.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H /************************************************************************************ * Included Files @@ -181,7 +181,7 @@ bool stm32_pwr_getwuf(void); * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_ENERGYLITE +#ifdef CONFIG_STM32F0L0G0_ENERGYLITE void stm32_pwr_setvos(uint16_t vos); /************************************************************************************ @@ -223,7 +223,7 @@ void stm32_pwr_enablepvd(void); void stm32_pwr_disablepvd(void); -#endif /* CONFIG_STM32F0L0_ENERGYLITE */ +#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */ #undef EXTERN #if defined(__cplusplus) @@ -231,4 +231,4 @@ void stm32_pwr_disablepvd(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_rcc.c b/arch/arm/src/stm32f0l0g0/stm32_rcc.c similarity index 97% rename from arch/arm/src/stm32f0l0/stm32_rcc.c rename to arch/arm/src/stm32f0l0g0/stm32_rcc.c index 73cf99a940..353ab5fb9f 100644 --- a/arch/arm/src/stm32f0l0/stm32_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_rcc.c + * arch/arm/src/stm32f0l0g0/stm32_rcc.c * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt @@ -58,12 +58,12 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32F0L0_RNG +#ifdef CONFIG_STM32F0L0G0_RNG # ifndef STM32_USE_CLK48 # error RNG requires CLK48 enabled # endif #endif -#ifdef CONFIG_STM32F0L0_USB +#ifdef CONFIG_STM32F0L0G0_USB # ifndef STM32_USE_CLK48 # error USB requires CLK48 enabled # endif @@ -113,7 +113,7 @@ * ****************************************************************************/ -#if defined(CONFIG_STM32F0L0_RTC) && defined(CONFIG_STM32F0L0_PWR) +#if defined(CONFIG_STM32F0L0G0_RTC) && defined(CONFIG_STM32F0L0G0_PWR) static inline void rcc_resetbkp(void) { uint32_t regval; @@ -188,7 +188,7 @@ void stm32_clockconfig(void) #endif -#ifdef CONFIG_STM32F0L0_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32F0L0G0_SYSCFG_IOCOMPENSATION /* Enable I/O Compensation */ stm32_iocompensation(); diff --git a/arch/arm/src/stm32f0l0/stm32_rcc.h b/arch/arm/src/stm32f0l0g0/stm32_rcc.h similarity index 94% rename from arch/arm/src/stm32f0l0/stm32_rcc.h rename to arch/arm/src/stm32f0l0g0/stm32_rcc.h index d157305efb..5c5444040e 100644 --- a/arch/arm/src/stm32f0l0/stm32_rcc.h +++ b/arch/arm/src/stm32f0l0g0/stm32_rcc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/stm32_rcc.h + * arch/arm/src/stm32f0l0g0/stm32_rcc.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H /************************************************************************************ * Included Files @@ -80,4 +80,4 @@ void stm32_clockconfig(void); void stm32_rcc_enablelse(void); -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_rng.c b/arch/arm/src/stm32f0l0g0/stm32_rng.c similarity index 98% rename from arch/arm/src/stm32f0l0/stm32_rng.c rename to arch/arm/src/stm32f0l0g0/stm32_rng.c index 1412b3c401..001c5805e9 100644 --- a/arch/arm/src/stm32f0l0/stm32_rng.c +++ b/arch/arm/src/stm32f0l0g0/stm32_rng.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_rng.c + * arch/arm/src/stm32f0l0g0/stm32_rng.c * * Copyright (C) 2012 Max Holtzberg. All rights reserved. * Author: Max Holtzberg @@ -54,7 +54,7 @@ #include "hardware/stm32_rng.h" #include "up_internal.h" -#if defined(CONFIG_STM32F0L0_RNG) +#if defined(CONFIG_STM32F0L0G0_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) /**************************************************************************** @@ -332,4 +332,4 @@ void devurandom_register(void) #endif #endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32F0L0_RNG */ +#endif /* CONFIG_STM32F0L0G0_RNG */ diff --git a/arch/arm/src/stm32f0l0/stm32_serial.c b/arch/arm/src/stm32f0l0g0/stm32_serial.c similarity index 94% rename from arch/arm/src/stm32f0l0/stm32_serial.c rename to arch/arm/src/stm32f0l0g0/stm32_serial.c index b94bf147aa..6ff7d58291 100644 --- a/arch/arm/src/stm32f0l0/stm32_serial.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_serial.c + * arch/arm/src/stm32f0l0g0/stm32_serial.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -51,9 +51,9 @@ * - STM32 UART IP version 2 - G0 */ -#if defined(CONFIG_STM32F0L0_HAVE_IP_USART_V1) +#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1) # include "stm32_serial_v1.c" -#elif defined(CONFIG_STM32F0L0_HAVE_IP_USART_V2) +#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2) # include "stm32_serial_v2.c" #else # error "Unsupported STM32 M0 serial" diff --git a/arch/arm/src/stm32f0l0/stm32_serial.h b/arch/arm/src/stm32f0l0g0/stm32_serial.h similarity index 91% rename from arch/arm/src/stm32f0l0/stm32_serial.h rename to arch/arm/src/stm32f0l0g0/stm32_serial.h index b51ef343fe..8fe1f9cb2b 100644 --- a/arch/arm/src/stm32f0l0/stm32_serial.h +++ b/arch/arm/src/stm32f0l0g0/stm32_serial.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/stm32_serial.h + * arch/arm/src/stm32f0l0g0/stm32_serial.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H /************************************************************************************ * Included Files @@ -47,4 +47,4 @@ * Pre-processor Definitions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_serial_v1.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c similarity index 97% rename from arch/arm/src/stm32f0l0/stm32_serial_v1.c rename to arch/arm/src/stm32f0l0g0/stm32_serial_v1.c index 1a8f003b43..97bf3fbe2d 100644 --- a/arch/arm/src/stm32f0l0/stm32_serial_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_serial_v1.c + * arch/arm/src/stm32f0l0g0/stm32_serial_v1.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -97,14 +97,14 @@ */ # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# ifndef CONFIG_STM32F0L0_DMA1 -# error STM32F0 USART2/3 receive DMA requires CONFIG_STM32F0L0_DMA1 +# ifndef CONFIG_STM32F0L0G0_DMA1 +# error STM32F0 USART2/3 receive DMA requires CONFIG_STM32F0L0G0_DMA1 # endif # endif # if defined(CONFIG_USART4_RXDMA) || defined(CONFIG_USART5_RXDMA) -# ifndef CONFIG_STM32F0L0_DMA2 -# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32F0L0_DMA2 +# ifndef CONFIG_STM32F0L0G0_DMA2 +# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32F0L0G0_DMA2 # endif # endif @@ -173,8 +173,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY 10 #endif #if defined(CONFIG_PM) # define PM_IDLE_DOMAIN 0 /* Revisit */ @@ -191,7 +191,7 @@ * See stm32serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -363,7 +363,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32F0L0_USART1 +#ifdef CONFIG_STM32F0L0G0_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -371,7 +371,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0L0_USART2 +#ifdef CONFIG_STM32F0L0G0_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -379,7 +379,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0L0_USART3 +#ifdef CONFIG_STM32F0L0G0_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -387,7 +387,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0L0_USART4 +#ifdef CONFIG_STM32F0L0G0_USART4 static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; # ifdef CONFIG_USART4_RXDMA @@ -395,7 +395,7 @@ static char g_usart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0L0_USART5 +#ifdef CONFIG_STM32F0L0G0_USART5 static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE]; static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE]; # ifdef CONFIG_USART5_RXDMA @@ -405,7 +405,7 @@ static char g_usart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32F0L0_USART1 +#ifdef CONFIG_STM32F0L0G0_USART1 static struct stm32_serial_s g_usart1priv = { .dev = @@ -466,7 +466,7 @@ static struct stm32_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32F0L0_USART2 +#ifdef CONFIG_STM32F0L0G0_USART2 static struct stm32_serial_s g_usart2priv = { .dev = @@ -527,7 +527,7 @@ static struct stm32_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32F0L0_USART3 +#ifdef CONFIG_STM32F0L0G0_USART3 static struct stm32_serial_s g_usart3priv = { .dev = @@ -588,7 +588,7 @@ static struct stm32_serial_s g_usart3priv = /* This describes the state of the STM32 USART4 port. */ -#ifdef CONFIG_STM32F0L0_USART4 +#ifdef CONFIG_STM32F0L0G0_USART4 static struct stm32_serial_s g_usart4priv = { .dev = @@ -653,7 +653,7 @@ static struct stm32_serial_s g_usart4priv = /* This describes the state of the STM32 USART5 port. */ -#ifdef CONFIG_STM32F0L0_USART5 +#ifdef CONFIG_STM32F0L0G0_USART5 static struct stm32_serial_s g_usart5priv = { .dev = @@ -720,19 +720,19 @@ static struct stm32_serial_s g_usart5priv = FAR static struct stm32_serial_s * const g_uart_devs[STM32_NUSART] = { -#ifdef CONFIG_STM32F0L0_USART1 +#ifdef CONFIG_STM32F0L0G0_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32F0L0_USART2 +#ifdef CONFIG_STM32F0L0G0_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32F0L0_USART3 +#ifdef CONFIG_STM32F0L0G0_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32F0L0_USART4 +#ifdef CONFIG_STM32F0L0G0_USART4 [3] = &g_usart4priv, #endif -#ifdef CONFIG_STM32F0L0_USART5 +#ifdef CONFIG_STM32F0L0G0_USART5 [4] = &g_usart5priv, #endif }; @@ -1008,7 +1008,7 @@ static void stm32serial_setformat(FAR struct uart_dev_s *dev) regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32F0L0_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1050,31 +1050,31 @@ static void stm32serial_setapbclock(FAR struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32F0L0_USART1 +#ifdef CONFIG_STM32F0L0G0_USART1 case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F0L0_USART2 +#ifdef CONFIG_STM32F0L0G0_USART2 case STM32_USART2_BASE: rcc_en = RCC_APB1ENR_USART2EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0_USART3 +#ifdef CONFIG_STM32F0L0G0_USART3 case STM32_USART3_BASE: rcc_en = RCC_APB1ENR_USART3EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0_USART4 +#ifdef CONFIG_STM32F0L0G0_USART4 case STM32_USART4_BASE: rcc_en = RCC_APB1ENR_USART4EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0_USART5 +#ifdef CONFIG_STM32F0L0G0_USART5 case STM32_USART5_BASE: rcc_en = RCC_APB1ENR_USART5EN; regaddr = STM32_RCC_APB1ENR; @@ -1135,7 +1135,7 @@ static int stm32serial_setup(FAR struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32F0L0_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1460,8 +1460,8 @@ static int up_interrupt(int irq, FAR void *context, FAR void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1592,7 +1592,7 @@ static int stm32serial_ioctl(FAR struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32F0L0_USART_SINGLEWIRE +#ifdef CONFIG_STM32F0L0G0_USART_SINGLEWIRE #warning please review the potential use of ALTERNATE_FUNCTION_OPENDRAIN case TIOCSSINGLEWIRE: { @@ -1713,8 +1713,8 @@ static int stm32serial_ioctl(FAR struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32F0L0_USART_BREAKS -# ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32F0L0G0_USART_BREAKS +# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -1927,7 +1927,7 @@ static bool stm32serial_rxflowcontrol(FAR struct uart_dev_s *dev, FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32F0L0_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2173,7 +2173,7 @@ static void stm32serial_txint(FAR struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { return; @@ -2426,7 +2426,7 @@ void up_serialinit(void) #if CONSOLE_USART > 0 (void)uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev); -#ifndef CONFIG_STM32F0L0_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING /* If not disabled, register the console USART to ttyS0 and exclude * it from initializing it further down */ @@ -2455,7 +2455,7 @@ void up_serialinit(void) continue; } -#ifndef CONFIG_STM32F0L0_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32f0l0/stm32_serial_v2.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c similarity index 97% rename from arch/arm/src/stm32f0l0/stm32_serial_v2.c rename to arch/arm/src/stm32f0l0g0/stm32_serial_v2.c index 5f86626150..3463093471 100644 --- a/arch/arm/src/stm32f0l0/stm32_serial_v2.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_serial.c + * arch/arm/src/stm32f0l0g0/stm32_serial.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt @@ -70,10 +70,10 @@ #include -#ifdef CONFIG_STM32F0L0_USART3 +#ifdef CONFIG_STM32F0L0G0_USART3 # error not supported yet #endif -#ifdef CONFIG_STM32F0L0_USART4 +#ifdef CONFIG_STM32F0L0G0_USART4 # error not supported yet #endif @@ -88,8 +88,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY 10 #endif #if defined(CONFIG_PM) # define PM_IDLE_DOMAIN 0 /* Revisit */ @@ -106,7 +106,7 @@ * See up_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -116,9 +116,9 @@ /* Warnings for potentially unsafe configuration combinations. */ -#if defined(CONFIG_STM32F0L0_FLOWCONTROL_BROKEN) && \ +#if defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) && \ !defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) -# error "CONFIG_STM32F0L0_FLOWCONTROL_BROKEN requires \ +# error "CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN requires \ CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled." #endif @@ -237,29 +237,29 @@ static const struct uart_ops_s g_uart_ops = /* Receive/Transmit buffers */ -#ifdef CONFIG_STM32F0L0_USART1 +#ifdef CONFIG_STM32F0L0G0_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; #endif -#ifdef CONFIG_STM32F0L0_USART2 +#ifdef CONFIG_STM32F0L0G0_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; #endif -#ifdef CONFIG_STM32F0L0_USART3 +#ifdef CONFIG_STM32F0L0G0_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; #endif -#ifdef CONFIG_STM32F0L0_USART4 +#ifdef CONFIG_STM32F0L0G0_USART4 static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; #endif /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32F0L0_USART1 +#ifdef CONFIG_STM32F0L0G0_USART1 static struct up_dev_s g_usart1priv = { .dev = @@ -313,7 +313,7 @@ static struct up_dev_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32F0L0_USART2 +#ifdef CONFIG_STM32F0L0G0_USART2 static struct up_dev_s g_usart2priv = { .dev = @@ -373,16 +373,16 @@ static struct up_dev_s g_usart2priv = static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] = { -#ifdef CONFIG_STM32F0L0_USART1 +#ifdef CONFIG_STM32F0L0G0_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32F0L0_USART2 +#ifdef CONFIG_STM32F0L0G0_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32F0L0_USART3 +#ifdef CONFIG_STM32F0L0G0_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32F0L0_USART4 +#ifdef CONFIG_STM32F0L0G0_USART4 [3] = &g_usart4priv #endif }; @@ -655,7 +655,7 @@ static void up_set_format(struct uart_dev_s *dev) regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ - !defined(CONFIG_STM32F0L0_FLOWCONTROL_BROKEN) + !defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -699,25 +699,25 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32F0L0_USART1 +#ifdef CONFIG_STM32F0L0G0_USART1 case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F0L0_USART2 +#ifdef CONFIG_STM32F0L0G0_USART2 case STM32_USART2_BASE: rcc_en = RCC_APB1ENR_USART2EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0_USART3 +#ifdef CONFIG_STM32F0L0G0_USART3 case STM32_USART3_BASE: rcc_en = RCC_APB1ENR_USART3EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0_USART4 +#ifdef CONFIG_STM32F0L0G0_USART4 case STM32_USART4_BASE: rcc_en = RCC_APB1ENR_USART4EN; regaddr = STM32_RCC_APB1ENR; @@ -782,7 +782,7 @@ static int up_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32F0L0_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1001,8 +1001,8 @@ static int up_interrupt(int irq, void *context, FAR void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1106,11 +1106,11 @@ static int up_interrupt(int irq, void *context, FAR void *arg) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif -#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT) +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK; @@ -1133,7 +1133,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F0L0_USART_SINGLEWIRE +#ifdef CONFIG_STM32F0L0G0_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -1274,8 +1274,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32F0L0_USART_BREAKS -# ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32F0L0G0_USART_BREAKS +# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -1481,7 +1481,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32F0L0_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -1856,7 +1856,7 @@ void up_serialinit(void) #if CONSOLE_USART > 0 (void)uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev); -#ifndef CONFIG_STM32F0L0_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -1880,7 +1880,7 @@ void up_serialinit(void) continue; } -#ifndef CONFIG_STM32F0L0_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32f0l0/stm32_spi.c b/arch/arm/src/stm32f0l0g0/stm32_spi.c similarity index 97% rename from arch/arm/src/stm32f0l0/stm32_spi.c rename to arch/arm/src/stm32f0l0g0/stm32_spi.c index 779ec0f62a..bd62655e19 100644 --- a/arch/arm/src/stm32f0l0/stm32_spi.c +++ b/arch/arm/src/stm32f0l0g0/stm32_spi.c @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/stm32_spi.c + * arch/arm/src/stm32f0l0g0/stm32_spi.c * copied from arch/arm/src/stm32 * * Copyright (C) 2009-2013, 2016 Gregory Nutt. All rights reserved. @@ -93,7 +93,7 @@ #include -#ifdef CONFIG_STM32F0L0_SPI +#ifdef CONFIG_STM32F0L0G0_SPI /************************************************************************************ * Pre-processor Definitions @@ -102,19 +102,19 @@ /* Configuration ********************************************************************/ /* SPI interrupts */ -#ifdef CONFIG_STM32F0L0_SPI_INTERRUPTS +#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32F0L0_SPI_INTERRUPTS) && defined(CONFIG_STM32F0L0_SPI_DMA) +#if defined(CONFIG_STM32F0L0G0_SPI_INTERRUPTS) && defined(CONFIG_STM32F0L0G0_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -148,10 +148,10 @@ struct stm32_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32F0L0_SPI_INTERRUPTS +#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -193,7 +193,7 @@ static inline bool spi_16bitmode(FAR struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA static void spi_dmarxwait(FAR struct stm32_spidev_s *priv); static void spi_dmatxwait(FAR struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(FAR struct stm32_spidev_s *priv); @@ -246,7 +246,7 @@ static int spi_pm_prepare(FAR struct pm_callback_s *cb, int domain, * Private Data ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI1 +#ifdef CONFIG_STM32F0L0G0_SPI1 static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, @@ -283,10 +283,10 @@ static struct stm32_spidev_s g_spi1dev = .spidev = { &g_spi1ops }, .spibase = STM32_SPI1_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F0L0_SPI_INTERRUPTS +#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA /* lines must be configured in board.h */ .rxch = DMACHAN_SPI1_RX, .txch = DMACHAN_SPI1_TX, @@ -297,7 +297,7 @@ static struct stm32_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32F0L0_SPI2 +#ifdef CONFIG_STM32F0L0G0_SPI2 static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, @@ -334,10 +334,10 @@ static struct stm32_spidev_s g_spi2dev = .spidev = { &g_spi2ops }, .spibase = STM32_SPI2_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32F0L0_SPI_INTERRUPTS +#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, #endif @@ -567,7 +567,7 @@ static inline bool spi_16bitmode(FAR struct stm32_spidev_s *priv) * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA static void spi_dmarxwait(FAR struct stm32_spidev_s *priv) { int ret; @@ -598,7 +598,7 @@ static void spi_dmarxwait(FAR struct stm32_spidev_s *priv) * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA static void spi_dmatxwait(FAR struct stm32_spidev_s *priv) { int ret; @@ -629,7 +629,7 @@ static void spi_dmatxwait(FAR struct stm32_spidev_s *priv) * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA static inline void spi_dmarxwakeup(FAR struct stm32_spidev_s *priv) { (void)nxsem_post(&priv->rxsem); @@ -644,7 +644,7 @@ static inline void spi_dmarxwakeup(FAR struct stm32_spidev_s *priv) * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA static inline void spi_dmatxwakeup(FAR struct stm32_spidev_s *priv) { (void)nxsem_post(&priv->txsem); @@ -659,7 +659,7 @@ static inline void spi_dmatxwakeup(FAR struct stm32_spidev_s *priv) * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)arg; @@ -679,7 +679,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)arg; @@ -699,7 +699,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA static void spi_dmarxsetup(FAR struct stm32_spidev_s *priv, FAR void *rxbuffer, FAR void *rxdummy, size_t nwords) { @@ -749,7 +749,7 @@ static void spi_dmarxsetup(FAR struct stm32_spidev_s *priv, FAR void *rxbuffer, * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA static void spi_dmatxsetup(FAR struct stm32_spidev_s *priv, FAR const void *txbuffer, FAR const void *txdummy, size_t nwords) { @@ -799,7 +799,7 @@ static void spi_dmatxsetup(FAR struct stm32_spidev_s *priv, FAR const void *txbu * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA static inline void spi_dmarxstart(FAR struct stm32_spidev_s *priv) { priv->rxresult = 0; @@ -815,7 +815,7 @@ static inline void spi_dmarxstart(FAR struct stm32_spidev_s *priv) * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA static inline void spi_dmatxstart(FAR struct stm32_spidev_s *priv) { priv->txresult = 0; @@ -1285,8 +1285,8 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) * ************************************************************************************/ -#if !defined(CONFIG_STM32F0L0_SPI_DMA) || defined(CONFIG_STM32F0L0_DMACAPABLE) -#if !defined(CONFIG_STM32F0L0_SPI_DMA) +#if !defined(CONFIG_STM32F0L0G0_SPI_DMA) || defined(CONFIG_STM32F0L0G0_DMACAPABLE) +#if !defined(CONFIG_STM32F0L0G0_SPI_DMA) static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, FAR void *rxbuffer, size_t nwords) #else @@ -1368,7 +1368,7 @@ static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuff } } } -#endif /* !CONFIG_STM32F0L0_SPI_DMA || CONFIG_STM32F0L0_DMACAPABLE */ +#endif /* !CONFIG_STM32F0L0G0_SPI_DMA || CONFIG_STM32F0L0G0_DMACAPABLE */ /**************************************************************************** * Name: spi_exchange (with DMA capability) @@ -1390,13 +1390,13 @@ static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuff * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, FAR void *rxbuffer, size_t nwords) { FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev; -#ifdef CONFIG_STM32F0L0_DMACAPABLE +#ifdef CONFIG_STM32F0L0G0_DMACAPABLE if ((txbuffer && !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) { @@ -1451,7 +1451,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, #endif } } -#endif /* CONFIG_STM32F0L0_SPI_DMA */ +#endif /* CONFIG_STM32F0L0G0_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1472,7 +1472,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(FAR struct spi_dev_s *dev) { -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -1691,7 +1691,7 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv) nxsem_init(&priv->exclsem, 0, 1); -#ifdef CONFIG_STM32F0L0_SPI_DMA +#ifdef CONFIG_STM32F0L0G0_SPI_DMA /* Initialize the SPI semaphores that is used to wait for DMA completion */ nxsem_init(&priv->rxsem, 0, 0); @@ -1756,7 +1756,7 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32F0L0_SPI1 +#ifdef CONFIG_STM32F0L0G0_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -1781,7 +1781,7 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F0L0_SPI2 +#ifdef CONFIG_STM32F0L0G0_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -1815,4 +1815,4 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus) return (FAR struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32F0L0_SPI */ +#endif /* CONFIG_STM32F0L0G0_SPI */ diff --git a/arch/arm/src/stm32f0l0/stm32_spi.h b/arch/arm/src/stm32f0l0g0/stm32_spi.h similarity index 97% rename from arch/arm/src/stm32f0l0/stm32_spi.h rename to arch/arm/src/stm32f0l0g0/stm32_spi.h index b9d84b82a3..5e0f5100a1 100644 --- a/arch/arm/src/stm32f0l0/stm32_spi.h +++ b/arch/arm/src/stm32f0l0g0/stm32_spi.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/stm32_spi.h + * arch/arm/src/stm32f0l0g0/stm32_spi.h * * Copyright (C) 2009, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -115,13 +115,13 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus); * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI1 +#ifdef CONFIG_STM32F0L0G0_SPI1 void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F0L0_SPI2 +#ifdef CONFIG_STM32F0L0G0_SPI2 void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); @@ -148,12 +148,12 @@ int stm32_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32F0L0_SPI1 +#ifdef CONFIG_STM32F0L0G0_SPI1 int stm32_spi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, FAR void *arg); #endif -#ifdef CONFIG_STM32F0L0_SPI2 +#ifdef CONFIG_STM32F0L0G0_SPI2 int stm32_spi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, FAR void *arg); #endif diff --git a/arch/arm/src/stm32f0l0/stm32_start.c b/arch/arm/src/stm32f0l0g0/stm32_start.c similarity index 99% rename from arch/arm/src/stm32f0l0/stm32_start.c rename to arch/arm/src/stm32f0l0g0/stm32_start.c index b2176ef187..457defaa5a 100644 --- a/arch/arm/src/stm32f0l0/stm32_start.c +++ b/arch/arm/src/stm32f0l0g0/stm32_start.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_start.c + * arch/arm/src/stm32f0l0g0/stm32_start.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/stm32f0l0/stm32_start.h b/arch/arm/src/stm32f0l0g0/stm32_start.h similarity index 93% rename from arch/arm/src/stm32f0l0/stm32_start.h rename to arch/arm/src/stm32f0l0g0/stm32_start.h index 73087cbe3f..e369231122 100644 --- a/arch/arm/src/stm32f0l0/stm32_start.h +++ b/arch/arm/src/stm32f0l0g0/stm32_start.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/stm32_start.h + * arch/arm/src/stm32f0l0g0/stm32_start.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_START_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_START_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H /************************************************************************************ * Included Files @@ -73,4 +73,4 @@ void stm32_boardinitialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_START_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_timerisr.c b/arch/arm/src/stm32f0l0g0/stm32_timerisr.c similarity index 96% rename from arch/arm/src/stm32f0l0/stm32_timerisr.c rename to arch/arm/src/stm32f0l0g0/stm32_timerisr.c index 0007fb4834..f4bddc4ef1 100644 --- a/arch/arm/src/stm32f0l0/stm32_timerisr.c +++ b/arch/arm/src/stm32f0l0g0/stm32_timerisr.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_timerisr.c + * arch/arm/src/stm32f0l0g0/stm32_timerisr.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -62,9 +62,9 @@ * (when CLKSOURCE = 0). ..." */ -#if defined(CONFIG_STM32F0L0_SYSTICK_CORECLK) +#if defined(CONFIG_STM32F0L0G0_SYSTICK_CORECLK) # define SYSTICK_CLOCK STM32_SYSCLK_FREQUENCY /* Core clock */ -#elif defined(CONFIG_STM32F0L0_SYSTICK_CORECLK_DIV16) +#elif defined(CONFIG_STM32F0L0G0_SYSTICK_CORECLK_DIV16) # define SYSTICK_CLOCK (STM32_SYSCLK_FREQUENCY / 16) /* Core clock divided by 16 */ #endif @@ -152,7 +152,7 @@ void arm_timer_initialize(void) * a divide-by-16 of the core clock (when CLKSOURCE = 0). ..." */ -#ifdef CONFIG_STM32F0L0_SYSTICK_CORECLK +#ifdef CONFIG_STM32F0L0G0_SYSTICK_CORECLK putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR); #else diff --git a/arch/arm/src/stm32f0l0/stm32_uart.h b/arch/arm/src/stm32f0l0g0/stm32_uart.h similarity index 60% rename from arch/arm/src/stm32f0l0/stm32_uart.h rename to arch/arm/src/stm32f0l0g0/stm32_uart.h index 823b2cdc46..ea83905a41 100644 --- a/arch/arm/src/stm32f0l0/stm32_uart.h +++ b/arch/arm/src/stm32f0l0g0/stm32_uart.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/stm32_uart.h + * arch/arm/src/stm32f0l0g0/stm32_uart.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H /************************************************************************************ * Included Files @@ -54,29 +54,29 @@ * device. */ -#if STM32_NUSART < 8 || !defined(CONFIG_STM32F0L0_HAVE_USART8) -# undef CONFIG_STM32F0L0_USART8 +#if STM32_NUSART < 8 || !defined(CONFIG_STM32F0L0G0_HAVE_USART8) +# undef CONFIG_STM32F0L0G0_USART8 #endif -#if STM32_NUSART < 7 || !defined(CONFIG_STM32F0L0_HAVE_USART7) -# undef CONFIG_STM32F0L0_USART7 +#if STM32_NUSART < 7 || !defined(CONFIG_STM32F0L0G0_HAVE_USART7) +# undef CONFIG_STM32F0L0G0_USART7 #endif -#if STM32_NUSART < 6 || !defined(CONFIG_STM32F0L0_HAVE_USART6) -# undef CONFIG_STM32F0L0_USART6 +#if STM32_NUSART < 6 || !defined(CONFIG_STM32F0L0G0_HAVE_USART6) +# undef CONFIG_STM32F0L0G0_USART6 #endif -#if STM32_NUSART < 5 || !defined(CONFIG_STM32F0L0_HAVE_USART5) -# undef CONFIG_STM32F0L0_USART5 +#if STM32_NUSART < 5 || !defined(CONFIG_STM32F0L0G0_HAVE_USART5) +# undef CONFIG_STM32F0L0G0_USART5 #endif -#if STM32_NUSART < 4 || !defined(CONFIG_STM32F0L0_HAVE_USART4) -# undef CONFIG_STM32F0L0_USART4 +#if STM32_NUSART < 4 || !defined(CONFIG_STM32F0L0G0_HAVE_USART4) +# undef CONFIG_STM32F0L0G0_USART4 #endif -#if STM32_NUSART < 3 || !defined(CONFIG_STM32F0L0_HAVE_USART3) -# undef CONFIG_STM32F0L0_USART3 +#if STM32_NUSART < 3 || !defined(CONFIG_STM32F0L0G0_HAVE_USART3) +# undef CONFIG_STM32F0L0G0_USART3 #endif #if STM32_NUSART < 2 -# undef CONFIG_STM32F0L0_USART2 +# undef CONFIG_STM32F0L0G0_USART2 #endif #if STM32_NUSART < 1 -# undef CONFIG_STM32F0L0_USART1 +# undef CONFIG_STM32F0L0G0_USART1 #endif /* USART 3-8 are multiplexed to the same interrupt. Current interrupt @@ -85,128 +85,128 @@ * issue in the future. */ -#if defined(CONFIG_STM32F0L0_USART3) -# undef CONFIG_STM32F0L0_USART4 -# undef CONFIG_STM32F0L0_USART5 -# undef CONFIG_STM32F0L0_USART6 -# undef CONFIG_STM32F0L0_USART7 -# undef CONFIG_STM32F0L0_USART8 -#elif defined(CONFIG_STM32F0L0_USART4) -# undef CONFIG_STM32F0L0_USART5 -# undef CONFIG_STM32F0L0_USART6 -# undef CONFIG_STM32F0L0_USART7 -# undef CONFIG_STM32F0L0_USART8 -#elif defined(CONFIG_STM32F0L0_USART5) -# undef CONFIG_STM32F0L0_USART6 -# undef CONFIG_STM32F0L0_USART7 -# undef CONFIG_STM32F0L0_USART8 -#elif defined(CONFIG_STM32F0L0_USART6) -# undef CONFIG_STM32F0L0_USART7 -# undef CONFIG_STM32F0L0_USART8 -#elif defined(CONFIG_STM32F0L0_USART7) -# undef CONFIG_STM32F0L0_USART8 +#if defined(CONFIG_STM32F0L0G0_USART3) +# undef CONFIG_STM32F0L0G0_USART4 +# undef CONFIG_STM32F0L0G0_USART5 +# undef CONFIG_STM32F0L0G0_USART6 +# undef CONFIG_STM32F0L0G0_USART7 +# undef CONFIG_STM32F0L0G0_USART8 +#elif defined(CONFIG_STM32F0L0G0_USART4) +# undef CONFIG_STM32F0L0G0_USART5 +# undef CONFIG_STM32F0L0G0_USART6 +# undef CONFIG_STM32F0L0G0_USART7 +# undef CONFIG_STM32F0L0G0_USART8 +#elif defined(CONFIG_STM32F0L0G0_USART5) +# undef CONFIG_STM32F0L0G0_USART6 +# undef CONFIG_STM32F0L0G0_USART7 +# undef CONFIG_STM32F0L0G0_USART8 +#elif defined(CONFIG_STM32F0L0G0_USART6) +# undef CONFIG_STM32F0L0G0_USART7 +# undef CONFIG_STM32F0L0G0_USART8 +#elif defined(CONFIG_STM32F0L0G0_USART7) +# undef CONFIG_STM32F0L0G0_USART8 #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32F0L0_USART1) || defined(CONFIG_STM32F0L0_USART2) || \ - defined(CONFIG_STM32F0L0_USART3) || defined(CONFIG_STM32F0L0_USART4) || \ - defined(CONFIG_STM32F0L0_USART5) || defined(CONFIG_STM32F0L0_USART6) || \ - defined(CONFIG_STM32F0L0_USART7) || defined(CONFIG_STM32F0L0_USART8) +#if defined(CONFIG_STM32F0L0G0_USART1) || defined(CONFIG_STM32F0L0G0_USART2) || \ + defined(CONFIG_STM32F0L0G0_USART3) || defined(CONFIG_STM32F0L0G0_USART4) || \ + defined(CONFIG_STM32F0L0G0_USART5) || defined(CONFIG_STM32F0L0G0_USART6) || \ + defined(CONFIG_STM32F0L0G0_USART7) || defined(CONFIG_STM32F0L0G0_USART8) # define HAVE_USART 1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32F0L0_USART1) -# undef CONFIG_STM32F0L0_USART1_SERIALDRIVER -# undef CONFIG_STM32F0L0_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0G0_USART1) +# undef CONFIG_STM32F0L0G0_USART1_SERIALDRIVER +# undef CONFIG_STM32F0L0G0_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0_USART2) -# undef CONFIG_STM32F0L0_USART2_SERIALDRIVER -# undef CONFIG_STM32F0L0_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0G0_USART2) +# undef CONFIG_STM32F0L0G0_USART2_SERIALDRIVER +# undef CONFIG_STM32F0L0G0_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0_USART3) -# undef CONFIG_STM32F0L0_USART3_SERIALDRIVER -# undef CONFIG_STM32F0L0_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0G0_USART3) +# undef CONFIG_STM32F0L0G0_USART3_SERIALDRIVER +# undef CONFIG_STM32F0L0G0_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0_USART4) -# undef CONFIG_STM32F0L0_USART4_SERIALDRIVER -# undef CONFIG_STM32F0L0_USART4_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0G0_USART4) +# undef CONFIG_STM32F0L0G0_USART4_SERIALDRIVER +# undef CONFIG_STM32F0L0G0_USART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0_USART5) -# undef CONFIG_STM32F0L0_USART5_SERIALDRIVER -# undef CONFIG_STM32F0L0_USART5_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0G0_USART5) +# undef CONFIG_STM32F0L0G0_USART5_SERIALDRIVER +# undef CONFIG_STM32F0L0G0_USART5_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0_USART6) -# undef CONFIG_STM32F0L0_USART6_SERIALDRIVER -# undef CONFIG_STM32F0L0_USART6_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0G0_USART6) +# undef CONFIG_STM32F0L0G0_USART6_SERIALDRIVER +# undef CONFIG_STM32F0L0G0_USART6_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0_USART7) -# undef CONFIG_STM32F0L0_USART7_SERIALDRIVER -# undef CONFIG_STM32F0L0_USART7_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0G0_USART7) +# undef CONFIG_STM32F0L0G0_USART7_SERIALDRIVER +# undef CONFIG_STM32F0L0G0_USART7_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0_USART8) -# undef CONFIG_STM32F0L0_USART8_SERIALDRIVER -# undef CONFIG_STM32F0L0_USART8_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0G0_USART8) +# undef CONFIG_STM32F0L0G0_USART8_SERIALDRIVER +# undef CONFIG_STM32F0L0G0_USART8_1WIREDRIVER #endif /* Check 1-Wire and U(S)ART conflicts */ -#if defined(CONFIG_STM32F0L0_USART1_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER) -# error Both CONFIG_STM32F0L0_USART1_1WIREDRIVER and CONFIG_STM32F0L0_USART1_SERIALDRIVER defined -# undef CONFIG_STM32F0L0_USART1_1WIREDRIVER +#if defined(CONFIG_STM32F0L0G0_USART1_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) +# error Both CONFIG_STM32F0L0G0_USART1_1WIREDRIVER and CONFIG_STM32F0L0G0_USART1_SERIALDRIVER defined +# undef CONFIG_STM32F0L0G0_USART1_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0_USART2_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER) -# error Both CONFIG_STM32F0L0_USART2_1WIREDRIVER and CONFIG_STM32F0L0_USART2_SERIALDRIVER defined -# undef CONFIG_STM32F0L0_USART2_1WIREDRIVER +#if defined(CONFIG_STM32F0L0G0_USART2_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) +# error Both CONFIG_STM32F0L0G0_USART2_1WIREDRIVER and CONFIG_STM32F0L0G0_USART2_SERIALDRIVER defined +# undef CONFIG_STM32F0L0G0_USART2_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0_USART3_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER) -# error Both CONFIG_STM32F0L0_USART3_1WIREDRIVER and CONFIG_STM32F0L0_USART3_SERIALDRIVER defined -# undef CONFIG_STM32F0L0_USART3_1WIREDRIVER +#if defined(CONFIG_STM32F0L0G0_USART3_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) +# error Both CONFIG_STM32F0L0G0_USART3_1WIREDRIVER and CONFIG_STM32F0L0G0_USART3_SERIALDRIVER defined +# undef CONFIG_STM32F0L0G0_USART3_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0_USART4_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER) -# error Both CONFIG_STM32F0L0_USART4_1WIREDRIVER and CONFIG_STM32F0L0_USART4_SERIALDRIVER defined -# undef CONFIG_STM32F0L0_USART4_1WIREDRIVER +#if defined(CONFIG_STM32F0L0G0_USART4_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) +# error Both CONFIG_STM32F0L0G0_USART4_1WIREDRIVER and CONFIG_STM32F0L0G0_USART4_SERIALDRIVER defined +# undef CONFIG_STM32F0L0G0_USART4_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0_USART5_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER) -# error Both CONFIG_STM32F0L0_USART5_1WIREDRIVER and CONFIG_STM32F0L0_USART5_SERIALDRIVER defined -# undef CONFIG_STM32F0L0_USART5_1WIREDRIVER +#if defined(CONFIG_STM32F0L0G0_USART5_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) +# error Both CONFIG_STM32F0L0G0_USART5_1WIREDRIVER and CONFIG_STM32F0L0G0_USART5_SERIALDRIVER defined +# undef CONFIG_STM32F0L0G0_USART5_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0_USART6_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER) -# error Both CONFIG_STM32F0L0_USART6_1WIREDRIVER and CONFIG_STM32F0L0_USART6_SERIALDRIVER defined -# undef CONFIG_STM32F0L0_USART6_1WIREDRIVER +#if defined(CONFIG_STM32F0L0G0_USART6_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) +# error Both CONFIG_STM32F0L0G0_USART6_1WIREDRIVER and CONFIG_STM32F0L0G0_USART6_SERIALDRIVER defined +# undef CONFIG_STM32F0L0G0_USART6_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0_USART7_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER) -# error Both CONFIG_STM32F0L0_USART7_1WIREDRIVER and CONFIG_STM32F0L0_USART7_SERIALDRIVER defined -# undef CONFIG_STM32F0L0_USART7_1WIREDRIVER +#if defined(CONFIG_STM32F0L0G0_USART7_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) +# error Both CONFIG_STM32F0L0G0_USART7_1WIREDRIVER and CONFIG_STM32F0L0G0_USART7_SERIALDRIVER defined +# undef CONFIG_STM32F0L0G0_USART7_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0_USART8_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER) -# error Both CONFIG_STM32F0L0_USART8_1WIREDRIVER and CONFIG_STM32F0L0_USART8_SERIALDRIVER defined -# undef CONFIG_STM32F0L0_USART8_1WIREDRIVER +#if defined(CONFIG_STM32F0L0G0_USART8_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) +# error Both CONFIG_STM32F0L0G0_USART8_1WIREDRIVER and CONFIG_STM32F0L0G0_USART8_SERIALDRIVER defined +# undef CONFIG_STM32F0L0G0_USART8_1WIREDRIVER #endif /* Is the serial driver enabled? */ -#if defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER) || \ - defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER) || \ - defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER) || \ - defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER) +#if defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) || \ + defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) || \ + defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) || \ + defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) # define HAVE_SERIALDRIVER 1 #endif /* Is the 1-Wire driver? */ -#if defined(CONFIG_STM32F0L0_USART1_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART2_1WIREDRIVER) || \ - defined(CONFIG_STM32F0L0_USART3_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART4_1WIREDRIVER) || \ - defined(CONFIG_STM32F0L0_USART5_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART6_1WIREDRIVER) || \ - defined(CONFIG_STM32F0L0_USART7_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART8_1WIREDRIVER) +#if defined(CONFIG_STM32F0L0G0_USART1_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART2_1WIREDRIVER) || \ + defined(CONFIG_STM32F0L0G0_USART3_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART4_1WIREDRIVER) || \ + defined(CONFIG_STM32F0L0G0_USART5_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART6_1WIREDRIVER) || \ + defined(CONFIG_STM32F0L0G0_USART7_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART8_1WIREDRIVER) # define HAVE_1WIREDRIVER 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE @@ -216,7 +216,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE @@ -226,7 +226,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE @@ -236,7 +236,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER) +#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -246,7 +246,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER) +#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -256,7 +256,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -266,7 +266,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER) +#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -277,7 +277,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER) +#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -315,35 +315,35 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32F0L0_USART1_SERIALDRIVER +#ifndef CONFIG_STM32F0L0G0_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32F0L0_USART2_SERIALDRIVER +#ifndef CONFIG_STM32F0L0G0_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32F0L0_USART3_SERIALDRIVER +#ifndef CONFIG_STM32F0L0G0_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32F0L0_USART4_SERIALDRIVER +#ifndef CONFIG_STM32F0L0G0_USART4_SERIALDRIVER # undef CONFIG_USART4_RXDMA #endif -#ifndef CONFIG_STM32F0L0_USART5_SERIALDRIVER +#ifndef CONFIG_STM32F0L0G0_USART5_SERIALDRIVER # undef CONFIG_USART5_RXDMA #endif -#ifndef CONFIG_STM32F0L0_USART6_SERIALDRIVER +#ifndef CONFIG_STM32F0L0G0_USART6_SERIALDRIVER # undef CONFIG_USART6_RXDMA #endif -#ifndef CONFIG_STM32F0L0_USART7_SERIALDRIVER +#ifndef CONFIG_STM32F0L0G0_USART7_SERIALDRIVER # undef CONFIG_USART7_RXDMA #endif -#ifndef CONFIG_STM32F0L0_USART8_SERIALDRIVER +#ifndef CONFIG_STM32F0L0G0_USART8_SERIALDRIVER # undef CONFIG_USART8_RXDMA #endif @@ -381,21 +381,21 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#if defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA) +#elif defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA) +#elif defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA) +#elif defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA) +#elif defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif @@ -460,4 +460,4 @@ void stm32_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_usbdev.c b/arch/arm/src/stm32f0l0g0/stm32_usbdev.c similarity index 99% rename from arch/arm/src/stm32f0l0/stm32_usbdev.c rename to arch/arm/src/stm32f0l0g0/stm32_usbdev.c index a3d5ff037a..be4eea7ff7 100644 --- a/arch/arm/src/stm32f0l0/stm32_usbdev.c +++ b/arch/arm/src/stm32f0l0g0/stm32_usbdev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_usbdev.c + * arch/arm/src/stm32f0l0g0/stm32_usbdev.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -66,7 +66,7 @@ #include "stm32_gpio.h" #include "stm32_usbdev.h" -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32F0L0_USB) +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32F0L0G0_USB) /**************************************************************************** * Pre-processor Definitions @@ -87,7 +87,7 @@ */ #ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32F0L0_USBDEV_REGDEBUG +# undef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG #endif /* Initial interrupt mask: Reset + Suspend + Correct Transfer */ @@ -370,7 +370,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG +#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); static void stm32_dumpep(int epno); @@ -631,7 +631,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = * Name: stm32_getreg ****************************************************************************/ -#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG +#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -689,7 +689,7 @@ static uint16_t stm32_getreg(uint32_t addr) * Name: stm32_putreg ****************************************************************************/ -#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG +#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -706,7 +706,7 @@ static void stm32_putreg(uint16_t val, uint32_t addr) * Name: stm32_dumpep ****************************************************************************/ -#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG +#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG static void stm32_dumpep(int epno) { uint32_t addr; @@ -3861,4 +3861,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32F0L0_USB */ +#endif /* CONFIG_USBDEV && CONFIG_STM32F0L0G0_USB */ diff --git a/arch/arm/src/stm32f0l0/stm32_usbdev.h b/arch/arm/src/stm32f0l0g0/stm32_usbdev.h similarity index 94% rename from arch/arm/src/stm32f0l0/stm32_usbdev.h rename to arch/arm/src/stm32f0l0g0/stm32_usbdev.h index fb3a48f44f..b034d5eb1b 100644 --- a/arch/arm/src/stm32f0l0/stm32_usbdev.h +++ b/arch/arm/src/stm32f0l0g0/stm32_usbdev.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0l0/stm32_usbdev.h + * arch/arm/src/stm32f0l0g0/stm32_usbdev.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H +#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H /************************************************************************************ * Included Files @@ -93,4 +93,4 @@ void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32f0l0/stm32f0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c similarity index 84% rename from arch/arm/src/stm32f0l0/stm32f0_rcc.c rename to arch/arm/src/stm32f0l0g0/stm32f0_rcc.c index fe34a2deb2..477fb6ad2d 100644 --- a/arch/arm/src/stm32f0l0/stm32f0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32f0_rcc.c + * arch/arm/src/stm32f0l0g0/stm32f0_rcc.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -59,7 +59,7 @@ /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32F0L0_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32F0L0G0_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CFGR3_CLK48_HSI48 # define STM32_USE_HSI48 # endif @@ -121,25 +121,25 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0_DMA1 +#ifdef CONFIG_STM32F0L0G0_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0_DMA2 +#ifdef CONFIG_STM32F0L0G0_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHBENR_DMA2EN; #endif -#ifdef CONFIG_STM32F0L0_CRC +#ifdef CONFIG_STM32F0L0G0_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0_TSC +#ifdef CONFIG_STM32F0L0G0_TSC /* TSC clock enable */ regval |= RCC_AHBENR_TSCEN; @@ -166,145 +166,145 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0_TIM2 +#ifdef CONFIG_STM32F0L0G0_TIM2 /* Timer 2 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_TIM2EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM3 +#ifdef CONFIG_STM32F0L0G0_TIM3 /* Timer 3 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_TIM3EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM4 +#ifdef CONFIG_STM32F0L0G0_TIM4 /* Timer 4 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_TIM4EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM6 +#ifdef CONFIG_STM32F0L0G0_TIM6 /* Timer 6 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_TIM6EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM7 +#ifdef CONFIG_STM32F0L0G0_TIM7 /* Timer 7 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_TIM7EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM14 +#ifdef CONFIG_STM32F0L0G0_TIM14 /* Timer 14 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_TIM14EN; #endif #endif -#ifdef CONFIG_STM32F0L0_WWDG +#ifdef CONFIG_STM32F0L0G0_WWDG /* Window Watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F0L0_SPI2 +#ifdef CONFIG_STM32F0L0G0_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0_USART2 +#ifdef CONFIG_STM32F0L0G0_USART2 /* USART 2 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_USART2EN; #endif #endif -#ifdef CONFIG_STM32F0L0_USART3 +#ifdef CONFIG_STM32F0L0G0_USART3 /* USART 3 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_USART3EN; #endif #endif -#ifdef CONFIG_STM32F0L0_USART4 +#ifdef CONFIG_STM32F0L0G0_USART4 /* USART 4 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_USART4EN; #endif #endif -#ifdef CONFIG_STM32F0L0_USART5 +#ifdef CONFIG_STM32F0L0G0_USART5 /* USART 5 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_USART5EN; #endif #endif -#ifdef CONFIG_STM32F0L0_I2C1 +#ifdef CONFIG_STM32F0L0G0_I2C1 /* I2C 1 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_I2C1EN; #endif #endif -#ifdef CONFIG_STM32F0L0_I2C2 +#ifdef CONFIG_STM32F0L0G0_I2C2 /* I2C 2 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_I2C2EN; #endif #endif -#ifdef CONFIG_STM32F0L0_USB +#ifdef CONFIG_STM32F0L0G0_USB /* USB clock enable */ regval |= RCC_APB1ENR_USBEN; #endif -#ifdef CONFIG_STM32F0L0_CAN1 +#ifdef CONFIG_STM32F0L0G0_CAN1 /* CAN1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F0L0_CRS +#ifdef CONFIG_STM32F0L0G0_CRS /* Clock recovery system clock enable */ regval |= RCC_APB1ENR_CRSEN; #endif -#ifdef CONFIG_STM32F0L0_PWR +#ifdef CONFIG_STM32F0L0G0_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; #endif -#ifdef CONFIG_STM32F0L0_DAC1 +#ifdef CONFIG_STM32F0L0G0_DAC1 /* DAC 1 interface clock enable */ regval |= RCC_APB1ENR_DAC1EN; #endif -#ifdef CONFIG_STM32F0L0_CEC +#ifdef CONFIG_STM32F0L0G0_CEC /* CEC interface clock enable */ regval |= RCC_APB1ENR_CECEN; @@ -331,84 +331,84 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0_SYSCFG +#ifdef CONFIG_STM32F0L0G0_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGCOMPEN; #endif -#ifdef CONFIG_STM32F0L0_USART6 +#ifdef CONFIG_STM32F0L0G0_USART6 /* USART 6 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_USART6EN; #endif #endif -#ifdef CONFIG_STM32F0L0_USART7 +#ifdef CONFIG_STM32F0L0G0_USART7 /* USART 7 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_USART7EN; #endif #endif -#ifdef CONFIG_STM32F0L0_USART8 +#ifdef CONFIG_STM32F0L0G0_USART8 /* USART 8 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_USART8EN; #endif #endif -#ifdef CONFIG_STM32F0L0_ADC1 +#ifdef CONFIG_STM32F0L0G0_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F0L0_TIM1 +#ifdef CONFIG_STM32F0L0G0_TIM1 /* Timer 1 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_TIM1EN; #endif #endif -#ifdef CONFIG_STM32F0L0_SPI1 +#ifdef CONFIG_STM32F0L0G0_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0_USART1 +#ifdef CONFIG_STM32F0L0G0_USART1 /* USART1 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_USART1EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM15 +#ifdef CONFIG_STM32F0L0G0_TIM15 /* Timer 15 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_TIM15EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM16 +#ifdef CONFIG_STM32F0L0G0_TIM16 /* Timer 16 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_TIM16EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM17 +#ifdef CONFIG_STM32F0L0G0_TIM17 /* Timer 17 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_TIM17EN; #endif #endif diff --git a/arch/arm/src/stm32f0l0/stm32g0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c similarity index 88% rename from arch/arm/src/stm32f0l0/stm32g0_rcc.c rename to arch/arm/src/stm32f0l0g0/stm32g0_rcc.c index 4b6d456fa1..3bfab43011 100644 --- a/arch/arm/src/stm32f0l0/stm32g0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32g0_rcc.c + * arch/arm/src/stm32f0l0g0/stm32g0_rcc.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -124,31 +124,31 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0_DMA1 +#ifdef CONFIG_STM32F0L0G0_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0_MIF +#ifdef CONFIG_STM32F0L0G0_MIF /* Memory interface clock enable */ regval |= RCC_AHBENR_MIFEN; #endif -#ifdef CONFIG_STM32F0L0_CRC +#ifdef CONFIG_STM32F0L0G0_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0_RNG +#ifdef CONFIG_STM32F0L0G0_RNG /* Random number generator clock enable */ regval |= RCC_AHBENR_RNGEN; #endif -#ifdef CONFIG_STM32F0L0_AES +#ifdef CONFIG_STM32F0L0G0_AES /* AES modules clock enable */ regval |= RCC_AHBENR_AESEN; @@ -175,110 +175,110 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0_TIM2 +#ifdef CONFIG_STM32F0L0G0_TIM2 /* Timer 2 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_TIM2EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM3 +#ifdef CONFIG_STM32F0L0G0_TIM3 /* Timer 3 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_TIM3EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM6 +#ifdef CONFIG_STM32F0L0G0_TIM6 /* Timer 6 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_TIM6EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM7 +#ifdef CONFIG_STM32F0L0G0_TIM7 /* Timer 7 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_TIM7EN; #endif #endif -#ifdef CONFIG_STM32F0L0_SPI2 +#ifdef CONFIG_STM32F0L0G0_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0_USART2 +#ifdef CONFIG_STM32F0L0G0_USART2 /* USART 2 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_USART2EN; #endif #endif -#ifdef CONFIG_STM32F0L0_USART3 +#ifdef CONFIG_STM32F0L0G0_USART3 /* USART 3 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_USART3EN; #endif #endif -#ifdef CONFIG_STM32F0L0_USART4 +#ifdef CONFIG_STM32F0L0G0_USART4 /* USART 4 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_USART4EN; #endif #endif -#ifdef CONFIG_STM32F0L0_LPUSART1 +#ifdef CONFIG_STM32F0L0G0_LPUSART1 /* USART 5 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_LPUSART1EN; #endif #endif -#ifdef CONFIG_STM32F0L0_I2C1 +#ifdef CONFIG_STM32F0L0G0_I2C1 /* I2C 1 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_I2C1EN; #endif #endif -#ifdef CONFIG_STM32F0L0_I2C2 +#ifdef CONFIG_STM32F0L0G0_I2C2 /* I2C 2 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_I2C2EN; #endif #endif -#ifdef CONFIG_STM32F0L0_PWR +#ifdef CONFIG_STM32F0L0G0_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; #endif -#ifdef CONFIG_STM32F0L0_DAC1 +#ifdef CONFIG_STM32F0L0G0_DAC1 /* DAC 1 interface clock enable */ regval |= RCC_APB1ENR_DAC1EN; #endif -#ifdef CONFIG_STM32F0L0_LPTIM1 +#ifdef CONFIG_STM32F0L0G0_LPTIM1 /* LPTIM1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F0L0_LPTIM2 +#ifdef CONFIG_STM32F0L0G0_LPTIM2 /* LPTIM2 clock enable */ regval |= RCC_APB1ENR_LPTIM2EN; @@ -305,67 +305,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0_SYSCFG +#ifdef CONFIG_STM32F0L0G0_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32F0L0_TIM1 +#ifdef CONFIG_STM32F0L0G0_TIM1 /* TIM1 Timer clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_TIM1EN; #endif #endif -#ifdef CONFIG_STM32F0L0_SPI1 +#ifdef CONFIG_STM32F0L0G0_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0_USART1 +#ifdef CONFIG_STM32F0L0G0_USART1 /* USART1 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_USART1EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM14 +#ifdef CONFIG_STM32F0L0G0_TIM14 /* TIM14 Timer clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_TIM14EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM15 +#ifdef CONFIG_STM32F0L0G0_TIM15 /* TIM5 Timer clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_TIM15EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM16 +#ifdef CONFIG_STM32F0L0G0_TIM16 /* TIM16 Timer clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_TIM16EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM17 +#ifdef CONFIG_STM32F0L0G0_TIM17 /* TIM17 Timer clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_TIM17EN; #endif #endif -#ifdef CONFIG_STM32F0L0_ADC1 +#ifdef CONFIG_STM32F0L0G0_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; @@ -436,7 +436,7 @@ static inline bool stm32_rcc_enablehse(void) static void stm32_stdclockconfig(void) { uint32_t regval; -#if defined(CONFIG_STM32F0L0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) uint16_t pwrcr; #endif uint32_t pwr_vos; @@ -451,7 +451,7 @@ static void stm32_stdclockconfig(void) #warning TODO: configure VOS range UNUSED(pwr_vos); -#if defined(CONFIG_STM32F0L0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) /* If RTC / LCD selects HSE as clock source, the RTC prescaler * needs to be set before HSEON bit is set. */ @@ -574,8 +574,8 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#if defined(CONFIG_STM32F0L0_IWDG) || \ - defined(CONFIG_STM32F0L0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) +#if defined(CONFIG_STM32F0L0G0_IWDG) || \ + defined(CONFIG_STM32F0L0G0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) /* Low speed internal clock source LSI * * TODO: There is another case where the LSI needs to @@ -586,7 +586,7 @@ static void stm32_stdclockconfig(void) #endif -#if defined(CONFIG_STM32F0L0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) +#if defined(CONFIG_STM32F0L0G0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32f0l0/stm32l0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c similarity index 90% rename from arch/arm/src/stm32f0l0/stm32l0_rcc.c rename to arch/arm/src/stm32f0l0g0/stm32l0_rcc.c index 34302531f5..1d15e6f241 100644 --- a/arch/arm/src/stm32f0l0/stm32l0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0/stm32l0_rcc.c + * arch/arm/src/stm32f0l0g0/stm32l0_rcc.c * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -59,10 +59,10 @@ /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32F0L0_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32F0L0G0_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 # define STM32_USE_HSI48 -# ifndef CONFIG_STM32F0L0_VREFINT +# ifndef CONFIG_STM32F0L0G0_VREFINT # error VREFINT must be enabled if HSI48 used # endif # endif @@ -141,31 +141,31 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0_DMA1 +#ifdef CONFIG_STM32F0L0G0_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0_MIF +#ifdef CONFIG_STM32F0L0G0_MIF /* Memory interface clock enable */ regval |= RCC_AHBENR_MIFEN; #endif -#ifdef CONFIG_STM32F0L0_CRC +#ifdef CONFIG_STM32F0L0G0_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0_TSC +#ifdef CONFIG_STM32F0L0G0_TSC /* TSC clock enable */ regval |= RCC_AHBENR_TSCEN; #endif -#ifdef CONFIG_STM32F0L0_RNG +#ifdef CONFIG_STM32F0L0G0_RNG /* Random number generator clock enable */ regval |= RCC_AHBENR_RNGEN; @@ -192,137 +192,137 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0_TIM2 +#ifdef CONFIG_STM32F0L0G0_TIM2 /* Timer 2 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_TIM2EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM3 +#ifdef CONFIG_STM32F0L0G0_TIM3 /* Timer 3 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_TIM3EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM6 +#ifdef CONFIG_STM32F0L0G0_TIM6 /* Timer 6 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_TIM6EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM7 +#ifdef CONFIG_STM32F0L0G0_TIM7 /* Timer 7 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_TIM7EN; #endif #endif -#ifdef CONFIG_STM32F0L0_LCD +#ifdef CONFIG_STM32F0L0G0_LCD /* LCD clock enable */ regval |= RCC_APB1ENR_LCDEN; #endif -#ifdef CONFIG_STM32F0L0_WWDG +#ifdef CONFIG_STM32F0L0G0_WWDG /* Window Watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F0L0_SPI2 +#ifdef CONFIG_STM32F0L0G0_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0_USART2 +#ifdef CONFIG_STM32F0L0G0_USART2 /* USART 2 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_USART2EN; #endif #endif -#ifdef CONFIG_STM32F0L0_USART3 +#ifdef CONFIG_STM32F0L0G0_USART3 /* USART 3 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_USART3EN; #endif #endif -#ifdef CONFIG_STM32F0L0_USART4 +#ifdef CONFIG_STM32F0L0G0_USART4 /* USART 4 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_USART4EN; #endif #endif -#ifdef CONFIG_STM32F0L0_USART5 +#ifdef CONFIG_STM32F0L0G0_USART5 /* USART 5 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_USART5EN; #endif #endif -#ifdef CONFIG_STM32F0L0_I2C1 +#ifdef CONFIG_STM32F0L0G0_I2C1 /* I2C 1 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_I2C1EN; #endif #endif -#ifdef CONFIG_STM32F0L0_I2C2 +#ifdef CONFIG_STM32F0L0G0_I2C2 /* I2C 2 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_I2C2EN; #endif #endif -#ifdef CONFIG_STM32F0L0_USB +#ifdef CONFIG_STM32F0L0G0_USB /* USB clock enable */ regval |= RCC_APB1ENR_USBEN; #endif -#ifdef CONFIG_STM32F0L0_CRS +#ifdef CONFIG_STM32F0L0G0_CRS /* Clock recovery system clock enable */ regval |= RCC_APB1ENR_CRSEN; #endif -#ifdef CONFIG_STM32F0L0_PWR +#ifdef CONFIG_STM32F0L0G0_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; #endif -#ifdef CONFIG_STM32F0L0_DAC1 +#ifdef CONFIG_STM32F0L0G0_DAC1 /* DAC 1 interface clock enable */ regval |= RCC_APB1ENR_DAC1EN; #endif -#ifdef CONFIG_STM32F0L0_I2C3 +#ifdef CONFIG_STM32F0L0G0_I2C3 /* I2C 3 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB1ENR_I2C4EN; #endif #endif -#ifdef CONFIG_STM32F0L0_LPTIM1 +#ifdef CONFIG_STM32F0L0G0_LPTIM1 /* LPTIM1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; @@ -349,44 +349,44 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0_SYSCFG +#ifdef CONFIG_STM32F0L0G0_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32F0L0_TIM21 +#ifdef CONFIG_STM32F0L0G0_TIM21 /* TIM21 Timer clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_TIM21EN; #endif #endif -#ifdef CONFIG_STM32F0L0_TIM22 +#ifdef CONFIG_STM32F0L0G0_TIM22 /* TIM22 Timer clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_TIM10EN; #endif #endif -#ifdef CONFIG_STM32F0L0_ADC1 +#ifdef CONFIG_STM32F0L0G0_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F0L0_SPI1 +#ifdef CONFIG_STM32F0L0G0_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0_USART1 +#ifdef CONFIG_STM32F0L0G0_USART1 /* USART1 clock enable */ -#ifdef CONFIG_STM32F0L0_FORCEPOWER +#ifdef CONFIG_STM32F0L0G0_FORCEPOWER regval |= RCC_APB2ENR_USART1EN; #endif #endif @@ -488,7 +488,7 @@ static inline bool stm32_rcc_enablehse(void) static void stm32_stdclockconfig(void) { uint32_t regval; -#if defined(CONFIG_STM32F0L0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) uint16_t pwrcr; #endif uint32_t pwr_vos; @@ -539,7 +539,7 @@ static void stm32_stdclockconfig(void) stm32_pwr_setvos(pwr_vos); -#if defined(CONFIG_STM32F0L0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) /* If RTC / LCD selects HSE as clock source, the RTC prescaler * needs to be set before HSEON bit is set. */ @@ -717,8 +717,8 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#if defined(CONFIG_STM32F0L0_IWDG) || \ - defined(CONFIG_STM32F0L0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) +#if defined(CONFIG_STM32F0L0G0_IWDG) || \ + defined(CONFIG_STM32F0L0G0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) /* Low speed internal clock source LSI * * TODO: There is another case where the LSI needs to @@ -729,7 +729,7 @@ static void stm32_stdclockconfig(void) #endif -#if defined(CONFIG_STM32F0L0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) +#if defined(CONFIG_STM32F0L0G0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -757,7 +757,7 @@ static void stm32_stdclockconfig(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0_VREFINT +#ifdef CONFIG_STM32F0L0G0_VREFINT static void vrefint_enable(void) { uint32_t regval = 0; @@ -794,7 +794,7 @@ static inline void rcc_enableperipherals(void) rcc_enableahb(); rcc_enableapb2(); rcc_enableapb1(); -#ifdef CONFIG_STM32F0L0_VREFINT +#ifdef CONFIG_STM32F0L0G0_VREFINT vrefint_enable(); #endif diff --git a/configs/b-l072z-lrwan1/adc/defconfig b/configs/b-l072z-lrwan1/adc/defconfig index 25f41d9bf8..6c5aa20f72 100644 --- a/configs/b-l072z-lrwan1/adc/defconfig +++ b/configs/b-l072z-lrwan1/adc/defconfig @@ -52,11 +52,11 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0_ADC1=y -CONFIG_STM32F0L0_ADC1_DMA=y -CONFIG_STM32F0L0_DMA1=y -CONFIG_STM32F0L0_PWR=y -CONFIG_STM32F0L0_USART2=y +CONFIG_STM32F0L0G0_ADC1=y +CONFIG_STM32F0L0G0_ADC1_DMA=y +CONFIG_STM32F0L0G0_DMA1=y +CONFIG_STM32F0L0G0_PWR=y +CONFIG_STM32F0L0G0_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 diff --git a/configs/b-l072z-lrwan1/include/board.h b/configs/b-l072z-lrwan1/include/board.h index 0e093532b1..73d7fee954 100644 --- a/configs/b-l072z-lrwan1/include/board.h +++ b/configs/b-l072z-lrwan1/include/board.h @@ -100,7 +100,7 @@ /* 48MHz clock configuration */ -#if defined(CONFIG_STM32F0L0_USB) || defined(CONFIG_STM32F0L0_RNG) +#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE diff --git a/configs/b-l072z-lrwan1/nsh/defconfig b/configs/b-l072z-lrwan1/nsh/defconfig index ba659d1cbe..1889cfb3e4 100644 --- a/configs/b-l072z-lrwan1/nsh/defconfig +++ b/configs/b-l072z-lrwan1/nsh/defconfig @@ -47,8 +47,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0_PWR=y -CONFIG_STM32F0L0_USART2=y +CONFIG_STM32F0L0G0_PWR=y +CONFIG_STM32F0L0G0_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 diff --git a/configs/b-l072z-lrwan1/nxlines_oled/defconfig b/configs/b-l072z-lrwan1/nxlines_oled/defconfig index e0553e10d9..8eea9cc24a 100644 --- a/configs/b-l072z-lrwan1/nxlines_oled/defconfig +++ b/configs/b-l072z-lrwan1/nxlines_oled/defconfig @@ -59,9 +59,9 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0_I2C1=y -CONFIG_STM32F0L0_PWR=y -CONFIG_STM32F0L0_USART2=y +CONFIG_STM32F0L0G0_I2C1=y +CONFIG_STM32F0L0G0_PWR=y +CONFIG_STM32F0L0G0_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=1024 CONFIG_TASK_NAME_SIZE=0 diff --git a/configs/b-l072z-lrwan1/src/Makefile b/configs/b-l072z-lrwan1/src/Makefile index 31ab0fd412..246c7eec06 100644 --- a/configs/b-l072z-lrwan1/src/Makefile +++ b/configs/b-l072z-lrwan1/src/Makefile @@ -48,7 +48,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0_SPI),y) +ifeq ($(CONFIG_STM32F0L0G0_SPI),y) CSRCS += stm32_spi.c endif diff --git a/configs/b-l072z-lrwan1/src/b-l072z-lrwan1.h b/configs/b-l072z-lrwan1/src/b-l072z-lrwan1.h index 3c861c2d0c..19ea9565c0 100644 --- a/configs/b-l072z-lrwan1/src/b-l072z-lrwan1.h +++ b/configs/b-l072z-lrwan1/src/b-l072z-lrwan1.h @@ -150,7 +150,7 @@ int stm32_bringup(void); * ************************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI +#ifdef CONFIG_STM32F0L0G0_SPI void stm32_spidev_initialize(void); #endif diff --git a/configs/b-l072z-lrwan1/src/stm32_adc.c b/configs/b-l072z-lrwan1/src/stm32_adc.c index 4fe1261066..b7a6b657d6 100644 --- a/configs/b-l072z-lrwan1/src/stm32_adc.c +++ b/configs/b-l072z-lrwan1/src/stm32_adc.c @@ -48,7 +48,7 @@ #include "stm32.h" -#if defined(CONFIG_ADC) && defined(CONFIG_STM32F0L0_ADC1) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32F0L0G0_ADC1) /**************************************************************************** * Pre-processor Definitions @@ -142,4 +142,4 @@ int stm32_adc_setup(void) return OK; } -#endif /* CONFIG_ADC && CONFIG_STM32F0L0_ADC1 */ +#endif /* CONFIG_ADC && CONFIG_STM32F0L0G0_ADC1 */ diff --git a/configs/b-l072z-lrwan1/src/stm32_boot.c b/configs/b-l072z-lrwan1/src/stm32_boot.c index 6c3a45d462..91dd57707a 100644 --- a/configs/b-l072z-lrwan1/src/stm32_boot.c +++ b/configs/b-l072z-lrwan1/src/stm32_boot.c @@ -84,7 +84,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0_SPI +#ifdef CONFIG_STM32F0L0G0_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/configs/b-l072z-lrwan1/src/stm32_bringup.c b/configs/b-l072z-lrwan1/src/stm32_bringup.c index 0764d56d45..65d12f6ab0 100644 --- a/configs/b-l072z-lrwan1/src/stm32_bringup.c +++ b/configs/b-l072z-lrwan1/src/stm32_bringup.c @@ -110,13 +110,13 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32F0L0_I2C1 +#ifdef CONFIG_STM32F0L0G0_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32F0L0_I2C2 +#ifdef CONFIG_STM32F0L0G0_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32F0L0_I2C3 +#ifdef CONFIG_STM32F0L0G0_I2C3 stm32_i2c_register(3); #endif } diff --git a/configs/b-l072z-lrwan1/src/stm32_spi.c b/configs/b-l072z-lrwan1/src/stm32_spi.c index 4cdc1de26a..11ea02946a 100644 --- a/configs/b-l072z-lrwan1/src/stm32_spi.c +++ b/configs/b-l072z-lrwan1/src/stm32_spi.c @@ -54,7 +54,7 @@ #include "b-l072z-lrwan1.h" #include -#ifdef CONFIG_STM32F0L0_SPI +#ifdef CONFIG_STM32F0L0G0_SPI /**************************************************************************** * Pre-processor Definitions @@ -92,7 +92,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32F0L0_SPI1 +#ifdef CONFIG_STM32F0L0G0_SPI1 # ifdef CONFIG_LPWAN_SX127X /* Configure the SPI-based SX127X chip select GPIO */ @@ -130,7 +130,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI1 +#ifdef CONFIG_STM32F0L0G0_SPI1 void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -177,9 +177,9 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) return status; } -#endif /* CONFIG_STM32F0L0_SPI1 */ +#endif /* CONFIG_STM32F0L0G0_SPI1 */ -#ifdef CONFIG_STM32F0L0_SPI2 +#ifdef CONFIG_STM32F0L0G0_SPI2 void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -190,7 +190,7 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) { return 0; } -#endif /* CONFIG_STM32F0L0_SPI2 */ +#endif /* CONFIG_STM32F0L0G0_SPI2 */ -#endif /* CONFIG_STM32F0L0_SPI */ +#endif /* CONFIG_STM32F0L0G0_SPI */ diff --git a/configs/b-l072z-lrwan1/sx127x/defconfig b/configs/b-l072z-lrwan1/sx127x/defconfig index 1e219bd15f..65e839cd12 100644 --- a/configs/b-l072z-lrwan1/sx127x/defconfig +++ b/configs/b-l072z-lrwan1/sx127x/defconfig @@ -57,9 +57,9 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0_PWR=y -CONFIG_STM32F0L0_SPI1=y -CONFIG_STM32F0L0_USART2=y +CONFIG_STM32F0L0G0_PWR=y +CONFIG_STM32F0L0G0_SPI1=y +CONFIG_STM32F0L0G0_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 diff --git a/configs/nucleo-f072rb/include/board.h b/configs/nucleo-f072rb/include/board.h index 873e0cce0b..8a36398164 100644 --- a/configs/nucleo-f072rb/include/board.h +++ b/configs/nucleo-f072rb/include/board.h @@ -113,7 +113,7 @@ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ #define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0_USB +#ifdef CONFIG_STM32F0L0G0_USB # undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ # define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ @@ -129,7 +129,7 @@ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0_USB +#ifdef CONFIG_STM32F0L0G0_USB # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ diff --git a/configs/nucleo-f072rb/nsh/defconfig b/configs/nucleo-f072rb/nsh/defconfig index 299b042f6c..3cdb7e5063 100644 --- a/configs/nucleo-f072rb/nsh/defconfig +++ b/configs/nucleo-f072rb/nsh/defconfig @@ -54,8 +54,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0_PWR=y -CONFIG_STM32F0L0_USART2=y +CONFIG_STM32F0L0G0_PWR=y +CONFIG_STM32F0L0G0_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 diff --git a/configs/nucleo-f072rb/src/nucleo-f072rb.h b/configs/nucleo-f072rb/src/nucleo-f072rb.h index 03eae5d48a..7197480355 100644 --- a/configs/nucleo-f072rb/src/nucleo-f072rb.h +++ b/configs/nucleo-f072rb/src/nucleo-f072rb.h @@ -55,14 +55,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0_SPI1 -# undef CONFIG_STM32F0L0_SPI2 -# undef CONFIG_STM32F0L0_SPI3 +# undef CONFIG_STM32F0L0G0_SPI1 +# undef CONFIG_STM32F0L0G0_SPI2 +# undef CONFIG_STM32F0L0G0_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0_SPI2 -# undef CONFIG_STM32F0L0_SPI3 +# undef CONFIG_STM32F0L0G0_SPI2 +# undef CONFIG_STM32F0L0G0_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0_SPI3 +# undef CONFIG_STM32F0L0G0_SPI3 #endif /* Nucleo-F072RB GPIOs ******************************************************/ diff --git a/configs/nucleo-f072rb/src/stm32_bringup.c b/configs/nucleo-f072rb/src/stm32_bringup.c index bfaa991e0a..e3d4f24670 100644 --- a/configs/nucleo-f072rb/src/stm32_bringup.c +++ b/configs/nucleo-f072rb/src/stm32_bringup.c @@ -53,7 +53,7 @@ ****************************************************************************/ #undef HAVE_I2C_DRIVER -#if defined(CONFIG_STM32F0L0_I2C1) && defined(CONFIG_I2C_DRIVER) +#if defined(CONFIG_STM32F0L0G0_I2C1) && defined(CONFIG_I2C_DRIVER) # define HAVE_I2C_DRIVER 1 #endif diff --git a/configs/nucleo-f091rc/include/board.h b/configs/nucleo-f091rc/include/board.h index 02fea16229..2cf25a579f 100644 --- a/configs/nucleo-f091rc/include/board.h +++ b/configs/nucleo-f091rc/include/board.h @@ -113,7 +113,7 @@ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ #define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0_USB +#ifdef CONFIG_STM32F0L0G0_USB # undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ # define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ @@ -129,7 +129,7 @@ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0_USB +#ifdef CONFIG_STM32F0L0G0_USB # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ diff --git a/configs/nucleo-f091rc/nsh/defconfig b/configs/nucleo-f091rc/nsh/defconfig index d2ab77af89..c168d81cac 100644 --- a/configs/nucleo-f091rc/nsh/defconfig +++ b/configs/nucleo-f091rc/nsh/defconfig @@ -57,8 +57,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0_PWR=y -CONFIG_STM32F0L0_USART2=y +CONFIG_STM32F0L0G0_PWR=y +CONFIG_STM32F0L0G0_USART2=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/configs/nucleo-f091rc/src/Makefile b/configs/nucleo-f091rc/src/Makefile index 31f84b485a..0028d08be6 100644 --- a/configs/nucleo-f091rc/src/Makefile +++ b/configs/nucleo-f091rc/src/Makefile @@ -49,7 +49,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0_SPI),y) +ifeq ($(CONFIG_STM32F0L0G0_SPI),y) CSRCS += stm32_spi.c endif diff --git a/configs/nucleo-f091rc/src/nucleo-f091rc.h b/configs/nucleo-f091rc/src/nucleo-f091rc.h index ad7279f4c3..30418e4271 100644 --- a/configs/nucleo-f091rc/src/nucleo-f091rc.h +++ b/configs/nucleo-f091rc/src/nucleo-f091rc.h @@ -55,14 +55,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0_SPI1 -# undef CONFIG_STM32F0L0_SPI2 -# undef CONFIG_STM32F0L0_SPI3 +# undef CONFIG_STM32F0L0G0_SPI1 +# undef CONFIG_STM32F0L0G0_SPI2 +# undef CONFIG_STM32F0L0G0_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0_SPI2 -# undef CONFIG_STM32F0L0_SPI3 +# undef CONFIG_STM32F0L0G0_SPI2 +# undef CONFIG_STM32F0L0G0_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0_SPI3 +# undef CONFIG_STM32F0L0G0_SPI3 #endif /* Nucleo-F091RC GPIOs ******************************************************/ @@ -139,7 +139,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI +#ifdef CONFIG_STM32F0L0G0_SPI void stm32_spidev_initialize(void); #endif diff --git a/configs/nucleo-f091rc/src/stm32_boot.c b/configs/nucleo-f091rc/src/stm32_boot.c index 80f4deee82..d54e17d57a 100644 --- a/configs/nucleo-f091rc/src/stm32_boot.c +++ b/configs/nucleo-f091rc/src/stm32_boot.c @@ -70,7 +70,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0_SPI +#ifdef CONFIG_STM32F0L0G0_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/configs/nucleo-f091rc/src/stm32_spi.c b/configs/nucleo-f091rc/src/stm32_spi.c index cbfac40aa2..fcd965ef0d 100644 --- a/configs/nucleo-f091rc/src/stm32_spi.c +++ b/configs/nucleo-f091rc/src/stm32_spi.c @@ -54,7 +54,7 @@ #include "nucleo-f091rc.h" #include -#ifdef CONFIG_STM32F0L0_SPI +#ifdef CONFIG_STM32F0L0G0_SPI /**************************************************************************** * Pre-processor Definitions @@ -92,7 +92,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32F0L0_SPI1 +#ifdef CONFIG_STM32F0L0G0_SPI1 # ifdef CONFIG_LPWAN_SX127X /* Configure the SPI-based SX127X chip select GPIO */ @@ -103,7 +103,7 @@ void stm32_spidev_initialize(void) stm32_gpiowrite(GPIO_SX127X_CS, true); # endif -#endif /* CONFIG_STM32F0L0_SPI1 */ +#endif /* CONFIG_STM32F0L0G0_SPI1 */ } /**************************************************************************** @@ -132,7 +132,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI1 +#ifdef CONFIG_STM32F0L0G0_SPI1 void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); @@ -178,9 +178,9 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) return status; } -#endif /* CONFIG_STM32F0L0_SPI1 */ +#endif /* CONFIG_STM32F0L0G0_SPI1 */ -#ifdef CONFIG_STM32F0L0_SPI2 +#ifdef CONFIG_STM32F0L0G0_SPI2 void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -191,6 +191,6 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) { return 0; } -#endif /* CONFIG_STM32F0L0_SPI2 */ +#endif /* CONFIG_STM32F0L0G0_SPI2 */ #endif diff --git a/configs/nucleo-f091rc/sx127x/defconfig b/configs/nucleo-f091rc/sx127x/defconfig index 7a35b39b09..832ceae063 100644 --- a/configs/nucleo-f091rc/sx127x/defconfig +++ b/configs/nucleo-f091rc/sx127x/defconfig @@ -59,9 +59,9 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0_PWR=y -CONFIG_STM32F0L0_SPI1=y -CONFIG_STM32F0L0_USART2=y +CONFIG_STM32F0L0G0_PWR=y +CONFIG_STM32F0L0G0_SPI1=y +CONFIG_STM32F0L0G0_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 diff --git a/configs/nucleo-g071rb/nsh/defconfig b/configs/nucleo-g071rb/nsh/defconfig index c6c32b44ec..ea3f5afb48 100644 --- a/configs/nucleo-g071rb/nsh/defconfig +++ b/configs/nucleo-g071rb/nsh/defconfig @@ -48,7 +48,7 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0_USART2=y +CONFIG_STM32F0L0G0_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 diff --git a/configs/nucleo-g071rb/src/stm32_boot.c b/configs/nucleo-g071rb/src/stm32_boot.c index 3e05a66e03..b524411536 100644 --- a/configs/nucleo-g071rb/src/stm32_boot.c +++ b/configs/nucleo-g071rb/src/stm32_boot.c @@ -67,7 +67,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0_SPI +#ifdef CONFIG_STM32F0L0G0_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/configs/nucleo-l073rz/include/board.h b/configs/nucleo-l073rz/include/board.h index 9c268d241b..844e2373f9 100644 --- a/configs/nucleo-l073rz/include/board.h +++ b/configs/nucleo-l073rz/include/board.h @@ -101,7 +101,7 @@ /* 48MHz clock configuration */ -#if defined(CONFIG_STM32F0L0_USB) || defined(CONFIG_STM32F0L0_RNG) +#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE diff --git a/configs/nucleo-l073rz/nsh/defconfig b/configs/nucleo-l073rz/nsh/defconfig index 613c9c8678..eb2a814fe4 100644 --- a/configs/nucleo-l073rz/nsh/defconfig +++ b/configs/nucleo-l073rz/nsh/defconfig @@ -47,8 +47,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0_PWR=y -CONFIG_STM32F0L0_USART2=y +CONFIG_STM32F0L0G0_PWR=y +CONFIG_STM32F0L0G0_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 diff --git a/configs/nucleo-l073rz/src/Makefile b/configs/nucleo-l073rz/src/Makefile index eb04a71a45..908bf72df8 100644 --- a/configs/nucleo-l073rz/src/Makefile +++ b/configs/nucleo-l073rz/src/Makefile @@ -48,7 +48,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0_SPI),y) +ifeq ($(CONFIG_STM32F0L0G0_SPI),y) CSRCS += stm32_spi.c endif diff --git a/configs/nucleo-l073rz/src/nucleo-l073rz.h b/configs/nucleo-l073rz/src/nucleo-l073rz.h index c770ad0c50..92506d5124 100644 --- a/configs/nucleo-l073rz/src/nucleo-l073rz.h +++ b/configs/nucleo-l073rz/src/nucleo-l073rz.h @@ -153,7 +153,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI +#ifdef CONFIG_STM32F0L0G0_SPI void stm32_spidev_initialize(void); #endif diff --git a/configs/nucleo-l073rz/src/stm32_boot.c b/configs/nucleo-l073rz/src/stm32_boot.c index 55b3989232..5ba0372431 100644 --- a/configs/nucleo-l073rz/src/stm32_boot.c +++ b/configs/nucleo-l073rz/src/stm32_boot.c @@ -83,7 +83,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0_SPI +#ifdef CONFIG_STM32F0L0G0_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/configs/nucleo-l073rz/src/stm32_mfrc522.c b/configs/nucleo-l073rz/src/stm32_mfrc522.c index e6ccb66807..97c13d9d7f 100644 --- a/configs/nucleo-l073rz/src/stm32_mfrc522.c +++ b/configs/nucleo-l073rz/src/stm32_mfrc522.c @@ -49,7 +49,7 @@ #include "stm32_spi.h" #include "nucleo-l073rz.h" -#if defined(CONFIG_SPI) && defined(CONFIG_STM32F0L0_SPI2) && defined(CONFIG_CL_MFRC522) +#if defined(CONFIG_SPI) && defined(CONFIG_STM32F0L0G0_SPI2) && defined(CONFIG_CL_MFRC522) /************************************************************************************ * Pre-processor Definitions diff --git a/configs/nucleo-l073rz/src/stm32_spi.c b/configs/nucleo-l073rz/src/stm32_spi.c index de68edcdfa..5fec5218b6 100644 --- a/configs/nucleo-l073rz/src/stm32_spi.c +++ b/configs/nucleo-l073rz/src/stm32_spi.c @@ -54,7 +54,7 @@ #include "nucleo-l073rz.h" #include -#ifdef CONFIG_STM32F0L0_SPI +#ifdef CONFIG_STM32F0L0G0_SPI /**************************************************************************** * Pre-processor Definitions @@ -92,7 +92,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32F0L0_SPI1 +#ifdef CONFIG_STM32F0L0G0_SPI1 # ifdef CONFIG_WL_NRF24L01 /* Configure the SPI-based NRF24L01 chip select GPIO */ @@ -112,16 +112,16 @@ void stm32_spidev_initialize(void) stm32_gpiowrite(GPIO_SX127X_CS, true); # endif -#endif /* CONFIG_STM32F0L0_SPI1 */ +#endif /* CONFIG_STM32F0L0G0_SPI1 */ -#ifdef CONFIG_STM32F0L0_SPI2 +#ifdef CONFIG_STM32F0L0G0_SPI2 /* Configure the SPI-based MFRC522 chip select GPIO */ # ifdef CONFIG_CL_MFRC522 (void)stm32_configgpio(GPIO_MFRC522_CS); # endif -#endif /* CONFIG_STM32F0L0_SPI2 */ +#endif /* CONFIG_STM32F0L0G0_SPI2 */ } /**************************************************************************** @@ -150,7 +150,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0_SPI1 +#ifdef CONFIG_STM32F0L0G0_SPI1 void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); @@ -215,9 +215,9 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) return status; } -#endif /* CONFIG_STM32F0L0_SPI1 */ +#endif /* CONFIG_STM32F0L0G0_SPI1 */ -#ifdef CONFIG_STM32F0L0_SPI2 +#ifdef CONFIG_STM32F0L0G0_SPI2 void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -259,6 +259,6 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) return status; } -#endif /* CONFIG_STM32F0L0_SPI2 */ +#endif /* CONFIG_STM32F0L0G0_SPI2 */ #endif diff --git a/configs/nucleo-l073rz/sx127x/defconfig b/configs/nucleo-l073rz/sx127x/defconfig index 9ccdb7f8dc..2ce7ee1738 100644 --- a/configs/nucleo-l073rz/sx127x/defconfig +++ b/configs/nucleo-l073rz/sx127x/defconfig @@ -58,9 +58,9 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0_PWR=y -CONFIG_STM32F0L0_SPI1=y -CONFIG_STM32F0L0_USART2=y +CONFIG_STM32F0L0G0_PWR=y +CONFIG_STM32F0L0G0_SPI1=y +CONFIG_STM32F0L0G0_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 diff --git a/configs/stm32f051-discovery/include/board.h b/configs/stm32f051-discovery/include/board.h index 7db6f4b8a0..543c118180 100644 --- a/configs/stm32f051-discovery/include/board.h +++ b/configs/stm32f051-discovery/include/board.h @@ -113,7 +113,7 @@ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ #define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0_USB +#ifdef CONFIG_STM32F0L0G0_USB # undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ # define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ @@ -129,7 +129,7 @@ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0_USB +#ifdef CONFIG_STM32F0L0G0_USB # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ diff --git a/configs/stm32f051-discovery/nsh/defconfig b/configs/stm32f051-discovery/nsh/defconfig index ffc93e5a34..4ee63b9a0b 100644 --- a/configs/stm32f051-discovery/nsh/defconfig +++ b/configs/stm32f051-discovery/nsh/defconfig @@ -50,8 +50,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0_PWR=y -CONFIG_STM32F0L0_USART1=y +CONFIG_STM32F0L0G0_PWR=y +CONFIG_STM32F0L0G0_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 diff --git a/configs/stm32f051-discovery/src/Makefile b/configs/stm32f051-discovery/src/Makefile index 564a6e714f..ffc5bc3aef 100644 --- a/configs/stm32f051-discovery/src/Makefile +++ b/configs/stm32f051-discovery/src/Makefile @@ -49,7 +49,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0_SPI),y) +ifeq ($(CONFIG_STM32F0L0G0_SPI),y) CSRCS += stm32_spi.c endif diff --git a/configs/stm32f051-discovery/src/stm32f051-discovery.h b/configs/stm32f051-discovery/src/stm32f051-discovery.h index 22691e03fe..7dc94065dc 100644 --- a/configs/stm32f051-discovery/src/stm32f051-discovery.h +++ b/configs/stm32f051-discovery/src/stm32f051-discovery.h @@ -55,14 +55,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0_SPI1 -# undef CONFIG_STM32F0L0_SPI2 -# undef CONFIG_STM32F0L0_SPI3 +# undef CONFIG_STM32F0L0G0_SPI1 +# undef CONFIG_STM32F0L0G0_SPI2 +# undef CONFIG_STM32F0L0G0_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0_SPI2 -# undef CONFIG_STM32F0L0_SPI3 +# undef CONFIG_STM32F0L0G0_SPI2 +# undef CONFIG_STM32F0L0G0_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0_SPI3 +# undef CONFIG_STM32F0L0G0_SPI3 #endif /* STM32F0Discovery GPIOs ***************************************************************************/ diff --git a/configs/stm32f072-discovery/include/board.h b/configs/stm32f072-discovery/include/board.h index ad5032af40..2ebd0d251f 100644 --- a/configs/stm32f072-discovery/include/board.h +++ b/configs/stm32f072-discovery/include/board.h @@ -113,7 +113,7 @@ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ #define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0_USB +#ifdef CONFIG_STM32F0L0G0_USB # undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ # define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ @@ -129,7 +129,7 @@ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0_USB +#ifdef CONFIG_STM32F0L0G0_USB # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ diff --git a/configs/stm32f072-discovery/nsh/defconfig b/configs/stm32f072-discovery/nsh/defconfig index 5621f0dc6a..3ea9636940 100644 --- a/configs/stm32f072-discovery/nsh/defconfig +++ b/configs/stm32f072-discovery/nsh/defconfig @@ -50,8 +50,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0_PWR=y -CONFIG_STM32F0L0_USART1=y +CONFIG_STM32F0L0G0_PWR=y +CONFIG_STM32F0L0G0_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 diff --git a/configs/stm32f072-discovery/src/Makefile b/configs/stm32f072-discovery/src/Makefile index e6bb4efaf2..550288851a 100644 --- a/configs/stm32f072-discovery/src/Makefile +++ b/configs/stm32f072-discovery/src/Makefile @@ -49,7 +49,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0_SPI),y) +ifeq ($(CONFIG_STM32F0L0G0_SPI),y) CSRCS += stm32_spi.c endif diff --git a/configs/stm32f072-discovery/src/stm32f072-discovery.h b/configs/stm32f072-discovery/src/stm32f072-discovery.h index 3d834708a2..4c527a1b67 100644 --- a/configs/stm32f072-discovery/src/stm32f072-discovery.h +++ b/configs/stm32f072-discovery/src/stm32f072-discovery.h @@ -55,14 +55,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0_SPI1 -# undef CONFIG_STM32F0L0_SPI2 -# undef CONFIG_STM32F0L0_SPI3 +# undef CONFIG_STM32F0L0G0_SPI1 +# undef CONFIG_STM32F0L0G0_SPI2 +# undef CONFIG_STM32F0L0G0_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0_SPI2 -# undef CONFIG_STM32F0L0_SPI3 +# undef CONFIG_STM32F0L0G0_SPI2 +# undef CONFIG_STM32F0L0G0_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0_SPI3 +# undef CONFIG_STM32F0L0G0_SPI3 #endif /* STM32F0Discovery GPIOs ***************************************************************************/