STM32 I2C: Final fixes from Max Kriegleder et al.
This commit is contained in:
Gregory Nutt
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8dbc4714c5
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5d3479bbec
@ -56,7 +56,8 @@
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* - Private: Private data of an I2C Hardware
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*
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* TODO
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* - Setup and test polled operation (CONFIG_I2C_POLLED)
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* - Trace events in polled operation fill trace table very quickly. Events 1111 and 1004 get traced
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* in an alternate fashion during polling causing multiple entries.
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* - Check for all possible deadlocks (as BUSY='1' I2C needs to be reset in HW using the I2C_CR1_SWRST)
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* - SMBus support (hardware layer timings are already supported) and add SMBA gpio pin
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* - Slave support with multiple addresses (on multiple instances):
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@ -206,38 +207,38 @@ enum stm32_intstate_e
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/* Trace events */
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#ifdef CONFIG_I2C_TRACE
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static const uint32_t I2CEVENT_NONE = 0; /* No events have occurred with this status */
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static const uint32_t I2CEVENT_STATE_ERROR = 1000; /* No correct state detected, diver cannot handle state */
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static const uint32_t I2CEVENT_ISR_SHUTDOWN = 1001; /* ISR gets shutdown */
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static const uint32_t I2CEVENT_ISR_EMPTY_CALL = 1002; /* ISR gets called but no I2C logic comes into play */
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static const uint32_t I2CEVENT_MSG_HANDLING = 1003; /* Message Handling 1/1: advances the msg processing param = msgc*/
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static const uint32_t I2CEVENT_POLL_DEV_NOT_RDY = 1004; /* During polled operation if device is not ready yet */
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static const uint32_t I2CEVENT_ISR_CALL = 1111; /* ISR called*/
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static const uint16_t I2CEVENT_NONE = 0; /* No events have occurred with this status */
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static const uint16_t I2CEVENT_STATE_ERROR = 1000; /* No correct state detected, diver cannot handle state */
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static const uint16_t I2CEVENT_ISR_SHUTDOWN = 1001; /* ISR gets shutdown */
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static const uint16_t I2CEVENT_ISR_EMPTY_CALL = 1002; /* ISR gets called but no I2C logic comes into play */
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static const uint16_t I2CEVENT_MSG_HANDLING = 1003; /* Message Handling 1/1: advances the msg processing param = msgc*/
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static const uint16_t I2CEVENT_POLL_DEV_NOT_RDY = 1004; /* During polled operation if device is not ready yet */
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static const uint16_t I2CEVENT_ISR_CALL = 1111; /* ISR called*/
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static const uint32_t I2CEVENT_SENDADDR = 5; /* Start/Master bit set and address sent, param = priv->msgv->addr(EV5 in reference manual) */
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static const uint32_t I2CEVENT_ADDR_HDL_READ_1 = 51; /* Read of length 1 address handling, param = 0 */
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static const uint32_t I2CEVENT_ADDR_HDL_READ_2 = 52; /* Read of length 2 address handling, param = 0 */
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static const uint32_t I2CEVENT_EMPTY_MSG = 5000; /* Empty message detected, param=0 */
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static const uint16_t I2CEVENT_SENDADDR = 5; /* Start/Master bit set and address sent, param = priv->msgv->addr(EV5 in reference manual) */
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static const uint16_t I2CEVENT_ADDR_HDL_READ_1 = 51; /* Read of length 1 address handling, param = 0 */
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static const uint16_t I2CEVENT_ADDR_HDL_READ_2 = 52; /* Read of length 2 address handling, param = 0 */
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static const uint16_t I2CEVENT_EMPTY_MSG = 5000; /* Empty message detected, param=0 */
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static const uint32_t I2CEVENT_ADDRESS_ACKED = 6; /* Address has been ACKed(i.e. it's a valid address) param = address */
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static const uint32_t I2CEVENT_ADDRESS_ACKED_READ_1 = 63; /* Event when reading single byte just after address is beeing ACKed, param = 0 */
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static const uint32_t I2CEVENT_ADDRESS_ACKED_READ_2 = 61; /* Event when reading two bytes just after address is beeing ACKed, param = 0 */
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static const uint32_t I2CEVENT_ADDRESS_ACKED_WRITE = 681; /* Address has been ACKed(i.e. it's a valid address) in write mode and byte has been written */
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static const uint32_t I2CEVENT_ADDRESS_NACKED = 6000; /* Address has been NACKed(i.e. it's an invalid address) param = address */
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static const uint16_t I2CEVENT_ADDRESS_ACKED = 6; /* Address has been ACKed(i.e. it's a valid address) param = address */
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static const uint16_t I2CEVENT_ADDRESS_ACKED_READ_1 = 63; /* Event when reading single byte just after address is beeing ACKed, param = 0 */
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static const uint16_t I2CEVENT_ADDRESS_ACKED_READ_2 = 61; /* Event when reading two bytes just after address is beeing ACKed, param = 0 */
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static const uint16_t I2CEVENT_ADDRESS_ACKED_WRITE = 681; /* Address has been ACKed(i.e. it's a valid address) in write mode and byte has been written */
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static const uint16_t I2CEVENT_ADDRESS_NACKED = 6000; /* Address has been NACKed(i.e. it's an invalid address) param = address */
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static const uint32_t I2CEVENT_READ = 7; /* RxNE = 1 therefore can be read, param = dcnt */
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static const uint32_t I2CEVENT_READ_3 = 72; /* EV7_2 reference manual, reading byte N-2 and N-1 when N >=3 */
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static const uint32_t I2CEVENT_READ_2 = 73; /* EV7_3 reference manual, reading byte 1 and 2 when N == 2 */
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static const uint32_t I2CEVENT_READ_SR_EMPTY = 79; /* DR is full but SR is empty, does not read DR and waits for SR to fill in next ISR */
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static const uint32_t I2CEVENT_READ_LAST_BYTE = 72; /* EV7_2 reference manual last two bytes are in SR and DR */
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static const uint32_t I2CEVENT_READ_ERROR = 7000; /* read mode error */
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static const uint16_t I2CEVENT_READ = 7; /* RxNE = 1 therefore can be read, param = dcnt */
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static const uint16_t I2CEVENT_READ_3 = 72; /* EV7_2 reference manual, reading byte N-2 and N-1 when N >=3 */
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static const uint16_t I2CEVENT_READ_2 = 73; /* EV7_3 reference manual, reading byte 1 and 2 when N == 2 */
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static const uint16_t I2CEVENT_READ_SR_EMPTY = 79; /* DR is full but SR is empty, does not read DR and waits for SR to fill in next ISR */
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static const uint16_t I2CEVENT_READ_LAST_BYTE = 72; /* EV7_2 reference manual last two bytes are in SR and DR */
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static const uint16_t I2CEVENT_READ_ERROR = 7000; /* read mode error */
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static const uint32_t I2CEVENT_WRITE_TO_DR = 8; /* EV8 reference manual, writing into the data register param = byte to send */
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static const uint32_t I2CEVENT_WRITE_STOP = 82; /* EV8_2 reference manual, set stop bit after write is finished */
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static const uint32_t I2CEVENT_WRITE_RESTART = 83; /* Re-send start bit as next packet is a read */
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static const uint32_t I2CEVENT_WRITE_NO_RESTART = 84; /* don't restart as packet flag says so */
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static const uint32_t I2CEVENT_WRITE_ERROR = 8000; /* Error in write mode, param = 0 */
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static const uint32_t I2CEVENT_WRITE_FLAG_ERROR = 8001; /* Next message has unrecognized flag, param = priv->msgv->flags */
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static const uint16_t I2CEVENT_WRITE_TO_DR = 8; /* EV8 reference manual, writing into the data register param = byte to send */
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static const uint16_t I2CEVENT_WRITE_STOP = 82; /* EV8_2 reference manual, set stop bit after write is finished */
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static const uint16_t I2CEVENT_WRITE_RESTART = 83; /* Re-send start bit as next packet is a read */
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static const uint16_t I2CEVENT_WRITE_NO_RESTART = 84; /* don't restart as packet flag says so */
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static const uint16_t I2CEVENT_WRITE_ERROR = 8000; /* Error in write mode, param = 0 */
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static const uint16_t I2CEVENT_WRITE_FLAG_ERROR = 8001; /* Next message has unrecognized flag, param = priv->msgv->flags */
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#endif /* CONFIG_I2C_TRACE */
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/* Trace data */
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@ -338,9 +339,9 @@ static inline void stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev);
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#ifdef CONFIG_I2C_TRACE
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static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv);
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static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status);
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static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint16_t status);
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static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
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uint32_t event, uint32_t parm);
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uint16_t event, uint32_t parm);
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static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv);
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#endif /* CONFIG_I2C_TRACE */
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@ -877,7 +878,7 @@ static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv)
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stm32_i2c_traceclear(priv);
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}
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static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status)
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static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint16_t status)
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{
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struct stm32_trace_s *trace = &priv->trace[priv->tndx];
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@ -917,7 +918,7 @@ static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t statu
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}
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static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
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uint32_t event, uint32_t parm)
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uint16_t event, uint32_t parm)
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{
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struct stm32_trace_s *trace;
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@ -1285,10 +1286,9 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
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if (priv->msgc == 0)
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{
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priv->msgv == NULL;
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/* Good practice + done by last implementation when messages are finished
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* (compatibility)
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/* No more messages, don't need to increment msgv. This pointer will be set
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* to zero when reaching the termination of the ISR calls, i.e. Messages
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* handling(2/2).
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*/
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}
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else
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@ -1868,16 +1868,23 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
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if (priv->dcnt == -1 && priv->msgc == 0)
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{
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uint32_t regval;
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i2cvdbg("Shutting down I2C ISR\n");
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stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0);
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/* Clear internal pointer to the message content.
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* Good practice + done by last implementation when messages are finished
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* (compatibility concerns)
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*/
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priv->msgv = NULL;
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#ifdef CONFIG_I2C_POLLED
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priv->intstate = INTSTATE_DONE;
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#else
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/* clear all interrupts */
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/* Clear all interrupts */
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uint32_t regval;
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regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET);
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regval &= ~I2C_CR2_ALLINTS;
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stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval);
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@ -2154,7 +2161,7 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
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* process the first message(first priv->msgv entry) correctly.
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*/
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priv->dcnt = -1;
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priv->dcnt = -1;
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priv->status = 0;
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stm32_i2c_sendstart(priv);
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