From 5d4e4b191912c4c03d91de27680faa2f174b24fa Mon Sep 17 00:00:00 2001
From: Huang Qi <huangqi3@xiaomi.com>
Date: Thu, 30 Mar 2023 13:02:09 +0800
Subject: [PATCH] tools/riscv: Map extensions to certain cpu model for LLVM
 based toolchain

RISCV has a modular instruction set. It's hard to define cpu-model to support all toolchain.
For Zig, cpu model is this formal: generic_rv[32|64][i][m][a][f][d][c]
For Rust, cpu model is this formal: riscv[32|64][i][m][a][f][d][c]
So, it's better to map the NuttX config to LLVM builtin cpu model, these models supported by
all LLVM based toolchain.
Refer to : https://github.com/llvm/llvm-project/blob/release/15.x/llvm/lib/Target/RISCV/RISCV.td
These models can't cover all implementation of RISCV, but it's enough for most cases.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
---
 arch/risc-v/src/common/Toolchain.defs | 32 ++++++++++++++++++++++-----
 1 file changed, 26 insertions(+), 6 deletions(-)

diff --git a/arch/risc-v/src/common/Toolchain.defs b/arch/risc-v/src/common/Toolchain.defs
index 1d794539f6..520f3058f0 100644
--- a/arch/risc-v/src/common/Toolchain.defs
+++ b/arch/risc-v/src/common/Toolchain.defs
@@ -132,27 +132,22 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
 
   ifeq ($(CONFIG_ARCH_RV_ISA_M),y)
     ARCHRVISAM = m
-    ZARCHRVISAM := +m
   endif
 
   ifeq ($(CONFIG_ARCH_RV_ISA_A),y)
     ARCHRVISAA = a
-    ZARCHRVISAA := +a
   endif
 
   ifeq ($(CONFIG_ARCH_RV_ISA_C),y)
     ARCHRVISAC = c
-    ZARCHRVISAC := +c
   endif
 
   ifeq ($(CONFIG_ARCH_FPU),y)
     ARCHRVISAF = f
-    ZARCHRVISAF := +f
   endif
 
   ifeq ($(CONFIG_ARCH_DPFPU),y)
     ARCHRVISAD = d
-    ZARCHRVISAD := +d
   endif
 
   # Detect abi type
@@ -169,7 +164,8 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
 
   # Construct arch flags
 
-  ARCHCPUFLAGS = -march=$(ARCHTYPE)i$(ARCHRVISAM)$(ARCHRVISAA)$(ARCHRVISAF)$(ARCHRVISAD)$(ARCHRVISAC)
+  ARCHCPUEXTFLAGS = i$(ARCHRVISAM)$(ARCHRVISAA)$(ARCHRVISAF)$(ARCHRVISAD)$(ARCHRVISAC)
+  ARCHCPUFLAGS = -march=$(ARCHTYPE)$(ARCHCPUEXTFLAGS)
 
   # Construct arch abi flags
 
@@ -186,6 +182,30 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
 
 endif
 
+# RISCV has a modular instruction set. It's hard to define cpu-model to support all toolchain.
+# For Zig, cpu model is this formal: generic_rv[32|64][i][m][a][f][d][c]
+# For Rust, cpu model is this formal: riscv[32|64][i][m][a][f][d][c]
+# So, it's better to map the NuttX config to LLVM builtin cpu model, these models supported by
+# all LLVM based toolchain.
+# Refer to : https://github.com/llvm/llvm-project/blob/release/15.x/llvm/lib/Target/RISCV/RISCV.td
+# These models can't cover all implementation of RISCV, but it's enough for most cases.
+
+ifeq ($(CONFIG_ARCH_RV32),y)
+  ifeq ($(ARCHCPUEXTFLAGS), imc)
+    LLVM_CPUTYPE := sifive-e20
+  else ifeq ($(ARCHCPUEXTFLAGS), imac)
+    LLVM_CPUTYPE := sifive-e31
+  else ifeq ($(ARCHCPUEXTFLAGS), imafc)
+    LLVM_CPUTYPE := sifive-e76
+  endif
+else
+  ifeq ($(ARCHCPUEXTFLAGS), imac)
+    LLVM_CPUTYPE := sifive-s51
+  else ifeq ($(ARCHCPUEXTFLAGS), imafdc)
+    LLVM_CPUTYPE := sifive-u54
+  endif
+endif
+
 ifeq ($(CONFIG_MM_KASAN_ALL),y)
   ARCHOPTIMIZATION += -fsanitize=kernel-address
 endif