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xtensa/esp32_irq.c: Hard code special IRQs in the IRQ map. These IRQs

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are do not go through the regular process where we attache the CPU
interrupt to a peripheral and update our map, also, they are fixed and a
have reserved CPU interrupt, thus hard code their values at startup.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit is contained in:
Abdelatif Guettouche 2021-08-05 16:58:07 +02:00 committed by Gustavo Henrique Nihei
parent 56a7f3b651
commit 5d626f7267
1 changed files with 8 additions and 12 deletions
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20
arch/xtensa/src/esp32/esp32_irq.c
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@ -167,6 +167,14 @@ void up_irqinitialize(void)
g_irqmap[i] = IRQ_UNMAPPED;
}
/* Hard code special cases. */
g_irqmap[XTENSA_IRQ_TIMER0] = IRQ_MKMAP(0, ESP32_CPUINT_TIMER0);
#ifdef CONFIG_ESP32_WIRELESS
g_irqmap[ESP32_IRQ_MAC] = IRQ_MKMAP(0, ESP32_CPUINT_MAC);
#endif
/* Initialize CPU interrupts */
esp32_cpuint_initialize();
@ -287,18 +295,6 @@ void up_enable_irq(int irq)
int cpu = IRQ_GETCPU(g_irqmap[irq]);
int cpuint = IRQ_GETCPUINT(g_irqmap[irq]);
/* The internal Timer 0 interrupt is not attached to any peripheral, and
* thus has no mapping, it has to be handled separately.
* We know it's enabled early before the second CPU has started, so we don't
* need any IPC call.
*/
if (irq == XTENSA_IRQ_TIMER0)
{
cpu = 0;
cpuint = ESP32_CPUINT_TIMER0;
}
DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX);
#ifdef CONFIG_SMP
DEBUGASSERT(cpu >= 0 && cpu <= CONFIG_SMP_NCPUS);