arch/risc-v: move REGLOAD/REGSTORE macro to riscv_internal.h
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
This commit is contained in:
Petro Karashchenko
Xiang Xiao
parent
264e39e121
commit
5d856971db
@ -31,14 +31,6 @@
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* Public Symbols
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****************************************************************************/
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#ifdef CONFIG_ARCH_RV32
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# define REGLOAD lw
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# define REGSTORE sw
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#else
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# define REGLOAD ld
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# define REGSTORE sd
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#endif
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#ifdef CONFIG_IRQ_NSTACKS
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# define IRQ_NSTACKS CONFIG_IRQ_NSTACKS
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#elif defined CONFIG_SMP
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@ -26,12 +26,20 @@
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#include <arch/irq.h>
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#include "riscv_internal.h"
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#ifdef CONFIG_ARCH_FPU
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#define FS_MASK 0x6000
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#define FS_OFF 0x0000
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#define FS_INITIAL 0x2000
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#define FS_CLEAN 0x4000
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#define FS_DIRTY 0x6000
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/************************************************************************************
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* Public Symbols
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************************************************************************************/
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@ -42,31 +50,6 @@
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.file "riscv_fpu.S"
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#define FS_MASK 0x6000
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#define FS_OFF 0x0000
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#define FS_INITIAL 0x2000
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#define FS_CLEAN 0x4000
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#define FS_DIRTY 0x6000
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#if defined(CONFIG_ARCH_QPFPU)
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# define FLOAD flq
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# define FSTORE fsq
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#elif defined(CONFIG_ARCH_DPFPU)
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# define FLOAD fld
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# define FSTORE fsd
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#else
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# define FLOAD flw
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# define FSTORE fsw
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#endif
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#ifdef CONFIG_ARCH_RV32
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# define REGLOAD lw
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# define REGSTORE sw
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#else
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# define REGLOAD ld
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# define REGSTORE sd
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#endif
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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@ -38,6 +38,32 @@
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* Pre-processor Definitions
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****************************************************************************/
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#ifdef __ASSEMBLY__
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# define __STR(s) s
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#else
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# define __STR(s) #s
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#endif
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#define __XSTR(s) __STR(s)
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#if defined(CONFIG_ARCH_QPFPU)
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# define FLOAD __STR(flq)
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# define FSTORE __STR(fsq)
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#elif defined(CONFIG_ARCH_DPFPU)
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# define FLOAD __STR(fld)
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# define FSTORE __STR(fsd)
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#else
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# define FLOAD __STR(flw)
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# define FSTORE __STR(fsw)
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#endif
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#ifdef CONFIG_ARCH_RV32
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# define REGLOAD __STR(lw)
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# define REGSTORE __STR(sw)
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#else
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# define REGLOAD __STR(ld)
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# define REGSTORE __STR(sd)
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#endif
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/* This is the value used to mark the stack for subsequent stack monitoring
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* logic.
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*/
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@ -49,6 +75,7 @@
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/* RISC-V requires a 16-byte stack alignment. */
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#define STACK_ALIGNMENT 16
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#define STACK_FRAME_SIZE __XSTR(STACK_ALIGNMENT)
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/* Stack alignment macros */
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@ -26,6 +26,8 @@
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#include <arch/syscall.h>
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#include "riscv_internal.h"
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#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__)
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/****************************************************************************
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@ -69,8 +71,8 @@ up_signal_handler:
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/* Save ra on the stack */
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addi sp, sp, -16
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sd ra, 8(sp)
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addi sp, sp, -STACK_FRAME_SIZE
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REGSTORE ra, 8(sp)
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/* Call the signal handler */
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@ -82,8 +84,8 @@ up_signal_handler:
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/* Restore the register */
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ld ra, 8(sp) /* Restore ra in sp */
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addi sp, sp, 16
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REGLOAD ra, 8(sp) /* Restore ra in sp */
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addi sp, sp, STACK_FRAME_SIZE
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/* Execute the SYS_signal_handler_return SVCall (will not return) */
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@ -109,45 +109,24 @@ static void riscv_registerdump(const uintptr_t *regs)
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#ifdef CONFIG_LIB_SYSCALL
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static void dispatch_syscall(void) naked_function;
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#ifdef CONFIG_ARCH_RV64
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static void dispatch_syscall(void)
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{
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asm volatile
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(
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" addi sp, sp, -8\n" /* Create a stack frame to hold ra */
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" sd ra, 0(sp)\n" /* Save ra in the stack frame */
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" la t0, g_stublookup\n" /* t0=The base of the stub lookup table */
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" slli a0, a0, 3\n" /* a0=Offset for the stub lookup table */
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" add t0, t0, a0\n" /* t0=The address in the table */
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" ld t0, 0(t0)\n" /* t0=The address of the stub for this syscall */
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" jalr ra, t0\n" /* Call the stub (modifies ra) */
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" ld ra, 0(sp)\n" /* Restore ra */
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" addi sp, sp, 8\n" /* Destroy the stack frame */
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" mv a2, a0\n" /* a2=Save return value in a0 */
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" li a0, 3\n" /* a0=SYS_syscall_return (3) */
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" ecall" /* Return from the syscall */
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"addi sp, sp, -" STACK_FRAME_SIZE "\n" /* Create a stack frame to hold ra */
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REGSTORE " ra, 0(sp)\n" /* Save ra in the stack frame */
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"la t0, g_stublookup\n" /* t0=The base of the stub lookup table */
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"slli a0, a0, 3\n" /* a0=Offset for the stub lookup table */
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"add t0, t0, a0\n" /* t0=The address in the table */
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REGLOAD " t0, 0(t0)\n" /* t0=The address of the stub for this syscall */
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"jalr ra, t0\n" /* Call the stub (modifies ra) */
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REGLOAD " ra, 0(sp)\n" /* Restore ra */
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"addi sp, sp, " STACK_FRAME_SIZE "\n" /* Destroy the stack frame */
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"mv a2, a0\n" /* a2=Save return value in a0 */
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"li a0, 3\n" /* a0=SYS_syscall_return (3) */
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"ecall" /* Return from the syscall */
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);
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}
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#else
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static void dispatch_syscall(void)
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{
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asm volatile
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(
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" addi sp, sp, -4\n" /* Create a stack frame to hold ra */
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" sw ra, 0(sp)\n" /* Save ra in the stack frame */
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" la t0, g_stublookup\n" /* t0=The base of the stub lookup table */
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" slli a0, a0, 3\n" /* a0=Offset for the stub lookup table */
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" add t0, t0, a0\n" /* t0=The address in the table */
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" lw t0, 0(t0)\n" /* t0=The address of the stub for this syscall */
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" jalr ra, t0\n" /* Call the stub (modifies ra) */
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" lw ra, 0(sp)\n" /* Restore ra */
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" addi sp, sp, 4\n" /* Destroy the stack frame */
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" mv a2, a0\n" /* a2=Save return value in a0 */
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" li a0, 3\n" /* a0=SYS_syscall_return (3) */
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" ecall" /* Return from the syscall */
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);
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}
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#endif
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#endif
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/****************************************************************************
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@ -72,11 +72,7 @@ __start:
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/* Load idle stack base to sp */
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#ifdef CONFIG_ARCH_RV32
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lw sp, 0(t0)
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#else
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ld sp, 0(t0)
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#endif
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REGLOAD sp, 0(t0)
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/*
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* sp (stack top) = sp + idle stack size - XCPTCONTEXT_SIZE
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