diff --git a/arch/arm/src/stm32/stm32_bbsram.c b/arch/arm/src/stm32/stm32_bbsram.c
index 81c49340ae..a401feca56 100644
--- a/arch/arm/src/stm32/stm32_bbsram.c
+++ b/arch/arm/src/stm32/stm32_bbsram.c
@@ -256,7 +256,7 @@ static void stm32_bbsram_semtake(FAR struct stm32_bbsram_s *priv)
 
 static inline void stm32_bbsram_unlock(void)
 {
-  (void)stm32_pwr_enablebkp(true);
+  stm32_pwr_enablebkp(true);
 }
 
 /****************************************************************************
@@ -276,7 +276,7 @@ static inline void stm32_bbsram_unlock(void)
 
 static inline void stm32_bbsram_lock(void)
 {
-  (void)stm32_pwr_enablebkp(false);
+  stm32_pwr_enablebkp(false);
 }
 
 /****************************************************************************
diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c
index 553f76e73d..cf3c115d63 100644
--- a/arch/arm/src/stm32/stm32_rcc.c
+++ b/arch/arm/src/stm32/stm32_rcc.c
@@ -128,7 +128,7 @@ static inline void rcc_resetbkp(void)
   regval = getreg32(RTC_MAGIC_REG);
   if (regval != RTC_MAGIC)
     {
-      (void)stm32_pwr_enablebkp(true);
+      stm32_pwr_enablebkp(true);
 
       /* We might be changing RTCSEL - to ensure such changes work, we must
        * reset the backup domain (having backed up the RTC_MAGIC token)
@@ -137,7 +137,7 @@ static inline void rcc_resetbkp(void)
       modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST);
       modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0);
 
-      (void)stm32_pwr_enablebkp(false);
+      stm32_pwr_enablebkp(false);
     }
 }
 #else
diff --git a/arch/arm/src/stm32/stm32_rtcc.c b/arch/arm/src/stm32/stm32_rtcc.c
index da8f57db59..21e0441c06 100644
--- a/arch/arm/src/stm32/stm32_rtcc.c
+++ b/arch/arm/src/stm32/stm32_rtcc.c
@@ -222,7 +222,7 @@ static void rtc_wprunlock(void)
    * registers and backup SRAM).
    */
 
-  (void)stm32_pwr_enablebkp(true);
+  stm32_pwr_enablebkp(true);
 
   /* The following steps are required to unlock the write protection on all the
    * RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR).
@@ -261,7 +261,7 @@ static inline void rtc_wprlock(void)
    * registers and backup SRAM).
    */
 
-  (void)stm32_pwr_enablebkp(false);
+  stm32_pwr_enablebkp(false);
 }
 
 /************************************************************************************
@@ -598,7 +598,7 @@ int up_rtc_initialize(void)
 
   regval = getreg32(RTC_MAGIC_REG);
 
-  (void)stm32_pwr_enablebkp(true);
+  stm32_pwr_enablebkp(true);
 
   if (regval != RTC_MAGIC)
     {
@@ -673,7 +673,7 @@ int up_rtc_initialize(void)
         }
     }
 
-  (void)stm32_pwr_enablebkp(false);
+  stm32_pwr_enablebkp(false);
 
   /* Loop, attempting to initialize/resume the RTC.  This loop is necessary
    * because it seems that occasionally it takes longer to initialize the RTC
@@ -724,7 +724,7 @@ int up_rtc_initialize(void)
        * backup data registers and backup SRAM).
        */
 
-      (void)stm32_pwr_enablebkp(true);
+      stm32_pwr_enablebkp(true);
 
       /* Remember that the RTC is initialized */
 
@@ -744,7 +744,7 @@ int up_rtc_initialize(void)
    * data registers and backup SRAM).
    */
 
-  (void)stm32_pwr_enablebkp(false);
+  stm32_pwr_enablebkp(false);
 
   if (ret != OK && nretry > 0)
     {
diff --git a/arch/arm/src/stm32/stm32_rtcounter.c b/arch/arm/src/stm32/stm32_rtcounter.c
index 8156de0a60..137e7344a0 100644
--- a/arch/arm/src/stm32/stm32_rtcounter.c
+++ b/arch/arm/src/stm32/stm32_rtcounter.c
@@ -377,7 +377,7 @@ int up_rtc_initialize(void)
    * registers and backup SRAM).
    */
 
-  (void)stm32_pwr_enablebkp(true);
+  stm32_pwr_enablebkp(true);
 
   /* Set access to the peripheral, enable the backup domain (BKP) and the lower
    * power external 32,768Hz (Low-Speed External, LSE) oscillator.  Configure the
@@ -428,7 +428,7 @@ int up_rtc_initialize(void)
    * registers and backup SRAM).
    */
 
-  (void)stm32_pwr_enablebkp(false);
+  stm32_pwr_enablebkp(false);
 
   return OK;
 }
@@ -605,7 +605,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
   /* Enable write access to the backup domain */
 
   flags = enter_critical_section();
-  (void)stm32_pwr_enablebkp(true);
+  stm32_pwr_enablebkp(true);
 
   /* Then write the broken out values to the RTC counter and BKP overflow register
    * (hi-res mode only)
@@ -625,7 +625,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
   putreg16(regvals.ovf, RTC_TIMEMSB_REG);
 #endif
 
-  (void)stm32_pwr_enablebkp(false);
+  stm32_pwr_enablebkp(false);
   leave_critical_section(flags);
   return OK;
 }
diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
index 7145243b89..5b1f244977 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
@@ -263,7 +263,7 @@ static void rtc_wprunlock(void)
    * registers and backup SRAM).
    */
 
-  (void)stm32_pwr_enablebkp(true);
+  stm32_pwr_enablebkp(true);
 
   /* The following steps are required to unlock the write protection on all the
    * RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR).
@@ -302,7 +302,7 @@ static inline void rtc_wprlock(void)
    * data registers and backup SRAM).
    */
 
-  (void)stm32_pwr_enablebkp(false);
+  stm32_pwr_enablebkp(false);
 }
 
 /****************************************************************************
@@ -892,7 +892,7 @@ int up_rtc_initialize(void)
 
   regval = getreg32(RTC_MAGIC_REG);
 
-  (void)stm32_pwr_enablebkp(true);
+  stm32_pwr_enablebkp(true);
 
   if (regval != RTC_MAGIC)
     {
@@ -972,7 +972,7 @@ int up_rtc_initialize(void)
         }
     }
 
-  (void)stm32_pwr_enablebkp(false);
+  stm32_pwr_enablebkp(false);
 
   /* Loop, attempting to initialize/resume the RTC.  This loop is necessary
    * because it seems that occasionally it takes longer to initialize the RTC
@@ -1023,7 +1023,7 @@ int up_rtc_initialize(void)
        * backup data registers and backup SRAM).
        */
 
-      (void)stm32_pwr_enablebkp(true);
+      stm32_pwr_enablebkp(true);
 
       /* Remember that the RTC is initialized */
 
@@ -1043,7 +1043,7 @@ int up_rtc_initialize(void)
    * data registers and backup SRAM).
    */
 
-  (void)stm32_pwr_enablebkp(false);
+  stm32_pwr_enablebkp(false);
 
   if (ret != OK && nretry > 0)
     {