sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Add power save logic

Browse Source 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2637 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-04-29 01:55:16 +00:00
parent fae4de246f
commit 5db45464f7
2 changed files with 285 additions and 163 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

246
drivers/net/enc28j60.c
View File

@ -57,6 +57,7 @@
#include <nuttx/arch.h>
#include <nuttx/spi.h>
#include <nuttx/wqueue.h>
#include <nuttx/clock.h>
#include <net/uip/uip.h>
#include <net/uip/uip-arp.h>
@ -111,6 +112,11 @@
#define ENC_TXTIMEOUT (60*CLK_TCK)
/* Poll timeout */
#define ENC_POLLTIMEOUT MSEC2TICK(50)
/* Misc. Helper Macros ******************************************************/
#define enc_rdgreg(priv,ctrlreg) \
@ -203,7 +209,8 @@ static void enc_setbank(FAR struct enc_driver_s *priv, uint8_t bank);
static uint8_t enc_rdbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg);
static void enc_wrbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg,
uint8_t wrdata);
static uint8_t enc_rdmreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg);
static int enc_waitbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg,
uint8_t bits, uint8_t value);
/* SPI buffer transfers */
@ -247,6 +254,8 @@ static int enc_txavail(struct uip_driver_s *dev);
/* Initialization */
static void enc_pwrsave(FAR struct enc_driver_s *priv);
static void enc_pwrfull(FAR struct enc_driver_s *priv);
static void enc_setmacaddr(FAR struct enc_driver_s *priv);
static void enc_reset(FAR struct enc_driver_s *priv);
@ -464,53 +473,21 @@ static uint8_t enc_rdbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg)
enc_setbank(priv, GETBANK(ctrlreg));
/* Send the RCR command and collect the data. The sequence requires
* 16-clocks: 8 to clock out the cmd + 8 to clock in the data.
*/
(void)SPI_SEND(spi, ENC_RCR | GETADDR(ctrlreg)); /* Clock out the command */
rddata = SPI_SEND(spi, 0); /* Clock in the data */
/* De-select ENC28J60 chip */
enc_deselect(spi);
return rddata;
}
/****************************************************************************
* Function: enc_rdmreg
*
* Description:
* Somewhat different timing is required to read from any PHY or MAC
* registers. The PHY/MAC data is returned on the second byte after the
* command.
*
****************************************************************************/
static uint8_t enc_rdmreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg)
{
FAR struct spi_dev_s *spi;
uint8_t rddata;
DEBUGASSERT(priv && priv->spi);
spi = priv->spi;
/* Select ENC28J60 chip */
enc_select(spi);
/* Set the bank */
enc_setbank(priv, GETBANK(ctrlreg));
/* Send the RCR command and collect the data. The sequence requires
* 24-clocks: 8 to clock out the cmd, 8 dummy bits, and 8 to clock in
the data.
/* Send the RCR command and collect the data. How we collect the data
* depends on if this is a PHY/CAN or not. The normal sequence requires
* 16-clocks: 8 to clock out the cmd and 8 to clock in the data.
*/
(void)SPI_SEND(spi, ENC_RCR | GETADDR(ctrlreg)); /* Clock out the command */
(void)SPI_SEND(spi,0); /* Clock in the dummy byte */
rddata = SPI_SEND(spi, 0); /* Clock in the PHY/MAC data */
if (ISPHYMAC(ctrlreg))
{
/* The PHY/MAC sequence requires 24-clocks: 8 to clock out the cmd,
* 8 dummy bits, and 8 to clock in the PHY/MAC data.
*/
(void)SPI_SEND(spi,0); /* Clock in the dummy byte */
}
rddata = SPI_SEND(spi, 0); /* Clock in the data */
/* De-select ENC28J60 chip */
@ -522,7 +499,9 @@ static uint8_t enc_rdmreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg)
* Function: enc_wrbreg
*
* Description:
* Write to a banked control register using the WCR command.
* Write to a banked control register using the WCR command. Unlike
* reading, this same SPI sequence works for normal, MAC, and PHY
* registers.
*
****************************************************************************/
@ -554,6 +533,35 @@ static void enc_wrbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg,
enc_deselect(spi);
}
/****************************************************************************
* Function: enc_waitbreg
*
* Description:
* Wait until banked register bit(s) take a specific value (or a timeout
* occurs).
*
****************************************************************************/
static int enc_waitbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg,
uint8_t bits, uint8_t value)
{
uint32_t start = g_system_timer;
uint32_t elapsed;
uint8_t rddata;
/* Loop until the exit condition is met */
do
{
/* Read the byte from the requested banked register */
rddata = enc_rdbreg(priv, ctrlreg);
elapsed = g_system_timer - start;
}
while ((rddata & bits) != value || elapsed > ENC_POLLTIMEOUT);
return (rddata & bits) == value ? -ETIMEDOUT : OK;
}
/****************************************************************************
* Function: enc_rdbuffer
*
@ -630,7 +638,7 @@ static void enc_wrbuffer(FAR struct enc_driver_s *priv,
static uint16_t enc_rdphy(FAR struct enc_driver_s *priv, uint8_t phyaddr)
{
uint16_t data;
uint16_t data = 0;
/* Set the PHY address (and start the PHY read operation) */
@ -639,16 +647,17 @@ static uint16_t enc_rdphy(FAR struct enc_driver_s *priv, uint8_t phyaddr)
/* Wait until the PHY read completes */
while ((enc_rdmreg(priv, ENC_MISTAT) & MISTAT_BUSY) != 0 );
if (enc_waitbreg(priv, ENC_MISTAT, MISTAT_BUSY, 0x00) == OK);
{
/* Terminate reading */
/* Terminate reading */
enc_wrbreg(priv, ENC_MICMD, 0x00);
enc_wrbreg(priv, ENC_MICMD, 0x00);
/* Get the PHY data */
/* Get the PHY data */
data = (uint16_t)enc_rdmreg(priv, ENC_MIRDL);
data |= (uint16_t)enc_rdmreg(priv, ENC_MIRDH) << 8;
data = (uint16_t)enc_rdbreg(priv, ENC_MIRDL);
data |= (uint16_t)enc_rdbreg(priv, ENC_MIRDH) << 8;
}
return data;
}
@ -674,7 +683,7 @@ static void enc_wrphy(FAR struct enc_driver_s *priv, uint8_t phyaddr,
/* Wait until the PHY write completes */
while ((enc_rdmreg(priv, ENC_MISTAT) & MISTAT_BUSY) != 0);
enc_waitbreg(priv, ENC_MISTAT, MISTAT_BUSY, 0x00);
}
/****************************************************************************
@ -1282,10 +1291,21 @@ static int enc_ifup(struct uip_driver_s *dev)
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
/* Initialize Ethernet interface */
/* Initialize Ethernet interface, set the MAC address, and make sure that
* the ENC28J80 is not in power save mode.
*/
enc_reset(priv);
enc_setmacaddr(priv);
enc_pwrfull(priv);
/* Enable interrutps */
enc_bfsgreg(priv, ENC_EIE, EIE_INTIE | EIE_PKTIE);
/* Enable packet reception */
enc_bfsgreg(priv, ENC_ECON1, ECON1_RXEN);
/* Set and activate a timer process */
@ -1329,7 +1349,10 @@ static int enc_ifdown(struct uip_driver_s *dev)
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
/* Reset the device */
/* Reset the device and leave in the power save state */
enc_reset(priv);
enc_pwrsave(priv);
priv->bifup = false;
irqrestore(flags);
@ -1378,6 +1401,101 @@ static int enc_txavail(struct uip_driver_s *dev)
return OK;
}
/****************************************************************************
* Function: enc_pwrsave
*
* Description:
* The ENC28J60 may be commanded to power-down via the SPI interface.
* When powered down, it will no longer be able to transmit and receive
* any packets. To maximize power savings:
*
* 1. Turn off packet reception by clearing ECON1.RXEN.
* 2. Wait for any in-progress packets to finish being received by
* polling ESTAT.RXBUSY. This bit should be clear before proceeding.
* 3. Wait for any current transmissions to end by confirming ECON1.TXRTS
* is clear.
* 4. Set ECON2.VRPS (if not already set).
* 5. Enter Sleep by setting ECON2.PWRSV. All MAC, MII and PHY registers
* become inaccessible as a result. Setting PWRSV also clears
* ESTAT.CLKRDY automatically.
*
* In Sleep mode, all registers and buffer memory will maintain their
* states. The ETH registers and buffer memory will still be accessible
* by the host controller. Additionally, the clock driver will continue
* to operate. The CLKOUT function will be unaffected.
*
****************************************************************************/
static void enc_pwrsave(FAR struct enc_driver_s *priv)
{
/* 1. Turn off packet reception by clearing ECON1.RXEN. */
enc_bfcgreg(priv, ENC_ECON1, ECON1_RXEN);
/* 2. Wait for any in-progress packets to finish being received by
* polling ESTAT.RXBUSY. This bit should be clear before proceeding.
*/
if (enc_waitbreg(priv, ENC_ESTAT, ESTAT_RXBUSY, 0) == OK)
{
/* 3. Wait for any current transmissions to end by confirming
* ECON1.TXRTS is clear.
*/
enc_waitbreg(priv, ENC_ECON1, ECON1_TXRTS, 0);
/* 4. Set ECON2.VRPS (if not already set). */
enc_bfsgreg(priv, ENC_ECON2, ECON2_VRPS);
/* 5. Enter Sleep by setting ECON2.PWRSV. */
enc_bfsgreg(priv, ENC_ECON2, ECON2_PWRSV);
}
}
/****************************************************************************
* Function: enc_pwrfull
*
* Description:
* When normal operation is desired, the host controller must perform
* a slightly modified procedure:
*
* 1. Wake-up by clearing ECON2.PWRSV.
* 2. Wait at least 300 ìs for the PHY to stabilize. To accomplish the
* delay, the host controller may poll ESTAT.CLKRDY and wait for it
* to become set.
* 3. Restore receive capability by setting ECON1.RXEN.
*
* After leaving Sleep mode, there is a delay of many milliseconds
* before a new link is established (assuming an appropriate link
* partner is present). The host controller may wish to wait until
* the link is established before attempting to transmit any packets.
* The link status can be determined by polling the PHSTAT2.LSTAT bit.
* Alternatively, the link change interrupt may be used if it is
* enabled.
*
****************************************************************************/
static void enc_pwrfull(FAR struct enc_driver_s *priv)
{
/* 1. Wake-up by clearing ECON2.PWRSV. */
enc_bfcgreg(priv, ENC_ECON2, ECON2_PWRSV);
/* 2. Wait at least 300 ìs for the PHY to stabilize. To accomplish the
* delay, the host controller may poll ESTAT.CLKRDY and wait for it to
* become set.
*/
enc_waitbreg(priv, ENC_ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
/* 3. Restore receive capability by setting ECON1.RXEN.
*
* The caller will do this when it is read to receive packets
*/
}
/****************************************************************************
* Function: enc_setmacaddr
*
@ -1464,10 +1582,6 @@ int enc_initialize(FAR struct spi_dev_s *spi, unsigned int devno, unsigned int i
DEBUGASSERT(devno < CONFIG_ENC28J60_NINTERFACES);
priv = &g_enc28j60[devno];
/* Initialize and configure the ENC28J60 */
enc_reset(priv);
/* Initialize the driver structure */
memset(g_enc28j60, 0, CONFIG_ENC28J60_NINTERFACES*sizeof(struct enc_driver_s));
@ -1483,6 +1597,13 @@ int enc_initialize(FAR struct spi_dev_s *spi, unsigned int devno, unsigned int i
priv->spi = spi; /* Save the SPI instance */
priv->irq = irq; /* Save the IRQ number */
/* Make sure that the interface is in the down state. NOTE: The MAC
* address will not be set up until ifup. That gives the app time to set
* the MAC address before bringing the interface up.
*/
enc_ifdown(&priv->dev);
/* Attach the IRQ to the driver (but don't enable it yet) */
if (irq_attach(irq, enc_interrupt))
@ -1492,9 +1613,6 @@ int enc_initialize(FAR struct spi_dev_s *spi, unsigned int devno, unsigned int i
return -EAGAIN;
}
/* NOTE: The MAC address will not be set up ifup. That gives the app time
* to set the MAC address.
*/
/* Register the device with the OS so that socket IOCTLs can be performed */

202
drivers/net/enc28j60.h
View File

@ -152,8 +152,9 @@
/* Banked Control Registers *************************************************/
/* The remaining control registers are identified with a a 5 bit address and
* a bank selection. We pack the bank number and the control register
* address together to keep the design simpler.
* a bank selection. We pack the bank number and an indication if this is
* a MAC/PHY register access together with the control register address
* together to keep the design simpler.
*/
#define ENC_ADDR_SHIFT (0) /* Bits 0-4: Register address */
@ -164,67 +165,70 @@
# define ENC_BANK1 (1 << ENC_BSEL_SHIFT)
# define ENC_BANK2 (2 << ENC_BSEL_SHIFT)
# define ENC_BANK3 (3 << ENC_BSEL_SHIFT)
#define ENC_PHYMAC_SHIFT (7) /* Bit 7: This is a PHY/MAC command */
#define ENC_PHYMAC (1 << ENC_PHYMAC_SHIFT)
#define REGADDR(a,b) ((b) << ENC_BANK_SHIFT | (a))
#define REGADDR(a,b,m) ((m) << ENC_PHYMAC_SHIFT | (b) << ENC_BANK_SHIFT | (a))
#define GETADDR(a) ((a) & ENC_ADDR_MASK)
#define GETBANK(a) (((a) >> ENC_BANK_SHIFT) & 3)
#define ISPHYMAC(a) (((a) & ENC_PHYMAC) != 0)
/* Bank 0 Control Register Addresses */
#define ENC_ERDPTL REGADDR(0x00, 0) /* Read Pointer Low Byte (ERDPT<7:0> */
#define ENC_ERDPTH REGADDR(0x01, 0) /* Read Pointer High Byte (ERDPT<12:8>) */
#define ENC_EWRPTL REGADDR(0x02, 0) /* Write Pointer Low Byte (EWRPT<7:0>) */
#define ENC_EWRPTH REGADDR(0x03, 0) /* Write Pointer High Byte (EWRPT<12:8>) */
#define ENC_ETXSTL REGADDR(0x04, 0) /* TX Start Low Byte (ETXST<7:0>) */
#define ENC_ETXSTH REGADDR(0x05, 0) /* TX Start High Byte (ETXST<12:8>) */
#define ENC_ETXNDL REGADDR(0x06, 0) /* TX End Low Byte (ETXND<7:0>) */
#define ENC_ETXNDH REGADDR(0x07, 0) /* TX End High Byte (ETXND<12:8>) */
#define ENC_ERXSTL REGADDR(0x08, 0) /* RX Start Low Byte (ERXST<7:0>) */
#define ENC_ERXSTH REGADDR(0x09, 0) /* RX Start High Byte (ERXST<12:8>) */
#define ENC_ERXNDL REGADDR(0x0a, 0) /* RX End Low Byte (ERXND<7:0>) */
#define ENC_ERXNDH REGADDR(0x0b, 0) /* RX End High Byte (ERXND<12:8>) */
#define ENC_ERXRDPTL REGADDR(0x0c, 0) /* RX RD Pointer Low Byte (ERXRDPT<7:0>) */
#define ENC_ERXRDPTH REGADDR(0x0d, 0) /* RX RD Pointer High Byte (ERXRDPT<12:8>) */
#define ENC_ERXWRPTL REGADDR(0x0e, 0) /* RX WR Pointer Low Byte (ERXWRPT<7:0>) */
#define ENC_ERXWRPTH REGADDR(0x0f, 0) /* RX WR Pointer High Byte (ERXWRPT<12:8>) */
#define ENC_EDMASTL REGADDR(0x10, 0) /* DMA Start Low Byte (EDMAST<7:0>) */
#define ENC_EDMASTH REGADDR(0x11, 0) /* DMA Start High Byte (EDMAST<12:8>) */
#define ENC_EDMANDL REGADDR(0x12, 0) /* DMA End Low Byte (EDMAND<7:0>) */
#define ENC_EDMANDH REGADDR(0x13, 0) /* DMA End High Byte (EDMAND<12:8>) */
#define ENC_EDMADSTL REGADDR(0x14, 0) /* DMA Destination Low Byte (EDMADST<7:0>) */
#define ENC_EDMADSTH REGADDR(0x15, 0) /* DMA Destination High Byte (EDMADST<12:8>) */
#define ENC_EDMACSL REGADDR(0x16, 0) /* DMA Checksum Low Byte (EDMACS<7:0>) */
#define ENC_EDMACSH REGADDR(0x17, 0) /* DMA Checksum High Byte (EDMACS<15:8>) */
/* 0x18-0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
#define ENC_ERDPTL REGADDR(0x00, 0, 0) /* Read Pointer Low Byte (ERDPT<7:0> */
#define ENC_ERDPTH REGADDR(0x01, 0, 0) /* Read Pointer High Byte (ERDPT<12:8>) */
#define ENC_EWRPTL REGADDR(0x02, 0, 0) /* Write Pointer Low Byte (EWRPT<7:0>) */
#define ENC_EWRPTH REGADDR(0x03, 0, 0) /* Write Pointer High Byte (EWRPT<12:8>) */
#define ENC_ETXSTL REGADDR(0x04, 0, 0) /* TX Start Low Byte (ETXST<7:0>) */
#define ENC_ETXSTH REGADDR(0x05, 0, 0) /* TX Start High Byte (ETXST<12:8>) */
#define ENC_ETXNDL REGADDR(0x06, 0, 0) /* TX End Low Byte (ETXND<7:0>) */
#define ENC_ETXNDH REGADDR(0x07, 0, 0) /* TX End High Byte (ETXND<12:8>) */
#define ENC_ERXSTL REGADDR(0x08, 0, 0) /* RX Start Low Byte (ERXST<7:0>) */
#define ENC_ERXSTH REGADDR(0x09, 0, 0) /* RX Start High Byte (ERXST<12:8>) */
#define ENC_ERXNDL REGADDR(0x0a, 0, 0) /* RX End Low Byte (ERXND<7:0>) */
#define ENC_ERXNDH REGADDR(0x0b, 0, 0) /* RX End High Byte (ERXND<12:8>) */
#define ENC_ERXRDPTL REGADDR(0x0c, 0, 0) /* RX RD Pointer Low Byte (ERXRDPT<7:0>) */
#define ENC_ERXRDPTH REGADDR(0x0d, 0, 0) /* RX RD Pointer High Byte (ERXRDPT<12:8>) */
#define ENC_ERXWRPTL REGADDR(0x0e, 0, 0) /* RX WR Pointer Low Byte (ERXWRPT<7:0>) */
#define ENC_ERXWRPTH REGADDR(0x0f, 0, 0) /* RX WR Pointer High Byte (ERXWRPT<12:8>) */
#define ENC_EDMASTL REGADDR(0x10, 0, 0) /* DMA Start Low Byte (EDMAST<7:0>) */
#define ENC_EDMASTH REGADDR(0x11, 0, 0) /* DMA Start High Byte (EDMAST<12:8>) */
#define ENC_EDMANDL REGADDR(0x12, 0, 0) /* DMA End Low Byte (EDMAND<7:0>) */
#define ENC_EDMANDH REGADDR(0x13, 0, 0) /* DMA End High Byte (EDMAND<12:8>) */
#define ENC_EDMADSTL REGADDR(0x14, 0, 0) /* DMA Destination Low Byte (EDMADST<7:0>) */
#define ENC_EDMADSTH REGADDR(0x15, 0, 0) /* DMA Destination High Byte (EDMADST<12:8>) */
#define ENC_EDMACSL REGADDR(0x16, 0, 0) /* DMA Checksum Low Byte (EDMACS<7:0>) */
#define ENC_EDMACSH REGADDR(0x17, 0, 0) /* DMA Checksum High Byte (EDMACS<15:8>) */
/* 0x18-0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
/* Bank 1 Control Register Addresses */
#define ENC_EHT0 REGADDR(0x00, 1) /* Hash Table Byte 0 (EHT<7:0>) */
#define ENC_EHT1 REGADDR(0x01, 1) /* Hash Table Byte 1 (EHT<15:8>) */
#define ENC_EHT2 REGADDR(0x02, 1) /* Hash Table Byte 2 (EHT<23:16>) */
#define ENC_EHT3 REGADDR(0x03, 1) /* Hash Table Byte 3 (EHT<31:24>) */
#define ENC_EHT4 REGADDR(0x04, 1) /* Hash Table Byte 4 (EHT<39:32>) */
#define ENC_EHT5 REGADDR(0x05, 1) /* Hash Table Byte 5 (EHT<47:40>) */
#define ENC_EHT6 REGADDR(0x06, 1) /* Hash Table Byte 6 (EHT<55:48>) */
#define ENC_EHT7 REGADDR(0x07, 1) /* Hash Table Byte 7 (EHT<63:56>) */
#define ENC_EPMM0 REGADDR(0x08, 1) /* Pattern Match Mask Byte 0 (EPMM<7:0>) */
#define ENC_EPMM1 REGADDR(0x09, 1) /* Pattern Match Mask Byte 1 (EPMM<15:8>) */
#define ENC_EPMM2 REGADDR(0x0a, 1) /* Pattern Match Mask Byte 2 (EPMM<23:16>) */
#define ENC_EPMM3 REGADDR(0x0b, 1) /* Pattern Match Mask Byte 3 (EPMM<31:24>) */
#define ENC_EPMM4 REGADDR(0x0c, 1) /* Pattern Match Mask Byte 4 (EPMM<39:32>) */
#define ENC_EPMM5 REGADDR(0x0d, 1) /* Pattern Match Mask Byte 5 (EPMM<47:40>) */
#define ENC_EPMM6 REGADDR(0x0e, 1) /* Pattern Match Mask Byte 6 (EPMM<55:48>) */
#define ENC_EPMM7 REGADDR(0x0f, 1) /* Pattern Match Mask Byte 7 (EPMM<63:56>) */
#define ENC_EPMCSL REGADDR(0x10, 1) /* Pattern Match Checksum Low Byte (EPMCS<7:0>) */
#define ENC_EPMCSH REGADDR(0x11, 1) /* Pattern Match Checksum High Byte (EPMCS<15:0>) */
/* 0x12-0x13: Reserved */
#define ENC_EPMOL REGADDR(0x14, 1) /* Pattern Match Offset Low Byte (EPMO<7:0>) */
#define ENC_EPMOH REGADDR(0x15, 1) /* Pattern Match Offset High Byte (EPMO<12:8>) */
/* 0x16-0x17: Reserved */
#define ENC_ERXFCON REGADDR(0x18, 1) /* Receive Filter Configuration */
#define ENC_EPKTCNT REGADDR(0x19, 1) /* Ethernet Packet Count */
/* 0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
#define ENC_EHT0 REGADDR(0x00, 1, 0) /* Hash Table Byte 0 (EHT<7:0>) */
#define ENC_EHT1 REGADDR(0x01, 1, 0) /* Hash Table Byte 1 (EHT<15:8>) */
#define ENC_EHT2 REGADDR(0x02, 1, 0) /* Hash Table Byte 2 (EHT<23:16>) */
#define ENC_EHT3 REGADDR(0x03, 1, 0) /* Hash Table Byte 3 (EHT<31:24>) */
#define ENC_EHT4 REGADDR(0x04, 1, 0) /* Hash Table Byte 4 (EHT<39:32>) */
#define ENC_EHT5 REGADDR(0x05, 1, 0) /* Hash Table Byte 5 (EHT<47:40>) */
#define ENC_EHT6 REGADDR(0x06, 1, 0) /* Hash Table Byte 6 (EHT<55:48>) */
#define ENC_EHT7 REGADDR(0x07, 1, 0) /* Hash Table Byte 7 (EHT<63:56>) */
#define ENC_EPMM0 REGADDR(0x08, 1, 0) /* Pattern Match Mask Byte 0 (EPMM<7:0>) */
#define ENC_EPMM1 REGADDR(0x09, 1, 0) /* Pattern Match Mask Byte 1 (EPMM<15:8>) */
#define ENC_EPMM2 REGADDR(0x0a, 1, 0) /* Pattern Match Mask Byte 2 (EPMM<23:16>) */
#define ENC_EPMM3 REGADDR(0x0b, 1, 0) /* Pattern Match Mask Byte 3 (EPMM<31:24>) */
#define ENC_EPMM4 REGADDR(0x0c, 1, 0) /* Pattern Match Mask Byte 4 (EPMM<39:32>) */
#define ENC_EPMM5 REGADDR(0x0d, 1, 0) /* Pattern Match Mask Byte 5 (EPMM<47:40>) */
#define ENC_EPMM6 REGADDR(0x0e, 1, 0) /* Pattern Match Mask Byte 6 (EPMM<55:48>) */
#define ENC_EPMM7 REGADDR(0x0f, 1, 0) /* Pattern Match Mask Byte 7 (EPMM<63:56>) */
#define ENC_EPMCSL REGADDR(0x10, 1, 0) /* Pattern Match Checksum Low Byte (EPMCS<7:0>) */
#define ENC_EPMCSH REGADDR(0x11, 1, 0) /* Pattern Match Checksum High Byte (EPMCS<15:0>) */
/* 0x12-0x13: Reserved */
#define ENC_EPMOL REGADDR(0x14, 1, 0) /* Pattern Match Offset Low Byte (EPMO<7:0>) */
#define ENC_EPMOH REGADDR(0x15, 1, 0) /* Pattern Match Offset High Byte (EPMO<12:8>) */
/* 0x16-0x17: Reserved */
#define ENC_ERXFCON REGADDR(0x18, 1, 0) /* Receive Filter Configuration */
#define ENC_EPKTCNT REGADDR(0x19, 1, 0) /* Ethernet Packet Count */
/* 0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
/* Receive Filter Configuration Bit Definitions */
@ -239,29 +243,29 @@
/* Bank 2 Control Register Addresses */
#define ENC_MACON1 REGADDR(0x00, 2) /* MAC Control 1 */
/* 0x01: Reserved */
#define ENC_MACON3 REGADDR(0x02, 2) /* MAC Control 3 */
#define ENC_MACON4 REGADDR(0x03, 2) /* MAC Control 4 */
#define ENC_MABBIPG REGADDR(0x04, 2) /* Back-to-Back Inter-Packet Gap (BBIPG<6:0>) */
/* 0x05: Reserved */
#define ENC_MAIPGL REGADDR(0x06, 2) /* Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>) */
#define ENC_MAIPGH REGADDR(0x07, 2) /* Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>) */
#define ENC_MACLCON1 REGADDR(0x08, 2) /* MAC Collision Control 1 */
#define ENC_MACLCON2 REGADDR(0x09, 2) /* MAC Collision Control 2 */
#define ENC_MAMXFLL REGADDR(0x0a, 2) /* Maximum Frame Length Low Byte (MAMXFL<7:0>) */
#define ENC_MAMXFLH REGADDR(0x0b, 2) /* Maximum Frame Length High Byte (MAMXFL<15:8>) */
/* 0x0c-0x11: Reserved */
#define ENC_MICMD REGADDR(0x12, 2) /* MII Command Register */
/* 0x13: Reserved */
#define ENC_MIREGADR REGADDR(0x14, 2) /* MII Register Address */
/* 0x15: Reserved */
#define ENC_MIWRL REGADDR(0x16, 2) /* MII Write Data Low Byte (MIWR<7:0>) */
#define ENC_MIWRH REGADDR(0x17, 2) /* MII Write Data High Byte (MIWR<15:8>) */
#define ENC_MIRDL REGADDR(0x18, 2) /* MII Read Data Low Byte (MIRD<7:0>) */
#define ENC_MIRDH REGADDR(0x19, 2) /* MII Read Data High Byte(MIRD<15:8>) */
/* 0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
#define ENC_MACON1 REGADDR(0x00, 2, 1) /* MAC Control 1 */
/* 0x01: Reserved */
#define ENC_MACON3 REGADDR(0x02, 2, 1) /* MAC Control 3 */
#define ENC_MACON4 REGADDR(0x03, 2, 1) /* MAC Control 4 */
#define ENC_MABBIPG REGADDR(0x04, 2, 1) /* Back-to-Back Inter-Packet Gap (BBIPG<6:0>) */
/* 0x05: Reserved */
#define ENC_MAIPGL REGADDR(0x06, 2, 1) /* Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>) */
#define ENC_MAIPGH REGADDR(0x07, 2, 1) /* Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>) */
#define ENC_MACLCON1 REGADDR(0x08, 2, 1) /* MAC Collision Control 1 */
#define ENC_MACLCON2 REGADDR(0x09, 2, 1) /* MAC Collision Control 2 */
#define ENC_MAMXFLL REGADDR(0x0a, 2, 1) /* Maximum Frame Length Low Byte (MAMXFL<7:0>) */
#define ENC_MAMXFLH REGADDR(0x0b, 2, 1) /* Maximum Frame Length High Byte (MAMXFL<15:8>) */
/* 0x0c-0x11: Reserved */
#define ENC_MICMD REGADDR(0x12, 2, 1) /* MII Command Register */
/* 0x13: Reserved */
#define ENC_MIREGADR REGADDR(0x14, 2, 1) /* MII Register Address */
/* 0x15: Reserved */
#define ENC_MIWRL REGADDR(0x16, 2, 1) /* MII Write Data Low Byte (MIWR<7:0>) */
#define ENC_MIWRH REGADDR(0x17, 2, 1) /* MII Write Data High Byte (MIWR<15:8>) */
#define ENC_MIRDL REGADDR(0x18, 2, 1) /* MII Read Data Low Byte (MIRD<7:0>) */
#define ENC_MIRDH REGADDR(0x19, 2, 1) /* MII Read Data High Byte(MIRD<15:8>) */
/* 0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
/* MAC Control 1 Register Bit Definitions */
@ -295,27 +299,27 @@
/* Bank 3 Control Register Addresses */
#define ENC_MAADR5 REGADDR(0x00, 3) /* MAC Address Byte 5 (MAADR<15:8>) */
#define ENC_MAADR6 REGADDR(0x01, 3) /* MAC Address Byte 6 (MAADR<7:0>) */
#define ENC_MAADR3 REGADDR(0x02, 3) /* MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 */
#define ENC_MAADR4 REGADDR(0x03, 3) /* MAC Address Byte 4 (MAADR<23:16>) */
#define ENC_MAADR1 REGADDR(0x04, 3) /* MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 */
#define ENC_MAADR2 REGADDR(0x05, 3) /* MAC Address Byte 2 (MAADR<39:32>), OUI Byte */
#define ENC_EBSTSD REGADDR(0x06, 3) /* Built-in Self-Test Fill Seed (EBSTSD<7:0>) */
#define ENC_EBSTCON REGADDR(0x07, 3) /* Built-in Self-Test Control */
#define ENC_EBSTCSL REGADDR(0x08, 3) /* Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) */
#define ENC_EBSTCSH REGADDR(0x09, 3) /* Built-in Self-Test Checksum High Byte (EBSTCS<15:8>) */
#define ENC_MISTAT REGADDR(0x0a, 3) /* MII Status Register */
/* 0x0b-0x11: Reserved */
#define ENC_EREVID REGADDR(0x12, 3) /* Ethernet Revision ID */
/* 0x13-0x14: Reserved */
#define ENC_ECOCON REGADDR(0x15, 3) /* Clock Output Control */
/* 0x16: Reserved */
#define ENC_EFLOCON REGADDR(0x17, 3) /* Ethernet Flow Control */
#define ENC_EPAUSL REGADDR(0x18, 3) /* Pause Timer Value Low Byte (EPAUS<7:0>) */
#define ENC_EPAUSH REGADDR(0x19, 3) /* Pause Timer Value High Byte (EPAUS<15:8>) */
/* 0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
#define ENC_MAADR5 REGADDR(0x00, 3, 1) /* MAC Address Byte 5 (MAADR<15:8>) */
#define ENC_MAADR6 REGADDR(0x01, 3, 1) /* MAC Address Byte 6 (MAADR<7:0>) */
#define ENC_MAADR3 REGADDR(0x02, 3, 1) /* MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 */
#define ENC_MAADR4 REGADDR(0x03, 3, 1) /* MAC Address Byte 4 (MAADR<23:16>) */
#define ENC_MAADR1 REGADDR(0x04, 3, 1) /* MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 */
#define ENC_MAADR2 REGADDR(0x05, 3, 1) /* MAC Address Byte 2 (MAADR<39:32>), OUI Byte */
#define ENC_EBSTSD REGADDR(0x06, 3, 0) /* Built-in Self-Test Fill Seed (EBSTSD<7:0>) */
#define ENC_EBSTCON REGADDR(0x07, 3, 0) /* Built-in Self-Test Control */
#define ENC_EBSTCSL REGADDR(0x08, 3, 0) /* Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) */
#define ENC_EBSTCSH REGADDR(0x09, 3, 0) /* Built-in Self-Test Checksum High Byte (EBSTCS<15:8>) */
#define ENC_MISTAT REGADDR(0x0a, 3, 1) /* MII Status Register */
/* 0x0b-0x11: Reserved */
#define ENC_EREVID REGADDR(0x12, 3, 0) /* Ethernet Revision ID */
/* 0x13-0x14: Reserved */
#define ENC_ECOCON REGADDR(0x15, 3, 0) /* Clock Output Control */
/* 0x16: Reserved */
#define ENC_EFLOCON REGADDR(0x17, 3, 0) /* Ethernet Flow Control */
#define ENC_EPAUSL REGADDR(0x18, 3, 0) /* Pause Timer Value Low Byte (EPAUS<7:0>) */
#define ENC_EPAUSH REGADDR(0x19, 3, 0) /* Pause Timer Value High Byte (EPAUS<15:8>) */
/* 0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
/* Built-in Self-Test Control Register Bit Definitions */