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configs/metro-m4: Corrrect SERCOM3 pin configuration

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This commit is contained in:
Gregory Nutt 2018-08-01 14:56:11 -06:00
parent 8876f9cdae
commit 5dec4a6763
2 changed files with 8 additions and 8 deletions
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4
arch/arm/src/stm32l4/stm32l4_i2c.c
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@ -2649,9 +2649,9 @@ static int stm32l4_i2c_process(FAR struct i2c_master_s *dev,
status = stm32l4_i2c_getstatus(priv); status = stm32l4_i2c_getstatus(priv);
while(status & I2C_ISR_BUSY) while (status & I2C_ISR_BUSY)
{ {
if((clock_systimer() - start) > timeout) if ((clock_systimer() - start) > timeout)
{ {
i2cerr("ERROR: I2C Bus busy"); i2cerr("ERROR: I2C Bus busy");
errval = EBUSY; errval = EBUSY;

12
configs/metro-m4/include/board.h
View File

@ -425,22 +425,22 @@
* ------ ----------------- --------- * ------ ----------------- ---------
* SHIELD SAMD5E5 FUNCTION * SHIELD SAMD5E5 FUNCTION
* ------ ----------------- --------- * ------ ----------------- ---------
* D0 PA23 SERCOM3 PAD2 RXD * D0 PA23 SERCOM3 PAD1 RXD
* D1 PA22 SERCOM3 PAD0 TXD * D1 PA22 SERCOM3 PAD0 TXD
* *
* NOTES: * NOTES:
* USART_CTRLA_TXPAD0_1: TxD=PAD0 XCK=PAD1 RTS/TE=N/A CTS=N/A * USART_CTRLA_TXPAD0_1: TxD=PAD0XCK=N/A RTS/TE=PAD2 CTS=PAD3
* USART_CTRLA_RXPAD2: RxD=PAD2 * USART_CTRLA_RXPAD2: RxD=PAD1
*/ */
#define BOARD_SERCOM3_MUXCONFIG (USART_CTRLA_TXPAD0_1 | USART_CTRLA_RXPAD2) #define BOARD_SERCOM3_MUXCONFIG (USART_CTRLA_TXPAD0_2 | USART_CTRLA_RXPAD2)
#define BOARD_SERCOM3_PINMAP_PAD0 PORT_SERCOM3_PAD0_1 /* USART TX */ #define BOARD_SERCOM3_PINMAP_PAD0 PORT_SERCOM3_PAD0_1 /* USART TX */
#define BOARD_SERCOM3_PINMAP_PAD1 PORT_SERCOM3_PAD2_1 /* USART RX */ #define BOARD_SERCOM3_PINMAP_PAD1 PORT_SERCOM3_PAD1_1 /* USART RX */
#define BOARD_SERCOM3_PINMAP_PAD2 0 /* (not used) */ #define BOARD_SERCOM3_PINMAP_PAD2 0 /* (not used) */
#define BOARD_SERCOM3_PINMAP_PAD3 0 /* (not used) */ #define BOARD_SERCOM3_PINMAP_PAD3 0 /* (not used) */
#define BOARD_TXIRQ_SERCOM3 SAM_IRQ_SERCOM3_0 #define BOARD_TXIRQ_SERCOM3 SAM_IRQ_SERCOM3_0
#define BOARD_RXIRQ_SERCOM3 SAM_IRQ_SERCOM3_2 #define BOARD_RXIRQ_SERCOM3 SAM_IRQ_SERCOM3_1
#define BOARD_SERCOM3_COREGEN 1 /* 48MHz, common to all SERCOMS */ #define BOARD_SERCOM3_COREGEN 1 /* 48MHz, common to all SERCOMS */
#define BOARD_SERCOM3_SLOWGEN 3 /* 48MHz */ #define BOARD_SERCOM3_SLOWGEN 3 /* 48MHz */