Misc changes to get a clean compilation after incorporating all of Bob Doison's changes
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066cca1863
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@ -133,10 +133,6 @@
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_TC1_EMR (SAM_TC1_BASE+SAM_TC_EMR_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_TC1_FMR (SAM_TC1_BASE+SAM_TC_FMR_OFFSET)
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# define SAM_TC1_WPMR (SAM_TC1_BASE+SAM_TC_WPMR_OFFSET)
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#endif
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#define SAM_TC2_CCR (SAM_TC2_BASE+SAM_TC_CCR_OFFSET)
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#define SAM_TC2_CMR (SAM_TC2_BASE+SAM_TC_CMR_OFFSET)
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@ -157,10 +153,6 @@
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_TC2_EMR (SAM_TC2_BASE+SAM_TC_EMR_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_TC2_FMR (SAM_TC2_BASE+SAM_TC_FMR_OFFSET)
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# define SAM_TC2_WPMR (SAM_TC2_BASE+SAM_TC_WPMR_OFFSET)
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#endif
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#define SAM_TC3_CCR (SAM_TC3_BASE+SAM_TC_CCR_OFFSET)
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#define SAM_TC3_CMR (SAM_TC3_BASE+SAM_TC_CMR_OFFSET)
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@ -181,10 +173,6 @@
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_TC3_EMR (SAM_TC3_BASE+SAM_TC_EMR_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_TC3_FMR (SAM_TC3_BASE+SAM_TC_FMR_OFFSET)
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# define SAM_TC3_WPMR (SAM_TC3_BASE+SAM_TC_WPMR_OFFSET)
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#endif
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#define SAM_TC4_CCR (SAM_TC4_BASE+SAM_TC_CCR_OFFSET)
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#define SAM_TC4_CMR (SAM_TC4_BASE+SAM_TC_CMR_OFFSET)
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@ -205,10 +193,6 @@
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_TC4_EMR (SAM_TC4_BASE+SAM_TC_EMR_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_TC4_FMR (SAM_TC4_BASE+SAM_TC_FMR_OFFSET)
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# define SAM_TC4_WPMR (SAM_TC4_BASE+SAM_TC_WPMR_OFFSET)
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#endif
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#define SAM_TC5_CCR (SAM_TC5_BASE+SAM_TC_CCR_OFFSET)
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#define SAM_TC5_CMR (SAM_TC5_BASE+SAM_TC_CMR_OFFSET)
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@ -229,10 +213,6 @@
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_TC5_EMR (SAM_TC5_BASE+SAM_TC_EMR_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_TC5_FMR (SAM_TC5_BASE+SAM_TC_FMR_OFFSET)
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# define SAM_TC5_WPMR (SAM_TC5_BASE+SAM_TC_WPMR_OFFSET)
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#endif
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#define SAM_TC6_CCR (SAM_TC6_BASE+SAM_TC_CCR_OFFSET)
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#define SAM_TC6_CMR (SAM_TC6_BASE+SAM_TC_CMR_OFFSET)
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@ -297,23 +277,32 @@
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/* Timer common registers */
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_TC0_BCR (SAM_TC0_BASE+SAM_TC_BCR_OFFSET)
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# define SAM_TC0_BMR (SAM_TC0_BASE+SAM_TC_BMR_OFFSET)
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# define SAM_TC0_QIER (SAM_TC0_BASE+SAM_TC_QIER_OFFSET)
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# define SAM_TC0_QIDR (SAM_TC0_BASE+SAM_TC_QIDR_OFFSET)
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# define SAM_TC0_QIMR (SAM_TC0_BASE+SAM_TC_QIMR_OFFSET)
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# define SAM_TC0_QISR (SAM_TC0_BASE+SAM_TC_QISR_OFFSET)
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# define SAM_TC0_FMR (SAM_TC0_BASE+SAM_TC_FMR_OFFSET)
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# define SAM_TC0_WPMR (SAM_TC0_BASE+SAM_TC_WPMR_OFFSET)
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# define SAM_TC0_BCR (SAM_TC012_BASE+SAM_TC_BCR_OFFSET)
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# define SAM_TC0_BMR (SAM_TC012_BASE+SAM_TC_BMR_OFFSET)
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# define SAM_TC0_QIER (SAM_TC012_BASE+SAM_TC_QIER_OFFSET)
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# define SAM_TC0_QIDR (SAM_TC012_BASE+SAM_TC_QIDR_OFFSET)
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# define SAM_TC0_QIMR (SAM_TC012_BASE+SAM_TC_QIMR_OFFSET)
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# define SAM_TC0_QISR (SAM_TC012_BASE+SAM_TC_QISR_OFFSET)
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# define SAM_TC0_FMR (SAM_TC012_BASE+SAM_TC_FMR_OFFSET)
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# define SAM_TC0_WPMR (SAM_TC012_BASE+SAM_TC_WPMR_OFFSET)
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# define SAM_TC1_BCR (SAM_TC3_BASE+SAM_TC_BCR_OFFSET)
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# define SAM_TC1_BMR (SAM_TC3_BASE+SAM_TC_BMR_OFFSET)
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# define SAM_TC1_QIER (SAM_TC3_BASE+SAM_TC_QIER_OFFSET)
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# define SAM_TC1_QIDR (SAM_TC3_BASE+SAM_TC_QIDR_OFFSET)
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# define SAM_TC1_QIMR (SAM_TC3_BASE+SAM_TC_QIMR_OFFSET)
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# define SAM_TC1_QISR (SAM_TC3_BASE+SAM_TC_QISR_OFFSET)
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# define SAM_TC1_FMR (SAM_TC3_BASE+SAM_TC_FMR_OFFSET)
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# define SAM_TC1_WPMR (SAM_TC3_BASE+SAM_TC_WPMR_OFFSET)
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# define SAM_TC1_BCR (SAM_TC345_BASE+SAM_TC_BCR_OFFSET)
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# define SAM_TC1_BMR (SAM_TC345_BASE+SAM_TC_BMR_OFFSET)
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# define SAM_TC1_QIER (SAM_TC345_BASE+SAM_TC_QIER_OFFSET)
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# define SAM_TC1_QIDR (SAM_TC345_BASE+SAM_TC_QIDR_OFFSET)
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# define SAM_TC1_QIMR (SAM_TC345_BASE+SAM_TC_QIMR_OFFSET)
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# define SAM_TC1_QISR (SAM_TC345_BASE+SAM_TC_QISR_OFFSET)
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# define SAM_TC1_FMR (SAM_TC345_BASE+SAM_TC_FMR_OFFSET)
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# define SAM_TC1_WPMR (SAM_TC345_BASE+SAM_TC_WPMR_OFFSET)
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# define SAM_TC2_BCR (SAM_TC678_BASE+SAM_TC_BCR_OFFSET)
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# define SAM_TC2_BMR (SAM_TC678_BASE+SAM_TC_BMR_OFFSET)
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# define SAM_TC2_QIER (SAM_TC678_BASE+SAM_TC_QIER_OFFSET)
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# define SAM_TC2_QIDR (SAM_TC678_BASE+SAM_TC_QIDR_OFFSET)
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# define SAM_TC2_QIMR (SAM_TC678_BASE+SAM_TC_QIMR_OFFSET)
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# define SAM_TC2_QISR (SAM_TC678_BASE+SAM_TC_QISR_OFFSET)
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# define SAM_TC2_FMR (SAM_TC678_BASE+SAM_TC_FMR_OFFSET)
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# define SAM_TC2_WPMR (SAM_TC678_BASE+SAM_TC_WPMR_OFFSET)
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#else
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# define SAM_TC_BCR (SAM_TC_BASE+SAM_TC_BCR_OFFSET)
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# define SAM_TC_BMR (SAM_TC_BASE+SAM_TC_BMR_OFFSET)
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@ -129,7 +129,7 @@ int up_timerisr(int irq, uint32_t *regs)
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}
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/****************************************************************************
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* Function: up_timerinit
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* Function: up_timerinitialize
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*
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* Description:
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* This function is called during start-up to initialize
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@ -137,7 +137,7 @@ int up_timerisr(int irq, uint32_t *regs)
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*
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****************************************************************************/
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void up_timerinit(void)
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void up_timerinitialize(void)
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{
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uint32_t regval;
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@ -4,4 +4,10 @@
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#
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if ARCH_BOARD_SAM4S_XPLAINED_PRO
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config SAM4S_XPLAINED_PRO_CDCACM_DEVMINOR
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int "CDC/ACM Device Minor"
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default 0
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depends on SAM34_UDP && USBDEV && CDCACM
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endif
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@ -341,6 +341,7 @@ CONFIG_NSH_MMCSDSLOTNO=0
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#
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# Board-Specific Options
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#
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CONFIG_SAM4S_XPLAINED_PRO_CDCACM_DEVMINOR=0
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#
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# RTOS Features
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@ -574,7 +575,6 @@ CONFIG_ARCH_USBDEV_STALLQUEUE=y
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# CONFIG_USBDEV_COMPOSITE is not set
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# CONFIG_PL2303 is not set
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CONFIG_CDCACM=y
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CONFIG_CDCACM_DEVMINOR=0
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# CONFIG_CDCACM_CONSOLE is not set
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CONFIG_CDCACM_EP0MAXPACKET=64
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CONFIG_CDCACM_EPINTIN=1
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@ -747,6 +747,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
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# CONFIG_EXAMPLES_CAN is not set
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# CONFIG_EXAMPLES_CONFIGDATA is not set
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CONFIG_EXAMPLES_CPUHOG=y
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CONFIG_EXAMPLES_CPUHOG_STACKSIZE=2048
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CONFIG_EXAMPLES_CPUHOG_PRIORITY=50
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# CONFIG_EXAMPLES_CXXTEST is not set
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# CONFIG_EXAMPLES_DHCPD is not set
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# CONFIG_EXAMPLES_ELF is not set
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@ -783,6 +785,8 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
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# CONFIG_EXAMPLES_SENDMAIL is not set
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CONFIG_EXAMPLES_SERIALBLASTER=y
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CONFIG_EXAMPLES_SERIALRX=y
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CONFIG_EXAMPLES_SERIALRX_STACKSIZE=2048
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CONFIG_EXAMPLES_SERIALRX_PRIORITY=50
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# CONFIG_EXAMPLES_SERLOOP is not set
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# CONFIG_EXAMPLES_SLCD is not set
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# CONFIG_EXAMPLES_SMART_TEST is not set
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@ -73,7 +73,7 @@ CSRCS += sam_wdt.c
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endif
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ifeq ($(CONFIG_TIMER),y)
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CSRCS += sam_tc.c
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# CSRCS += sam_tc.c
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endif
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COBJS = $(CSRCS:.c=$(OBJEXT))
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@ -108,7 +108,7 @@ int nsh_archinitialize(void)
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#ifdef HAVE_USBDEV
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message("Registering CDC/ACM serial driver\n");
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ret = cdcacm_initialize(CONFIG_CDCACM_DEVMINOR, NULL);
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ret = cdcacm_initialize(CONFIG_SAM4S_XPLAINED_PRO_CDCACM_DEVMINOR, NULL);
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if (ret < 0)
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{
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message("ERROR: Failed to create the CDC/ACM serial device: %d\n", errno);
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@ -210,7 +210,6 @@ static int timer_close(FAR struct file *filep)
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{
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upper->crefs--;
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}
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#warning "anythin uninit to do on last close?"
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//sem_post(&upper->exclsem);
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ret = OK;
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@ -466,7 +465,7 @@ static int timer_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
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****************************************************************************/
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FAR void *timer_register(FAR const char *path,
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FAR struct timer_lowerhalf_s *lower)
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FAR struct timer_lowerhalf_s *lower)
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{
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FAR struct timer_upperhalf_s *upper;
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int ret;
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@ -558,7 +558,7 @@ static int procfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir)
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FAR struct procfs_dir_priv_s *priv;
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FAR struct procfs_level0_s *level0;
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FAR struct tcb_s *tcb;
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FAR const char *name;
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FAR const char *name = NULL;
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unsigned int index;
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irqstate_t flags;
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pid_t pid;
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@ -1287,7 +1287,7 @@ static int proc_closedir(FAR struct fs_dirent_s *dir)
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static int proc_readdir(struct fs_dirent_s *dir)
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{
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FAR struct proc_dir_s *procdir;
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FAR const struct proc_node_s *node;
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FAR const struct proc_node_s *node = NULL;
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FAR struct tcb_s *tcb;
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unsigned int index;
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irqstate_t flags;
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