Misc changes to get a clean compilation after incorporating all of Bob Doison's changes

This commit is contained in:
Gregory Nutt 2014-04-22 10:38:08 -06:00
parent 066cca1863
commit 5df14c7d40
9 changed files with 43 additions and 45 deletions

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@ -133,10 +133,6 @@
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC1_EMR (SAM_TC1_BASE+SAM_TC_EMR_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC1_FMR (SAM_TC1_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC1_WPMR (SAM_TC1_BASE+SAM_TC_WPMR_OFFSET)
#endif
#define SAM_TC2_CCR (SAM_TC2_BASE+SAM_TC_CCR_OFFSET)
#define SAM_TC2_CMR (SAM_TC2_BASE+SAM_TC_CMR_OFFSET)
@ -157,10 +153,6 @@
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC2_EMR (SAM_TC2_BASE+SAM_TC_EMR_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC2_FMR (SAM_TC2_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC2_WPMR (SAM_TC2_BASE+SAM_TC_WPMR_OFFSET)
#endif
#define SAM_TC3_CCR (SAM_TC3_BASE+SAM_TC_CCR_OFFSET)
#define SAM_TC3_CMR (SAM_TC3_BASE+SAM_TC_CMR_OFFSET)
@ -181,10 +173,6 @@
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC3_EMR (SAM_TC3_BASE+SAM_TC_EMR_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC3_FMR (SAM_TC3_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC3_WPMR (SAM_TC3_BASE+SAM_TC_WPMR_OFFSET)
#endif
#define SAM_TC4_CCR (SAM_TC4_BASE+SAM_TC_CCR_OFFSET)
#define SAM_TC4_CMR (SAM_TC4_BASE+SAM_TC_CMR_OFFSET)
@ -205,10 +193,6 @@
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC4_EMR (SAM_TC4_BASE+SAM_TC_EMR_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC4_FMR (SAM_TC4_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC4_WPMR (SAM_TC4_BASE+SAM_TC_WPMR_OFFSET)
#endif
#define SAM_TC5_CCR (SAM_TC5_BASE+SAM_TC_CCR_OFFSET)
#define SAM_TC5_CMR (SAM_TC5_BASE+SAM_TC_CMR_OFFSET)
@ -229,10 +213,6 @@
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC5_EMR (SAM_TC5_BASE+SAM_TC_EMR_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC5_FMR (SAM_TC5_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC5_WPMR (SAM_TC5_BASE+SAM_TC_WPMR_OFFSET)
#endif
#define SAM_TC6_CCR (SAM_TC6_BASE+SAM_TC_CCR_OFFSET)
#define SAM_TC6_CMR (SAM_TC6_BASE+SAM_TC_CMR_OFFSET)
@ -297,23 +277,32 @@
/* Timer common registers */
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC0_BCR (SAM_TC0_BASE+SAM_TC_BCR_OFFSET)
# define SAM_TC0_BMR (SAM_TC0_BASE+SAM_TC_BMR_OFFSET)
# define SAM_TC0_QIER (SAM_TC0_BASE+SAM_TC_QIER_OFFSET)
# define SAM_TC0_QIDR (SAM_TC0_BASE+SAM_TC_QIDR_OFFSET)
# define SAM_TC0_QIMR (SAM_TC0_BASE+SAM_TC_QIMR_OFFSET)
# define SAM_TC0_QISR (SAM_TC0_BASE+SAM_TC_QISR_OFFSET)
# define SAM_TC0_FMR (SAM_TC0_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC0_WPMR (SAM_TC0_BASE+SAM_TC_WPMR_OFFSET)
# define SAM_TC0_BCR (SAM_TC012_BASE+SAM_TC_BCR_OFFSET)
# define SAM_TC0_BMR (SAM_TC012_BASE+SAM_TC_BMR_OFFSET)
# define SAM_TC0_QIER (SAM_TC012_BASE+SAM_TC_QIER_OFFSET)
# define SAM_TC0_QIDR (SAM_TC012_BASE+SAM_TC_QIDR_OFFSET)
# define SAM_TC0_QIMR (SAM_TC012_BASE+SAM_TC_QIMR_OFFSET)
# define SAM_TC0_QISR (SAM_TC012_BASE+SAM_TC_QISR_OFFSET)
# define SAM_TC0_FMR (SAM_TC012_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC0_WPMR (SAM_TC012_BASE+SAM_TC_WPMR_OFFSET)
# define SAM_TC1_BCR (SAM_TC3_BASE+SAM_TC_BCR_OFFSET)
# define SAM_TC1_BMR (SAM_TC3_BASE+SAM_TC_BMR_OFFSET)
# define SAM_TC1_QIER (SAM_TC3_BASE+SAM_TC_QIER_OFFSET)
# define SAM_TC1_QIDR (SAM_TC3_BASE+SAM_TC_QIDR_OFFSET)
# define SAM_TC1_QIMR (SAM_TC3_BASE+SAM_TC_QIMR_OFFSET)
# define SAM_TC1_QISR (SAM_TC3_BASE+SAM_TC_QISR_OFFSET)
# define SAM_TC1_FMR (SAM_TC3_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC1_WPMR (SAM_TC3_BASE+SAM_TC_WPMR_OFFSET)
# define SAM_TC1_BCR (SAM_TC345_BASE+SAM_TC_BCR_OFFSET)
# define SAM_TC1_BMR (SAM_TC345_BASE+SAM_TC_BMR_OFFSET)
# define SAM_TC1_QIER (SAM_TC345_BASE+SAM_TC_QIER_OFFSET)
# define SAM_TC1_QIDR (SAM_TC345_BASE+SAM_TC_QIDR_OFFSET)
# define SAM_TC1_QIMR (SAM_TC345_BASE+SAM_TC_QIMR_OFFSET)
# define SAM_TC1_QISR (SAM_TC345_BASE+SAM_TC_QISR_OFFSET)
# define SAM_TC1_FMR (SAM_TC345_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC1_WPMR (SAM_TC345_BASE+SAM_TC_WPMR_OFFSET)
# define SAM_TC2_BCR (SAM_TC678_BASE+SAM_TC_BCR_OFFSET)
# define SAM_TC2_BMR (SAM_TC678_BASE+SAM_TC_BMR_OFFSET)
# define SAM_TC2_QIER (SAM_TC678_BASE+SAM_TC_QIER_OFFSET)
# define SAM_TC2_QIDR (SAM_TC678_BASE+SAM_TC_QIDR_OFFSET)
# define SAM_TC2_QIMR (SAM_TC678_BASE+SAM_TC_QIMR_OFFSET)
# define SAM_TC2_QISR (SAM_TC678_BASE+SAM_TC_QISR_OFFSET)
# define SAM_TC2_FMR (SAM_TC678_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC2_WPMR (SAM_TC678_BASE+SAM_TC_WPMR_OFFSET)
#else
# define SAM_TC_BCR (SAM_TC_BASE+SAM_TC_BCR_OFFSET)
# define SAM_TC_BMR (SAM_TC_BASE+SAM_TC_BMR_OFFSET)

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@ -129,7 +129,7 @@ int up_timerisr(int irq, uint32_t *regs)
}
/****************************************************************************
* Function: up_timerinit
* Function: up_timerinitialize
*
* Description:
* This function is called during start-up to initialize
@ -137,7 +137,7 @@ int up_timerisr(int irq, uint32_t *regs)
*
****************************************************************************/
void up_timerinit(void)
void up_timerinitialize(void)
{
uint32_t regval;

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@ -4,4 +4,10 @@
#
if ARCH_BOARD_SAM4S_XPLAINED_PRO
config SAM4S_XPLAINED_PRO_CDCACM_DEVMINOR
int "CDC/ACM Device Minor"
default 0
depends on SAM34_UDP && USBDEV && CDCACM
endif

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@ -341,6 +341,7 @@ CONFIG_NSH_MMCSDSLOTNO=0
#
# Board-Specific Options
#
CONFIG_SAM4S_XPLAINED_PRO_CDCACM_DEVMINOR=0
#
# RTOS Features
@ -574,7 +575,6 @@ CONFIG_ARCH_USBDEV_STALLQUEUE=y
# CONFIG_USBDEV_COMPOSITE is not set
# CONFIG_PL2303 is not set
CONFIG_CDCACM=y
CONFIG_CDCACM_DEVMINOR=0
# CONFIG_CDCACM_CONSOLE is not set
CONFIG_CDCACM_EP0MAXPACKET=64
CONFIG_CDCACM_EPINTIN=1
@ -747,6 +747,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
# CONFIG_EXAMPLES_CAN is not set
# CONFIG_EXAMPLES_CONFIGDATA is not set
CONFIG_EXAMPLES_CPUHOG=y
CONFIG_EXAMPLES_CPUHOG_STACKSIZE=2048
CONFIG_EXAMPLES_CPUHOG_PRIORITY=50
# CONFIG_EXAMPLES_CXXTEST is not set
# CONFIG_EXAMPLES_DHCPD is not set
# CONFIG_EXAMPLES_ELF is not set
@ -783,6 +785,8 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
# CONFIG_EXAMPLES_SENDMAIL is not set
CONFIG_EXAMPLES_SERIALBLASTER=y
CONFIG_EXAMPLES_SERIALRX=y
CONFIG_EXAMPLES_SERIALRX_STACKSIZE=2048
CONFIG_EXAMPLES_SERIALRX_PRIORITY=50
# CONFIG_EXAMPLES_SERLOOP is not set
# CONFIG_EXAMPLES_SLCD is not set
# CONFIG_EXAMPLES_SMART_TEST is not set

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@ -73,7 +73,7 @@ CSRCS += sam_wdt.c
endif
ifeq ($(CONFIG_TIMER),y)
CSRCS += sam_tc.c
# CSRCS += sam_tc.c
endif
COBJS = $(CSRCS:.c=$(OBJEXT))

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@ -108,7 +108,7 @@ int nsh_archinitialize(void)
#ifdef HAVE_USBDEV
message("Registering CDC/ACM serial driver\n");
ret = cdcacm_initialize(CONFIG_CDCACM_DEVMINOR, NULL);
ret = cdcacm_initialize(CONFIG_SAM4S_XPLAINED_PRO_CDCACM_DEVMINOR, NULL);
if (ret < 0)
{
message("ERROR: Failed to create the CDC/ACM serial device: %d\n", errno);

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@ -210,7 +210,6 @@ static int timer_close(FAR struct file *filep)
{
upper->crefs--;
}
#warning "anythin uninit to do on last close?"
//sem_post(&upper->exclsem);
ret = OK;
@ -466,7 +465,7 @@ static int timer_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
****************************************************************************/
FAR void *timer_register(FAR const char *path,
FAR struct timer_lowerhalf_s *lower)
FAR struct timer_lowerhalf_s *lower)
{
FAR struct timer_upperhalf_s *upper;
int ret;

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@ -558,7 +558,7 @@ static int procfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir)
FAR struct procfs_dir_priv_s *priv;
FAR struct procfs_level0_s *level0;
FAR struct tcb_s *tcb;
FAR const char *name;
FAR const char *name = NULL;
unsigned int index;
irqstate_t flags;
pid_t pid;

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@ -1287,7 +1287,7 @@ static int proc_closedir(FAR struct fs_dirent_s *dir)
static int proc_readdir(struct fs_dirent_s *dir)
{
FAR struct proc_dir_s *procdir;
FAR const struct proc_node_s *node;
FAR const struct proc_node_s *node = NULL;
FAR struct tcb_s *tcb;
unsigned int index;
irqstate_t flags;