Numerous fixes for basic STM32 SDIO DMA access
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2279 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
f702470d68
commit
5df8a7a194
@ -124,6 +124,19 @@ void up_initialize(void)
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up_irqinitialize();
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/* Initialize the DMA subsystem if the weak function stm32_dmainitialize has been
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* brought into the build
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*/
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#ifdef CONFIG_ARCH_DMA
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#ifdef CONFIG_HAVE_WEAKFUNCTIONS
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if (up_dmainitialize)
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#endif
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{
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up_dmainitialize();
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}
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#endif
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/* Initialize the system timer interrupt */
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#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS)
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@ -156,6 +156,9 @@ extern void up_boot(void);
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extern void up_copystate(uint32 *dest, uint32 *src);
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extern void up_decodeirq(uint32 *regs);
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extern void up_irqinitialize(void);
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#ifdef CONFIG_ARCH_DMA
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extern void weak_function up_dmainitialize(void);
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#endif
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extern int up_saveusercontext(uint32 *saveregs);
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extern void up_fullcontextrestore(uint32 *restoreregs) __attribute__ ((noreturn));
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extern void up_switchcontext(uint32 *saveregs, uint32 *restoreregs);
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@ -44,9 +44,12 @@
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#include <debug.h>
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#include <errno.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "os_internal.h"
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#include "chip.h"
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#include "stm32_dma.h"
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@ -64,6 +67,10 @@
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# define DMA_NCHANNELS DMA1_NCHANNELS
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#endif
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#ifndef CONFIG_DMA_PRI
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# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT
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#endif
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/* Convert the DMA channel base address to the DMA register block address */
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#define DMA_BASE(ch) (ch & 0xfffffc00)
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@ -76,7 +83,7 @@
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struct stm32_dma_s
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{
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ubyte chan; /* DMA channel number */
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ubyte chan; /* DMA channel number (0-6) */
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ubyte irq; /* DMA channel IRQ number */
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sem_t sem; /* Used to wait for DMA channel to become available */
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uint32 base; /* DMA register channel base address */
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@ -93,58 +100,58 @@ struct stm32_dma_s
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static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
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{
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{
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.chan = STM32_DMA1_CHAN1,
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.chan = 0,
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.irq = STM32_IRQ_DMA1CH1,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0),
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},
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{
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.chan = STM32_DMA1_CHAN2,
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.chan = 1,
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.irq = STM32_IRQ_DMA1CH2,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1),
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},
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{
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.chan = STM32_DMA1_CHAN3,
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.chan = 2,
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.irq = STM32_IRQ_DMA1CH3,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2),
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},
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{
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.chan = STM32_DMA1_CHAN4,
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.chan = 3,
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.irq = STM32_IRQ_DMA1CH4,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3),
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},
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{
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.chan = STM32_DMA1_CHAN5,
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.chan = 4,
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.irq = STM32_IRQ_DMA1CH5,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4),
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},
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{
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.chan = STM32_DMA1_CHAN6,
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.chan = 5,
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.irq = STM32_IRQ_DMA1CH6,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5),
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},
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{
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.chan = STM32_DMA1_CHAN7,
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.chan = 6,
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.irq = STM32_IRQ_DMA1CH7,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6),
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},
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#if STM32_NDMA > 1
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{
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.chan = STM32_DMA2_CHAN1,
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.chan = 0,
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.irq = STM32_IRQ_DMA2CH1,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0),
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},
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{
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.chan = STM32_DMA2_CHAN2,
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.chan = 1,
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.irq = STM32_IRQ_DMA2CH2,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1),
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},
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{
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.chan = STM32_DMA2_CHAN3,
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.chan = 2,
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.irq = STM32_IRQ_DMA2CH3,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2),
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},
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{
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.chan = STM32_DMA2_CHAN4,
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.chan = 3,
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#ifdef CONFIG_STM32_CONNECTIVITY_LINE
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.irq = STM32_IRQ_DMA2CH4,
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#else
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@ -153,7 +160,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3),
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},
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{
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.chan = STM32_DMA2_CHAN5,
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.chan = 4,
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#ifdef CONFIG_STM32_CONNECTIVITY_LINE
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.irq = STM32_IRQ_DMA2CH5,
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#else
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@ -227,6 +234,33 @@ static inline void stm32_dmagive(FAR struct stm32_dma_s *dmach)
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(void)sem_post(&dmach->sem);
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}
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/************************************************************************************
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* Name: stm32_dmachandisable
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*
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* Description:
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* Disable the DMA channel
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*
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************************************************************************************/
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static void stm32_dmachandisable(struct stm32_dma_s *dmach)
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{
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uint32 regval;
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/* Disable all interrupts at the DMA controller */
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regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
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regval &= ~DMA_CCR_ALLINTS;
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/* Disable the DMA channel */
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regval &= ~DMA_CCR_EN;
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dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
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/* Clear pending channel interrupts */
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dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmach->chan));
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}
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/************************************************************************************
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* Name: stm32_dmainterrupt
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*
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@ -239,13 +273,13 @@ static int stm32_dmainterrupt(int irq, void *context)
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{
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struct stm32_dma_s *dmach;
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uint32 isr;
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int chan;
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int chndx;
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/* Get the channel structure from the interrupt number */
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if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7)
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{
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chan = irq - STM32_IRQ_DMA1CH1;
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chndx = irq - STM32_IRQ_DMA1CH1;
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}
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else
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#if STM32_NDMA > 1
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@ -255,28 +289,28 @@ static int stm32_dmainterrupt(int irq, void *context)
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if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH45)
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#endif
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{
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chan = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS;
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chndx = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS;
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}
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else
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#endif
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{
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PANIC(OSERR_INTERNAL);
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}
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dmach = &g_dma[chan];
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dmach = &g_dma[chndx];
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/* Get the interrupt status (for this channel only) */
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isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & ~DMA_ISR_CHAN_MASK(chan);
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isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan);
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/* Clear pending interrupts (for this channel only) */
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/* Disable the DMA channel */
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dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr);
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stm32_dmachandisable(dmach);
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/* Invoke the callback */
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if (dmach->callback)
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{
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dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(chan), dmach->arg);
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dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(dmach->chan), dmach->arg);
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}
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return OK;
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}
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@ -296,16 +330,33 @@ static int stm32_dmainterrupt(int irq, void *context)
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*
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****************************************************************************/
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void weak_function stm32_dmainitialize(void)
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void weak_function up_dmainitialize(void)
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{
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int chan;
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struct stm32_dma_s *dmach;
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int chndx;
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/* Initialize each DMA channel */
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for (chndx = 0; chndx < DMA_NCHANNELS; chndx++)
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{
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dmach = &g_dma[chndx];
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sem_init(&dmach->sem, 0, 1);
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/* Attach DMA interrupt vectors */
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for (chan = 0; chan < DMA_NCHANNELS; chan++)
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{
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sem_init(&g_dma[chan].sem, 0, 1);
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irq_attach(g_dma[chan].irq, stm32_dmainterrupt);
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(void)irq_attach(dmach->irq, stm32_dmainterrupt);
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/* Disable the DMA channel */
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stm32_dmachandisable(dmach);
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/* Enable the IRQ at the NVIC (still disabled at the DMA controller) */
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up_enable_irq(dmach->irq);
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/* Set the interrrupt priority */
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up_prioritize_irq(dmach->irq, CONFIG_DMA_PRI);
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}
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}
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@ -314,7 +365,7 @@ void weak_function stm32_dmainitialize(void)
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*
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* Description:
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* Allocate a DMA channel. This function gives the caller mutually
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* exclusive access to the DMA channel specified by the 'chan' argument.
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* exclusive access to the DMA channel specified by the 'chndx' argument.
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* DMA channels are shared on the STM32: Devices sharing the same DMA
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* channel cannot do DMA concurrently! See the DMACHAN_* definitions in
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* stm32_dma.h.
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@ -330,8 +381,8 @@ void weak_function stm32_dmainitialize(void)
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* version. Feel free to do that if that is what you need.
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*
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* Returned Value:
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* Provided that 'chan' is valid, this function ALWAYS returns a non-NULL,
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* void* DMA channel handle. (If 'chan' is invalid, the function will
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* Provided that 'chndx' is valid, this function ALWAYS returns a non-NULL,
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* void* DMA channel handle. (If 'chndx' is invalid, the function will
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* assert if debug is enabled or do something ignorant otherwise).
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*
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* Assumptions:
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@ -341,11 +392,11 @@ void weak_function stm32_dmainitialize(void)
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*
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****************************************************************************/
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DMA_HANDLE stm32_dmachannel(int chan)
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DMA_HANDLE stm32_dmachannel(int chndx)
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{
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struct stm32_dma_s *dmach = &g_dma[chan];
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struct stm32_dma_s *dmach = &g_dma[chndx];
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DEBUGASSERT(chan < DMA_NCHANNELS);
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DEBUGASSERT(chndx < DMA_NCHANNELS);
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/* Get exclusive access to the DMA channel -- OR wait until the channel
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* is available if it is currently being used by another driver
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@ -478,3 +529,44 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, boole
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ccr |= (half ? (DMA_CCR_HTIE|DMA_CCR_TEIE) : (DMA_CCR_TCIE|DMA_CCR_TEIE));
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dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr);
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}
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/****************************************************************************
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* Name: stm32_dmadump
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*
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* Description:
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* Dump DMA register contents
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*
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* Assumptions:
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* - DMA handle allocated by stm32_dmachannel()
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_DMA
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void stm32_dmadump(DMA_HANDLE handle, const char *msg)
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{
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struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
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uint32 dmabase = DMA_BASE(dmach->base);
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irqstate_t flags;
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uint32 addr;
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dmalldbg("%s: base: %08x Channel base: %08x \n", msg, dmabase, dmach->base);
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flags = irqsave();
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addr = dmabase + STM32_DMA_ISR_OFFSET;
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dmalldbg(" ISRC[%08x]: %08x\n", addr, getreg32(addr));
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addr = dmach->base + STM32_DMACHAN_CCR_OFFSET;
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dmalldbg(" CCR[%08x]: %08x\n", addr, getreg32(addr));
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addr = dmach->base + STM32_DMACHAN_CNDTR_OFFSET;
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dmalldbg(" CNDTR[%08x]: %08x\n", addr, getreg32(addr));
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addr = dmach->base + STM32_DMACHAN_CPAR_OFFSET;
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dmalldbg(" CPAR[%08x]: %08x\n", addr, getreg32(addr));
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addr = dmach->base + STM32_DMACHAN_CMAR_OFFSET;
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dmalldbg(" CMAR[%08x]: %08x\n", addr, getreg32(addr));
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irqrestore(flags);
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}
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#endif
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@ -229,6 +229,7 @@
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#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
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#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
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#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
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#define DMA_IFCR_ALLCHANNELS (0x0fffffff)
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#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
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#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
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@ -263,6 +264,8 @@
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#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
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#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
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#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
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/* DMA channel number of data register */
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#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
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@ -50,6 +50,12 @@
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* Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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#if !defined(CONFIG_DEBUG) || !defined(CONFIG_DEBUG_VERBOSE)
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# undef CONFIG_DEBUG_DMA
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#endif
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/* NVIC priority levels *************************************************************/
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#define NVIC_SYSH_PRIORITY_MIN 0xff /* All bits set in minimum priority */
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@ -265,19 +271,6 @@ EXTERN int stm32_dumpgpio(uint32 pinset, const char *msg);
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# define stm32_dumpgpio(p,m)
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#endif
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/****************************************************************************
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* Name: stm32_dmainitialize
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*
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* Description:
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* Initialize the DMA subsystem
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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EXTERN void weak_function stm32_dmainitialize(void);
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/****************************************************************************
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* Name: stm32_dmachannel
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*
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@ -359,6 +352,23 @@ EXTERN void stm32_dmasetup(DMA_HANDLE handle, uint32 paddr, uint32 maddr,
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EXTERN void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback,
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void *arg, boolean half);
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/****************************************************************************
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* Name: stm32_dmadump
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*
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* Description:
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* Dump DMA register contents
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*
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* Assumptions:
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* - DMA handle allocated by stm32_dmachannel()
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_DMA
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EXTERN void stm32_dmadump(DMA_HANDLE handle, const char *msg);
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#else
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# define stm32_dmadump(handle)
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#endif
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/************************************************************************************
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* Function: stm32_ethinitialize
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*
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@ -118,10 +118,10 @@
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/* DMA CCR register settings */
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#define SDIO_RXDMA16_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_16BITS|\
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DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC)
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#define SDIO_TXDMA16_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_16BITS|\
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DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC|DMA_CCR_DIR)
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#define SDIO_RXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_32BITS|\
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DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC)
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#define SDIO_TXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_32BITS|\
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DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC|DMA_CCR_DIR)
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/* FIFO sizes */
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@ -528,6 +528,8 @@ static void stm32_dmacallback(DMA_HANDLE handle, ubyte isr, void *arg)
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/* We don't really do anything at the completion of DMA. The termination
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* of the transfer is driven by the SDIO interrupts.
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*/
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stm32_dmadump(handle, "DMA Callback");
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}
|
||||
#endif
|
||||
|
||||
@ -837,6 +839,15 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupeven
|
||||
|
||||
priv->remaining = 0;
|
||||
|
||||
/* DMA debug instrumentation */
|
||||
|
||||
#if defined(CONFIG_SDIO_DMA) && defined(CONFIG_DEBUG_DMA)
|
||||
if (priv->dmamode)
|
||||
{
|
||||
stm32_dmadump(priv->dma, "End of Transfer");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Is a data transfer complete event expected? */
|
||||
|
||||
if ((priv->waitevents & wkupevent) != 0)
|
||||
@ -1978,6 +1989,8 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR ubyte *buffer,
|
||||
|
||||
if (priv->widebus)
|
||||
{
|
||||
stm32_dmadump(priv->dma, "Before RECV Setup");
|
||||
|
||||
/* Save the destination buffer information for use by the interrupt handler */
|
||||
|
||||
priv->buffer = (uint32*)buffer;
|
||||
@ -1995,11 +2008,12 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR ubyte *buffer,
|
||||
|
||||
putreg32(1, SDIO_DCTRL_DMAEN_BB);
|
||||
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32)buffer,
|
||||
(buflen + 3) >> 2, SDIO_RXDMA16_CONFIG);
|
||||
(buflen + 3) >> 2, SDIO_RXDMA32_CONFIG);
|
||||
|
||||
/* Start the DMA */
|
||||
|
||||
stm32_dmastart(priv->dma, stm32_dmacallback, priv, FALSE);
|
||||
stm32_dmadump(priv->dma, "After RECV Setup");
|
||||
ret = OK;
|
||||
}
|
||||
return ret;
|
||||
@ -2044,6 +2058,8 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
|
||||
|
||||
if (priv->widebus)
|
||||
{
|
||||
stm32_dmadump(priv->dma, "Before SEND Setup");
|
||||
|
||||
/* Save the source buffer information for use by the interrupt handler */
|
||||
|
||||
priv->buffer = (uint32*)buffer;
|
||||
@ -2062,12 +2078,13 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
|
||||
/* Configure the TX DMA */
|
||||
|
||||
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32)buffer,
|
||||
(buflen + 3) >> 2, SDIO_TXDMA16_CONFIG);
|
||||
(buflen + 3) >> 2, SDIO_TXDMA32_CONFIG);
|
||||
putreg32(1, SDIO_DCTRL_DMAEN_BB);
|
||||
|
||||
/* Start the DMA */
|
||||
|
||||
stm32_dmastart(priv->dma, stm32_dmacallback, priv, FALSE);
|
||||
stm32_dmadump(priv->dma, "After SEND Setup");
|
||||
ret = OK;
|
||||
}
|
||||
return ret;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user