arch/arm/src/armv7-a/mmu.h: Fix some typos; Use TLBIMVA vs TLBIMVAAIS to invalidate the Cortex-A8 cache.
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@ -941,7 +941,11 @@ struct section_mapping_s
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.macro cp15_invalidate_tlb_bymva, vaddr
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dsb
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#if defined(CONFIG_ARCH_CORTEXA8)
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mcr p15, 0, \vaddr, c8, c7, 1 /* TLBIMVA */
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#else
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mcr p15, 0, \vaddr, c8, c3, 3 /* TLBIMVAAIS */
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#endif
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dsb
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isb
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.endm
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@ -970,7 +974,7 @@ struct section_mapping_s
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.endm
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/************************************************************************************
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* Name: cp14_wrttb
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* Name: cp15_wrttb
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*
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* Description:
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* The ARMv7-aA architecture supports two translation tables. This
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@ -984,7 +988,7 @@ struct section_mapping_s
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*
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************************************************************************************/
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.macro cp14_wrttb, ttb, scratch
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.macro cp15_wrttb, ttb, scratch
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mcr p15, 0, \ttb, c2, c0, 0
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nop
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nop
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@ -1220,7 +1224,11 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
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__asm__ __volatile__
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(
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"\tdsb\n"
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#if defined(CONFIG_ARCH_CORTEXA8)
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"\tmcr p15, 0, %0, c8, c7, 1\n" /* TLBIMVA */
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#else
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"\tmcr p15, 0, %0, c8, c3, 3\n" /* TLBIMVAAIS */
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#endif
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"\tdsb\n"
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"\tisb\n"
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:
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@ -1260,7 +1268,7 @@ static inline void cp15_wrdacr(unsigned int dacr)
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}
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/************************************************************************************
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* Name: cp14_wrttb
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* Name: cp15_wrttb
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*
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* Description:
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* The ARMv7-aA architecture supports two translation tables. This
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@ -1274,7 +1282,7 @@ static inline void cp15_wrdacr(unsigned int dacr)
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*
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************************************************************************************/
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static inline void cp14_wrttb(unsigned int ttb)
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static inline void cp15_wrttb(unsigned int ttb)
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{
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__asm__ __volatile__
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(
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