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arch/arm/src/stm32/stm32f33xxx_rcc.c: A flash wait state configuration. Flash latency must be fixed according to sysclk frequency. If this operation

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is not done or done after PLL configuration, the STM32 fail to continue boot
operation if the frequency if greater than 24MHz.  This common t add this operation according to the board variable STM32_SYSCLK_FREQUENCY.  Tested on stm32f334-disco board.
This commit is contained in:
Gwenhael Goavec-Merou 2018-02-17 12:27:29 -06:00 committed by Gregory Nutt
parent 6a405ead67
commit 5ec2b9d6fe
1 changed files with 21 additions and 0 deletions
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21
arch/arm/src/stm32/stm32f33xxx_rcc.c
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@ -435,6 +435,27 @@ static void stm32_stdclockconfig(void)
#endif
/* Set flash wait states according to sysclk:
*
* 0WS from 0-24MHz
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
regval = getreg32(STM32_FLASH_ACR);
regval &= ~(FLASH_ACR_LATENCY_MASK);
#if STM32_SYSCLK_FREQUENCY <= 24000000
regval |= FLASH_ACR_LATENCY_0;
#elif STM32_SYSCLK_FREQUENCY <= 48000000
regval |= FLASH_ACR_LATENCY_1;
#else
regval |= FLASH_ACR_LATENCY_2;
#endif
regval |= FLASH_ACR_PRTFBE;
putreg32(regval, STM32_FLASH_ACR);
/* Select the system clock source (probably the PLL) */
regval = getreg32(STM32_RCC_CFGR);