SAML21: Add AES register definition header file
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Gregory Nutt
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b5cc782205
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arch/arm/src/samdl/chip/saml_aes.h
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211
arch/arm/src/samdl/chip/saml_aes.h
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/********************************************************************************************
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* arch/arm/src/samdl/chip/saml_aes.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAML_AES_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAML_AES_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifdef CONFIG_ARCH_FAMILY_SAML21
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* AES register offsets ********************************************************************/
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#define SAM_AES_CTRLA_OFFSET 0x0000 /* Control A Register */
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#define SAM_AES_CTRLB_OFFSET 0x0004 /* Control B Register */
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#define SAM_AES_INTENCLR_OFFSET 0x0005 /* Interrupt Enable Clear Register */
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#define SAM_AES_INTENSET_OFFSET 0x0006 /* Interrupt Enable Set Register */
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#define SAM_AES_INTENFLAG_OFFSET 0x0007 /* Interrupt Flag Status and Clear Register */
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#define SAM_AES_DATABUFPTR_OFFSET 0x0008 /* Data Buffer Pointer Register */
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#define SAM_AES_DBGCTRL_OFFSET 0x0009 /* Debug Register */
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#define SAM_AES_KEYWORD_OFFSET(n) (0x0010 + ((n) << 2))
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# define SAM_AES_KEWORD0_OFFSET 0x0010 /* Keyword 0 Register */
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# define SAM_AES_KEWORD1_OFFSET 0x0014 /* Keyword 1 Register */
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# define SAM_AES_KEWORD2_OFFSET 0x0018 /* Keyword 2 Register */
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# define SAM_AES_KEWORD3_OFFSET 0x001c /* Keyword 3 Register */
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# define SAM_AES_KEWORD4_OFFSET 0x0020 /* Keyword 4 Register */
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# define SAM_AES_KEWORD5_OFFSET 0x0024 /* Keyword 5 Register */
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# define SAM_AES_KEWORD6_OFFSET 0x0028 /* Keyword 6 Register */
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#define SAM_AES_DATA_OFFSET 0x0038 /* Data Register */
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#define SAM_AES_INTVECT_OFFSET(n) (0x003c + ((n) << 2))
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# define SAM_AES_INTVECT0_OFFSET 0x003c /* Initialization Vector 0 Register */
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# define SAM_AES_INTVECT1_OFFSET 0x0040 /* Initialization Vector 1 Register */
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# define SAM_AES_INTVECT2_OFFSET 0x0044 /* Initialization Vector 2 Register */
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# define SAM_AES_INTVECT3_OFFSET 0x0048 /* Initialization Vector 3 Register */
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#define SAM_AES_HASHKEY_OFFSET(n) (0x004c + ((n) << 2))
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# define SAM_AES_HASHKEY0_OFFSET 0x004c /* Hash Key 0 Register */
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# define SAM_AES_HASHKEY1_OFFSET 0x0050 /* Hash Key 1 Register */
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# define SAM_AES_HASHKEY2_OFFSET 0x0054 /* Hash Key 2 Register */
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# define SAM_AES_HASHKEY3_OFFSET 0x0058 /* Hash Key 3 Register */
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#define SAM_AES_GHASH_OFFSET(n) (0x005c + ((n) << 2))
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# define SAM_AES_GHASH0_OFFSET 0x005c /* Galois Hash 0 Register */
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# define SAM_AES_GHASH1_OFFSET 0x0060 /* Galois Hash 1 Register */
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# define SAM_AES_GHASH2_OFFSET 0x0064 /* Galois Hash 2 Register */
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# define SAM_AES_GHASH3_OFFSET 0x0068 /* Galois Hash 3 Register */
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#define SAM_AES_CIPLEN_OFFSET 0x0070 /* Cipher Length Register */
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#define SAM_AES_RANDSEED_OFFSET 0x0074 /* Random Seed Register */
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/* AES register addresses ******************************************************************/
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#define SAM_AES_CTRLA (SAM_AES_BASE+SAM_AES_CTRLA_OFFSET)
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#define SAM_AES_CTRLB (SAM_AES_BASE+SAM_AES_CTRLB_OFFSET)
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#define SAM_AES_INTENCLR (SAM_AES_BASE+SAM_AES_INTENCLR_OFFSET)
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#define SAM_AES_INTENSET (SAM_AES_BASE+SAM_AES_INTENSET_OFFSET)
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#define SAM_AES_INTENFLAG (SAM_AES_BASE+SAM_AES_INTENFLAG_OFFSET)
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#define SAM_AES_DATABUFPTR (SAM_AES_BASE+SAM_AES_DATABUFPTR_OFFSET)
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#define SAM_AES_DBGCTRL (SAM_AES_BASE+SAM_AES_DBGCTRL_OFFSET)
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#define SAM_AES_KEYWORD(n) (SAM_AES_BASE+SAM_AES_KEYWORD_OFFSET(n))
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# define SAM_AES_KEWORD0 (SAM_AES_BASE+SAM_AES_KEWORD0_OFFSET)
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# define SAM_AES_KEWORD1 (SAM_AES_BASE+SAM_AES_KEWORD1_OFFSET)
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# define SAM_AES_KEWORD2 (SAM_AES_BASE+SAM_AES_KEWORD2_OFFSET)
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# define SAM_AES_KEWORD3 (SAM_AES_BASE+SAM_AES_KEWORD3_OFFSET)
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# define SAM_AES_KEWORD4 (SAM_AES_BASE+SAM_AES_KEWORD4_OFFSET)
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# define SAM_AES_KEWORD5 (SAM_AES_BASE+SAM_AES_KEWORD5_OFFSET)
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# define SAM_AES_KEWORD6 (SAM_AES_BASE+SAM_AES_KEWORD6_OFFSET)
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#define SAM_AES_DATA (SAM_AES_BASE+SAM_AES_DATA_OFFSET)
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#define SAM_AES_INTVECT(n) (SAM_AES_BASE+SAM_AES_INTVECT_OFFSET(n))
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# define SAM_AES_INTVECT0 (SAM_AES_BASE+SAM_AES_INTVECT0_OFFSET)
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# define SAM_AES_INTVECT1 (SAM_AES_BASE+SAM_AES_INTVECT1_OFFSET)
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# define SAM_AES_INTVECT2 (SAM_AES_BASE+SAM_AES_INTVECT2_OFFSET)
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# define SAM_AES_INTVECT3 (SAM_AES_BASE+SAM_AES_INTVECT3_OFFSET)
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#define SAM_AES_HASHKEY(n) (SAM_AES_BASE+SAM_AES_HASHKEY_OFFSET(n))
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# define SAM_AES_HASHKEY0 (SAM_AES_BASE+SAM_AES_HASHKEY0_OFFSET)
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# define SAM_AES_HASHKEY1 (SAM_AES_BASE+SAM_AES_HASHKEY1_OFFSET)
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# define SAM_AES_HASHKEY2 (SAM_AES_BASE+SAM_AES_HASHKEY2_OFFSET)
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# define SAM_AES_HASHKEY3 (SAM_AES_BASE+SAM_AES_HASHKEY3_OFFSET)
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#define SAM_AES_GHASH(n) (SAM_AES_BASE+SAM_AES_GHASH_OFFSET(n))
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# define SAM_AES_GHASH0 (SAM_AES_BASE+SAM_AES_GHASH0_OFFSET)
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# define SAM_AES_GHASH1 (SAM_AES_BASE+SAM_AES_GHASH1_OFFSET)
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# define SAM_AES_GHASH2 (SAM_AES_BASE+SAM_AES_GHASH2_OFFSET)
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# define SAM_AES_GHASH3 (SAM_AES_BASE+SAM_AES_GHASH3_OFFSET)
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#define SAM_AES_CIPLEN (SAM_AES_BASE+SAM_AES_CIPLEN_OFFSET)
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#define SAM_AES_RANDSEED (SAM_AES_BASE+SAM_AES_RANDSEED_OFFSET)
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/* AES register bit definitions ************************************************************/
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/* Control A Register */
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#define AES_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
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#define AES_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
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#define AES_CTRLA_AESMODE_SHIFT (2) /* Bits 2-4: AES mode of operation */
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#define AES_CTRLA_AESMODE_MASK (7 << AES_CTRLA_AESMODE_SHIFT)
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# define AES_CTRLA_AESMODE_ECB (0 << AES_CTRLA_AESMODE_SHIFT) /* Electronic code book mode */
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# define AES_CTRLA_AESMODE_CBC (1 << AES_CTRLA_AESMODE_SHIFT) /* Cipher block chaining mode */
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# define AES_CTRLA_AESMODE_OFB (2 << AES_CTRLA_AESMODE_SHIFT) /* Output feedback mode */
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# define AES_CTRLA_AESMODE_CFB (3 << AES_CTRLA_AESMODE_SHIFT) /* Cipher feedback mode */
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# define AES_CTRLA_AESMODE_CNTR (4 << AES_CTRLA_AESMODE_SHIFT) /* Counter mode */
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# define AES_CTRLA_AESMODE_CCM (5 << AES_CTRLA_AESMODE_SHIFT) /* CCM mode */
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# define AES_CTRLA_AESMODE_GCM (6 << AES_CTRLA_AESMODE_SHIFT) /* Galois counter mode */
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#define AES_CTRLA_CFBS_SHIFT (5) /* Bits 5-7: Cipher feedback block size */
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#define AES_CTRLA_CFBS_MASK (7 << AES_CTRLA_CFBS_SHIFT)
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# define AES_CTRLA_CFBS_128 (0 << AES_CTRLA_CFBS_SHIFT) /* 128-bit data block */
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# define AES_CTRLA_CFBS_64 (1 << AES_CTRLA_CFBS_SHIFT) /* 64-bit data block */
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# define AES_CTRLA_CFBS_32 (2 << AES_CTRLA_CFBS_SHIFT) /* 32-bit data block */
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# define AES_CTRLA_CFBS_16 (3 << AES_CTRLA_CFBS_SHIFT) /* 16-bit data block */
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# define AES_CTRLA_CFBS_8 (4 << AES_CTRLA_CFBS_SHIFT) /* 8-bit data block */
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#define AES_CTRLA_KEYSIZE_SHIFT (8) /* Bits 8-9: Encryption key size */
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#define AES_CTRLA_KEYSIZE_MASK (3 << AES_CTRLA_KEYSIZE_SHIFT)
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# define AES_CTRLA_KEYSIZE_128 (0 << AES_CTRLA_KEYSIZE_SHIFT) /* 128-bit key */
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# define AES_CTRLA_KEYSIZE_192 (1 << AES_CTRLA_KEYSIZE_SHIFT) /* 192-bit key */
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# define AES_CTRLA_KEYSIZE_256 (2 << AES_CTRLA_KEYSIZE_SHIFT) /* 256-bit key */
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#define AES_CTRLA_CIPHER (1 << 10) /* Bit 10: Cipher */
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#define AES_CTRLA_STARTMODE (1 << 11) /* Bit 11: Start mode select */
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#define AES_CTRLA_LOD (1 << 12) /* Bit 12: Last output data mode */
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#define AES_CTRLA_KEYGEN (1 << 13) /* Bit 13: Key generation */
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#define AES_CTRLA_XORKEY (1 << 14) /* Bit 14: XOR key */
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#define AES_CTRLA_CTYPE_SHIFT (16) /* Bits 16-19: Countermeasure type */
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#define AES_CTRLA_CTYPE_MASK (15 << AES_CTRLA_CTYPE_SHIFT)
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# define AES_CTRLA_CTYPE_CTYPE1 (1 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 1 enabled */
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# define AES_CTRLA_CTYPE_CTYPE2 (2 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 2 enabled */
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# define AES_CTRLA_CTYPE_CTYPE3 (4 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 3 enabled */
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# define AES_CTRLA_CTYPE_CTYPE4 (8 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 4 enabled */
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/* Control B Register */
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#define AES_CTRLB_START (1 << 0) /* Bit 0: Start encryption/decryption */
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#define AES_CTRLB_NEWMSG (1 << 1) /* Bit 1: New message */
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#define AES_CTRLB_EOM (1 << 2) /* Bit 2: End of message */
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#define AES_CTRLB_GFMUL (1 << 3) /* Bit 3: GF multiplication */
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/* Common Bit Definitions for the Interrupt Enable Clear Register, Interrupt Enable Set
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* Register, and Interrupt Flag Status and Clear Register
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*/
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#define AES_INT_ENCCMP (1 << 0) /* Bit 0: Encryption complete interrupt */
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#define AES_INT_GFMCMP (1 << 1) /* Bit 1: GF multiplication complete interrupt */
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#define AES_INT_ALL 0x03
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/* Data Buffer Pointer Register */
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#define AES_DATABUFPTR_MASK 0x03 /* Bits 0-1: Data pointer */
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/* Debug Register */
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#define AES_DBGCTRL_DBGRUN (1 << 0) /* Bit 0: Debug run */
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/* Keyword n Register, n = 0-7 (32-value) */
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/* Data Register (32-bit value) */
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/* Initialization Vector n Register, n=0-3 (32-bit value) */
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/* Hash Key n Register, n=0-3 (32-bit value) */
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/* Galois Hash n Register, n=0-3 (32-bit value) */
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/* Cipher Length Register (32-bit vaoue) */
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/* Random Seed Register (32-bit value) */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAML21 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAML_AES_H */
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@ -62,7 +62,6 @@
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* Condition out the whole file unless DMA is selected in the configuration */
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#ifdef CONFIG_SAMDL_DMAC
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@ -416,7 +415,9 @@ static struct dma_desc_s *sam_alloc_desc(struct sam_dmach_s *dmach)
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desc->srcaddr = (uint32_t)-1; /* Any non-zero value */
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/* Save a pointer to the first allocated DMA descriptor
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* (for sam_free_desc).
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* (for sam_free_desc). We have to do this because we cannot
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* use the link in the base descriptor; it will be overwritten
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* by the writeback.
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*/
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if (dmach->dc_head == NULL)
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