Missed a few in previous commit
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@ -195,7 +195,7 @@
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# define GCLK_GENCTRL_ID7 (7 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 7 */
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define GCLK_GENCTRL_ID8 (78<< GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 8 */
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# define GCLK_GENCTRL_ID8 (8 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 8 */
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#endif
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#define GCLK_GENCTRL_SRC_SHIFT (8) /* Bits 8-12: Source Select */
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@ -208,6 +208,11 @@
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# define GCLK_GENCTRL_SRC_XOSC32K (5 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC32K oscillator output */
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# define GCLK_GENCTRL_SRC_OSC8M (6 << GCLK_GENCTRL_SRC_SHIFT) /* OSC8M oscillator output */
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# define GCLK_GENCTRL_SRC_DFLL48M (7 << GCLK_GENCTRL_SRC_SHIFT) /* DFLL48M output */
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define GCLK_GENCTRL_SRC_FDPLL96M (8 << GCLK_GENCTRL_SRC_SHIFT) /* FDPLL96M output */
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#endif
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#define GCLK_GENCTRL_GENEN (1 << 16) /* Bit 16: Generic Clock Generator Enable */
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#define GCLK_GENCTRL_IDC (1 << 17) /* Bit 17: Improve Duty Cycle */
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#define GCLK_GENCTRL_OOV (1 << 18) /* Bit 18: Output Off Value */
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@ -228,6 +233,11 @@
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# define GCLK_GENDIV_ID5 (5 << GCLK_GENDIV_ID_SHIFT) /* Generic clock generator 5 */
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# define GCLK_GENDIV_ID6 (6 << GCLK_GENDIV_ID_SHIFT) /* Generic clock generator 6 */
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# define GCLK_GENDIV_ID7 (7 << GCLK_GENDIV_ID_SHIFT) /* Generic clock generator 7 */
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define GCLK_GENDIV_ID8 (8 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 8 */
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#endif
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#define GCLK_GENDIV_DIV_SHIFT (8) /* Bits 8-23: Division Factor */
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#define GCLK_GENDIV_DIV_MASK (0xffff << GCLK_GENDIV_DIV_SHIFT)
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# define GCLK_GENDIV_DIV(n) ((n) << GCLK_GENDIV_DIV_SHIFT)
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