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Add c5471 Ethernet driver

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@423 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2007-12-04 17:11:55 +00:00
parent 55358e04c8
commit 5efd8589a7
6 changed files with 2066 additions and 35 deletions
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1
ChangeLog
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@ -267,3 +267,4 @@
* Verfied basic DHCP client functionality (netutils/dhcpc) * Verfied basic DHCP client functionality (netutils/dhcpc)
* Implemented send() timeout logic * Implemented send() timeout logic
* Add a skeleton Ethernet device driver (drivers/net/skeleton.c) * Add a skeleton Ethernet device driver (drivers/net/skeleton.c)
* Added C5471 Ethernet device driver (arch/arm/src/c5471/c5471_ethernet.c)

1
Documentation/NuttX.html
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@ -756,6 +756,7 @@ Other memory:
* Implemented send() timeout logic * Implemented send() timeout logic
* Add TELNETD front end to NSH (examples/nsh) * Add TELNETD front end to NSH (examples/nsh)
* Add a skeleton Ethernet device driver (drivers/net/skeleton.c) * Add a skeleton Ethernet device driver (drivers/net/skeleton.c)
* Added C5471 Ethernet device driver (arch/arm/src/c5471/c5471_ethernet.c)
</pre></ul> </pre></ul>
<table width ="100%"> <table width ="100%">

5
arch/arm/src/c5471/Make.defs
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@ -37,7 +37,7 @@ HEAD_ASRC = up_nommuhead.S
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
up_createstack.c up_dataabort.c up_mdelay.c up_udealy.c up_doirq.c \ up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c up_doirq.c \
up_exit.c up_idle.c up_initialize.c up_initialstate.c \ up_exit.c up_idle.c up_initialize.c up_initialstate.c \
up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \ up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
@ -45,4 +45,5 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
up_undefinedinsn.c up_usestack.c up_undefinedinsn.c up_usestack.c
CHIP_ASRCS = c5471_lowputc.S c5471_vectors.S CHIP_ASRCS = c5471_lowputc.S c5471_vectors.S
CHIP_CSRCS = c5471_irq.c c5471_serial.c c5471_timerisr.c c5471_watchdog.c CHIP_CSRCS = c5471_irq.c c5471_serial.c c5471_timerisr.c c5471_watchdog.c \
c5471_ethernet.c

1976
arch/arm/src/c5471/c5471_ethernet.c Normal file
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File diff suppressed because it is too large Load Diff

86
arch/arm/src/c5471/chip.h
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@ -1,4 +1,4 @@
/************************************************************ /****************************************************************************
* c5471/chip.h * c5471/chip.h
* *
* Copyright (C) 2007 Gregory Nutt. All rights reserved. * Copyright (C) 2007 Gregory Nutt. All rights reserved.
@ -31,20 +31,61 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
************************************************************/ ****************************************************************************/
#ifndef __C5471_CHIP_H #ifndef __C5471_CHIP_H
#define __C5471_CHIP_H #define __C5471_CHIP_H
/************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************/ ****************************************************************************/
/************************************************************ /****************************************************************************
* Definitions * Definitions
************************************************************/ ****************************************************************************/
/* UARTs ****************************************************/ #define EIM_RAM_START 0xffd00000
/* Ethernet Interface Module (EIM) ******************************************/
#define EIM_CTRL 0xffff0000 /* ESM control register */
#define EIM_STATUS 0xffff0004 /* ESM status register */
#define EIM_CPU_TXBA 0xffff0008 /* CPU TX descriptors base address */
#define EIM_CPU_RXBA 0xffff000c /* CPU RX descriptors base address */
#define EIM_BUFSIZE 0xffff0010 /* Packet buffer size register */
#define EIM_CPU_FILTER 0xffff0014 /* CPU filtering contol registers */
#define EIM_CPU_DAHI 0xffff0018 /* CPU destination address (HI) */
#define EIM_CPU_DALO 0xffff001c /* CPU destination address (LO) */
#define EIM_MFVHI 0xffff0020 /* Multicast filter valid (HI) */
#define EIM_MFVLO 0xffff0024 /* Multicast filter valid (LO) */
#define EIM_MFMHI 0xffff0028 /* Multicast filter mask (HI) */
#define EIM_MFMLO 0xffff002c /* Multicast filter mask (LO) */
#define EIM_RXTH 0xffff0030 /* RX threshold register */
#define EIM_CPU_RXREADY 0xffff0034 /* CPU RX ready register */
#define EIM_INTEN 0xffff0038 /* ESM interrupt enable register */
#define EIM_ENET0_TXDESC 0xffff0040 /* ENET0 TX Queue pointer */
#define EIM_ENET0_RXDESC 0xffff0044 /* ENET0 RX Queue pointer */
#define EIM_CPU_TXDESC 0xffff0050 /* CPU TX Queue pointer */
#define EIM_CPU_RXDESC 0xffff0054 /* CPU RX Queue pointer */
#define ENET0_MODE 0xffff0100 /* Mode register */
#define ENET0_BOFFSEED 0xffff0104 /* Backoff seed register */
#define ENET0_BCOUNT 0xffff0108 /* Backoff count register */
#define ENET0_FLWPAUSE 0xffff010c /* TX flow pause count register */
#define ENET0_FLWCONTROL 0xffff0110 /* Flow control register */
#define ENET0_VTYPE 0xffff0114 /* VTYPE tag register */
#define ENET0_SEISR 0xffff0118 /* System error int status register */
#define ENET0_TXBUFRDY 0xffff011c /* TX descripter buffer ready */
#define ENET0_TDBA 0xffff0120 /* TX descriptor base address */
#define ENET0_RDBA 0xffff0124 /* RX descriptor base address */
#define ENET0_PARHI 0xffff0128 /* Dest phys address match (HI) */
#define ENET0_PARLO 0xffff012c /* Dest phys address match (LO) */
#define ENET0_LARHI 0xffff0130 /* Log address hash filter (HI) */
#define ENET0_LARLO 0xffff0134 /* Log address hash filter (LO) */
#define ENET0_ADRMODE_EN 0xffff0138 /* Address mode enable register */
#define ENET0_DRP 0xffff013c /* Desc ring poll interval count */
/* UARTs ********************************************************************/
#define UART_IRDA_BASE 0xffff0800 #define UART_IRDA_BASE 0xffff0800
#define UART_MODEM_BASE 0xffff1000 #define UART_MODEM_BASE 0xffff1000
@ -110,7 +151,7 @@
#define UART_MODEM_RDPTR_UTX 0xffff1064 /* TX FIFO Read Pointer Register */ #define UART_MODEM_RDPTR_UTX 0xffff1064 /* TX FIFO Read Pointer Register */
#define UART_MODEM_WRPTR_UTX 0xffff1068 /* TX FIFO Write Pointer Register */ #define UART_MODEM_WRPTR_UTX 0xffff1068 /* TX FIFO Write Pointer Register */
/* UART Settings ********************************************/ /* UART Settings ************************************************************/
/* Miscellaneous UART settings. */ /* Miscellaneous UART settings. */
@ -164,13 +205,13 @@
#define MDR_AUTOBAUDING_MODE 0x00000002 /* Modem UART only */ #define MDR_AUTOBAUDING_MODE 0x00000002 /* Modem UART only */
#define MDR_RESET_MODE 0x00000007 /* Both IrDA and Modem UARTs */ #define MDR_RESET_MODE 0x00000007 /* Both IrDA and Modem UARTs */
/* SPI ******************************************************/ /* SPI **********************************************************************/
#define MAX_SPI 3 #define MAX_SPI 3
#define SPI_REGISTER_BASE 0xffff2000 #define SPI_REGISTER_BASE 0xffff2000
/* GIO ******************************************************/ /* GIO **********************************************************************/
#define MAX_GIO (35) #define MAX_GIO (35)
@ -211,7 +252,7 @@
#define KBGPIO_EN 0xffff2914 /* Selects register for muxed #define KBGPIO_EN 0xffff2914 /* Selects register for muxed
* KBGPIOs */ * KBGPIOs */
/* Timers ***************************************************/ /* Timers *******************************************************************/
#define C5471_TIMER0_CTRL 0xffff2a00 #define C5471_TIMER0_CTRL 0xffff2a00
#define C5471_TIMER0_CNT 0xffff2a04 #define C5471_TIMER0_CNT 0xffff2a04
@ -252,11 +293,22 @@
#define ILR_IRQ14_REG 0xffff2d54 /* 14-GPIO[19:4] */ #define ILR_IRQ14_REG 0xffff2d54 /* 14-GPIO[19:4] */
#define ILR_IRQ15_REG 0xffff2d58 /* 15-API */ #define ILR_IRQ15_REG 0xffff2d58 /* 15-API */
/* I2C ******************************************************/ /* CLKM *********************************************************************/
#define CLKM 0xffff2f00
#define CLKM_CTL_RST 0xffff2f10
#define CLKM_RESET 0xffff2f18
#define CLKM_RESET_EIM 0x00000008
#define CLKM_EIM_CLK_STOP 0x00000010
#define CLKM_CTL_RST_LEAD_RESET 0x00000000
#define CLKM_CTL_RST_EXT_RESET 0x00000002
/* I2C **********************************************************************/
#define MAX_I2C 1 #define MAX_I2C 1
/* API ******************************************************/ /* API **********************************************************************/
#define DSPRAM_BASE 0xffe00000 /* DSPRAM base address */ #define DSPRAM_BASE 0xffe00000 /* DSPRAM base address */
#define DSPRAM_END 0xffe03fff #define DSPRAM_END 0xffe03fff
@ -308,12 +360,12 @@
#define DSPMEM_ARM_TO_DSP(addr) \ #define DSPMEM_ARM_TO_DSP(addr) \
((((__u32)(addr) - DSPMEM_ARM_START) >> 1) + DSPMEM_DSP_START) ((((__u32)(addr) - DSPMEM_ARM_START) >> 1) + DSPMEM_DSP_START)
/************************************************************ /****************************************************************************
* Inline Functions * Inline Functions
************************************************************/ ****************************************************************************/
/************************************************************ /****************************************************************************
* Public Function Prototypes * Public Function Prototypes
************************************************************/ ****************************************************************************/
#endif /* __C5471_CHIP_H */ #endif /* __C5471_CHIP_H */

28
drivers/net/skeleton.c
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@ -38,15 +38,7 @@
****************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#if defined(CONFIG_NET) && defined(CONFIG_NET_skeleton) #if defined(CONFIG_NET) && defined(CONFIG_skeleton_NET)
/* CONFIG_skeleton_NINTERFACES determines the number of physical interfaces
* that will be supported.
*/
#ifndef CONFIG_skeleton_NINTERFACES
# define CONFIG_skeleton_NINTERFACES 1
#endif
#include <time.h> #include <time.h>
#include <string.h> #include <string.h>
@ -65,6 +57,14 @@
* Definitions * Definitions
****************************************************************************/ ****************************************************************************/
/* CONFIG_skeleton_NINTERFACES determines the number of physical interfaces
* that will be supported.
*/
#ifndef CONFIG_skeleton_NINTERFACES
# define CONFIG_skeleton_NINTERFACES 1
#endif
/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */ /* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
#define skeleton_WDDELAY (1*CLK_TCK) #define skeleton_WDDELAY (1*CLK_TCK)
@ -82,8 +82,8 @@
* Private Types * Private Types
****************************************************************************/ ****************************************************************************/
/* The skel_driver_s encapsulates all DM90x0 state information for a single /* The skel_driver_s encapsulates all state information for a single hardware
* DM90x0 hardware interface * interface
*/ */
struct skel_driver_s struct skel_driver_s
@ -158,7 +158,7 @@ static int skel_transmit(struct skel_driver_s *skel)
/* Disable Ethernet interrupts */ /* Disable Ethernet interrupts */
/* Send the packet: address=skel->sk_dev.d_buf, length=skel_dev.d_len */ /* Send the packet: address=skel->sk_dev.d_buf, length=skel->sk_dev.d_len */
/* Restore Ethernet interrupts */ /* Restore Ethernet interrupts */
@ -239,7 +239,7 @@ static void skel_receive(struct skel_driver_s *skel)
/* Check if the packet is a valid size for the uIP buffer configuration */ /* Check if the packet is a valid size for the uIP buffer configuration */
/* Copy the data data from the hardware to skel->sk_dev.d_buf. Set /* Copy the data data from the hardware to skel->sk_dev.d_buf. Set
* amount of data in skel_dev.d_len * amount of data in skel->sk_dev.d_len
*/ */
/* We only accept IP packets of the configured type and ARP packets */ /* We only accept IP packets of the configured type and ARP packets */
@ -589,5 +589,5 @@ int skel_initialize(void)
return OK; return OK;
} }
#endif /* CONFIG_NET && CONFIG_NET_skeleton */ #endif /* CONFIG_NET && CONFIG_skeleton_NET */