arch/risc-v: introduce AIA support
Advanced Interrupt Architecture (AIA) introduces flexiable interrupt controll for RISC-V. It includes three parts: AIA CSRs, Incoming Message Signaled Interrupt Controller (IMSIC) and Advanced Platform-Level Interrupt Controller (APLIC). Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
This commit is contained in:
Inochi Amaoto
Alan Carvalho de Assis
parent
780366de62
commit
5f70307111
@ -553,6 +553,30 @@ config ARCH_RV_EXT_SSTC
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default n
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depends on ARCH_USE_S_MODE
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config ARCH_RV_HAVE_APLIC
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bool "Enable RISC-V Advanced Platform-Level Interrupt Controller support"
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default n
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---help---
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Instead of PLIC, RISC-V also defines Advanced Platform-Level Interrupt
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Controller (APLIC) to provide flexible interrupt control. This device
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is not backward compatible with PLIC.
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config ARCH_RV_EXT_AIA
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bool "Enable RISC-V SxAIA support"
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default n
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---help---
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Advanced Interrupt Architecture defines necessary features that
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impact the ISA at a hart. This should not be selected if the
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target does not support SxAIA for the operating mode of NuttX.
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if ARCH_RV_EXT_AIA
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config ARCH_RV_HAVE_IMSIC
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bool "Enable RISC-V AIA Incoming Message Controller support"
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default n
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endif # ARCH_RV_EXT_AIA
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choice
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prompt "Toolchain Selection"
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default RISCV_TOOLCHAIN_GNU_RV64
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@ -390,6 +390,31 @@
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#define MISELECT_CLICINTIE 0x1400 /* MIREG2 */
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#define MISELECT_CLICINTTRIG 0x1480 /* MIREG */
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/* AIA Machine-Level CSRs */
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#define CSR_MTOPEI 0x35c /* Machine top external interrupt */
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#define CSR_MTOPI 0xfb0 /* Machine top interrupt */
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#define CSR_MVIEN 0x308 /* Machine virtual interrupt enables */
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#define CSR_MVIP 0x309 /* Machine virtual interrupt-pending bits */
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/* AIA Machine-Level CSRs (High-Half) */
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#define CSR_MIDELEGH 0x313
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#define CSR_MIEH 0x314
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#define CSR_MVIENH 0x318
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#define CSR_MVIPH 0x319
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#define CSR_MIPH 0x354
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/* AIA Supervisor-Level CSRs */
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#define CSR_STOPEI 0x15c /* Supervisor top external interrupt */
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#define CSR_STOPI 0xdb0 /* Supervisor top interrupt */
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/* AIA Supervisor-Level CSRs (High-Half) */
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#define CSR_SIEH 0x114
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#define CSR_SIPH 0x154
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/* In mstatus register */
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#define MSTATUS_UIE (0x1 << 0) /* User Interrupt Enable */
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@ -554,6 +579,161 @@
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#define COUNTEREN_HPM30 (0x1 << 30)
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#define COUNTEREN_HPM31 (0x1 << 31)
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/* In topi/topei register */
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#define TOPI_IID_SHIFT 16
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#define TOPI_IPRIO_BITS 8
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#define TOPEI_ID_SHIFT 16
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/* In iselect register (AIA) */
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#define ISELECT_IPRIO0 0x30
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#define ISELECT_IPRIO1 0x31
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#define ISELECT_IPRIO2 0x32
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#define ISELECT_IPRIO3 0x33
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#define ISELECT_IPRIO4 0x34
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#define ISELECT_IPRIO5 0x35
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#define ISELECT_IPRIO6 0x36
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#define ISELECT_IPRIO7 0x37
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#define ISELECT_IPRIO8 0x38
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#define ISELECT_IPRIO9 0x39
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#define ISELECT_IPRIO10 0x3a
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#define ISELECT_IPRIO11 0x3b
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#define ISELECT_IPRIO12 0x3c
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#define ISELECT_IPRIO13 0x3d
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#define ISELECT_IPRIO14 0x3e
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#define ISELECT_IPRIO15 0x3f
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#define ISELECT_EIDELIVERY 0x70
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#define ISELECT_EITHRESHOLD 0x72
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#define ISELECT_EIP0 0x80
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#define ISELECT_EIP1 0x81
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#define ISELECT_EIP2 0x82
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#define ISELECT_EIP3 0x83
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#define ISELECT_EIP4 0x84
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#define ISELECT_EIP5 0x85
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#define ISELECT_EIP6 0x86
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#define ISELECT_EIP7 0x87
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#define ISELECT_EIP8 0x88
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#define ISELECT_EIP9 0x89
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#define ISELECT_EIP10 0x8a
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#define ISELECT_EIP11 0x8b
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#define ISELECT_EIP12 0x8c
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#define ISELECT_EIP13 0x8d
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#define ISELECT_EIP14 0x8e
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#define ISELECT_EIP15 0x8f
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#define ISELECT_EIP16 0x90
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#define ISELECT_EIP17 0x91
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#define ISELECT_EIP18 0x92
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#define ISELECT_EIP19 0x93
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#define ISELECT_EIP20 0x94
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#define ISELECT_EIP21 0x95
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#define ISELECT_EIP22 0x96
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#define ISELECT_EIP23 0x97
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#define ISELECT_EIP24 0x98
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#define ISELECT_EIP25 0x99
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#define ISELECT_EIP26 0x9a
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#define ISELECT_EIP27 0x9b
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#define ISELECT_EIP28 0x9c
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#define ISELECT_EIP29 0x9d
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#define ISELECT_EIP30 0x9e
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#define ISELECT_EIP31 0x9f
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#define ISELECT_EIP32 0xa0
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#define ISELECT_EIP33 0xa1
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#define ISELECT_EIP34 0xa2
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#define ISELECT_EIP35 0xa3
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#define ISELECT_EIP36 0xa4
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#define ISELECT_EIP37 0xa5
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#define ISELECT_EIP38 0xa6
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#define ISELECT_EIP39 0xa7
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#define ISELECT_EIP40 0xa8
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#define ISELECT_EIP41 0xa9
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#define ISELECT_EIP42 0xaa
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#define ISELECT_EIP43 0xab
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#define ISELECT_EIP44 0xac
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#define ISELECT_EIP45 0xad
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#define ISELECT_EIP46 0xae
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#define ISELECT_EIP47 0xaf
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#define ISELECT_EIP48 0xb0
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#define ISELECT_EIP49 0xb1
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#define ISELECT_EIP50 0xb2
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#define ISELECT_EIP51 0xb3
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#define ISELECT_EIP52 0xb4
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#define ISELECT_EIP53 0xb5
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#define ISELECT_EIP54 0xb6
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#define ISELECT_EIP55 0xb7
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#define ISELECT_EIP56 0xb8
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#define ISELECT_EIP57 0xb9
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#define ISELECT_EIP58 0xba
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#define ISELECT_EIP59 0xbb
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#define ISELECT_EIP60 0xbc
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#define ISELECT_EIP61 0xbd
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#define ISELECT_EIP62 0xbe
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#define ISELECT_EIP63 0xbf
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#define ISELECT_EIE0 0xc0
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#define ISELECT_EIE1 0xc1
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#define ISELECT_EIE2 0xc2
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#define ISELECT_EIE3 0xc3
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#define ISELECT_EIE4 0xc4
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#define ISELECT_EIE5 0xc5
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#define ISELECT_EIE6 0xc6
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#define ISELECT_EIE7 0xc7
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#define ISELECT_EIE8 0xc8
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#define ISELECT_EIE9 0xc9
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#define ISELECT_EIE10 0xca
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#define ISELECT_EIE11 0xcb
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#define ISELECT_EIE12 0xcc
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#define ISELECT_EIE13 0xcd
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#define ISELECT_EIE14 0xce
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#define ISELECT_EIE15 0xcf
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#define ISELECT_EIE16 0xd0
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#define ISELECT_EIE17 0xd1
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#define ISELECT_EIE18 0xd2
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#define ISELECT_EIE19 0xd3
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#define ISELECT_EIE20 0xd4
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#define ISELECT_EIE21 0xd5
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#define ISELECT_EIE22 0xd6
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#define ISELECT_EIE23 0xd7
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#define ISELECT_EIE24 0xd8
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#define ISELECT_EIE25 0xd9
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#define ISELECT_EIE26 0xda
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#define ISELECT_EIE27 0xdb
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#define ISELECT_EIE28 0xdc
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#define ISELECT_EIE29 0xdd
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#define ISELECT_EIE30 0xde
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#define ISELECT_EIE31 0xdf
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#define ISELECT_EIE32 0xe0
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#define ISELECT_EIE33 0xe1
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#define ISELECT_EIE34 0xe2
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#define ISELECT_EIE35 0xe3
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#define ISELECT_EIE36 0xe4
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#define ISELECT_EIE37 0xe5
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#define ISELECT_EIE38 0xe6
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#define ISELECT_EIE39 0xe7
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#define ISELECT_EIE40 0xe8
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#define ISELECT_EIE41 0xe9
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#define ISELECT_EIE42 0xea
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#define ISELECT_EIE43 0xeb
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#define ISELECT_EIE44 0xec
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#define ISELECT_EIE45 0xed
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#define ISELECT_EIE46 0xee
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#define ISELECT_EIE47 0xef
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#define ISELECT_EIE48 0xf0
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#define ISELECT_EIE49 0xf1
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#define ISELECT_EIE50 0xf2
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#define ISELECT_EIE51 0xf3
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#define ISELECT_EIE52 0xf4
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#define ISELECT_EIE53 0xf5
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#define ISELECT_EIE54 0xf6
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#define ISELECT_EIE55 0xf7
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#define ISELECT_EIE56 0xf8
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#define ISELECT_EIE57 0xf9
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#define ISELECT_EIE58 0xfa
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#define ISELECT_EIE59 0xfb
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#define ISELECT_EIE60 0xfc
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#define ISELECT_EIE61 0xfd
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#define ISELECT_EIE62 0xfe
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#define ISELECT_EIE63 0xff
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/****************************************************************************
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* Public Types
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****************************************************************************/
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@ -45,6 +45,12 @@
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# define CSR_TVAL CSR_STVAL /* Trap value register */
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# define CSR_TVEC CSR_STVEC /* Trap vector base addr register */
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# define CSR_ENVCFG CSR_SENVCFG /* Env configuration register */
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# define CSR_IEH CSR_SIEH
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# define CSR_ISELECT CSR_SISELECT /* Indirect select register */
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# define CSR_IREG CSR_SIREG /* Indirect alias register */
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# define CSR_IPH CSR_SIPH
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# define CSR_TOPEI CSR_STOPEI /* Top external interrupt register */
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# define CSR_TOPI CSR_STOPI /* Top interrupt register */
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/* In status register */
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@ -88,6 +94,12 @@
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# define CSR_TVAL CSR_MTVAL /* Trap value register */
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# define CSR_TVEC CSR_MTVEC /* Trap vector base addr register */
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# define CSR_ENVCFG CSR_MENVCFG /* Env configuration register */
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# define CSR_IEH CSR_MIEH
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# define CSR_ISELECT CSR_MISELECT /* Indirect select register */
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# define CSR_IREG CSR_MIREG /* Indirect alias register */
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# define CSR_IPH CSR_MIPH
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# define CSR_TOPEI CSR_MTOPEI /* Top external interrupt register */
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# define CSR_TOPI CSR_MTOPI /* Top interrupt register */
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/* In status register */
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@ -88,6 +88,14 @@ if(CONFIG_ARCH_RV_ISA_A)
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list(APPEND SRCS riscv_testset.S)
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endif()
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if(CONFIG_ARCH_RV_HAVE_APLIC)
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list(APPEND SRCS riscv_aplic.c)
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endif()
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if(CONFIG_ARCH_RV_HAVE_IMSIC)
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list(APPEND SRCS riscv_imsic.c)
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endif()
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if(CONFIG_RISCV_SEMIHOSTING_HOSTFS)
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list(APPEND SRCS riscv_semihost.S riscv_hostfs.c)
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endif()
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@ -91,6 +91,10 @@ ifeq ($(CONFIG_ARCH_RV_ISA_A),y)
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CMN_ASRCS += riscv_testset.S
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endif
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ifeq ($(CONFIG_ARCH_RV_HAVE_APLIC),y)
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CMN_CSRCS += riscv_aia.c
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endif
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ifeq ($(CONFIG_RISCV_SEMIHOSTING_HOSTFS),y)
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CMN_ASRCS += riscv_semihost.S
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CMN_CSRCS += riscv_hostfs.c
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290
arch/risc-v/src/common/riscv_aia.h
Normal file
290
arch/risc-v/src/common/riscv_aia.h
Normal file
@ -0,0 +1,290 @@
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/****************************************************************************
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* arch/risc-v/src/common/riscv_aia.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRC_COMMON_RISCV_AIA_H
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#define __ARCH_RISCV_SRC_COMMON_RISCV_AIA_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/bits.h>
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#include <arch/csr.h>
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#include "riscv_internal.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* AIA IMSIC */
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#define RISCV_IMSIC_MAX_REGS 16
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#define RISCV_IMSIC_MMIO_PAGE_LE 0x00
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#define RISCV_IMSIC_MMIO_PAGE_BE 0x04
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#define RISCV_IMSIC_MMIO_PAGE_BIT 12
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#define RISCV_IMSIC_TOPEI_ID_BIT 16
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#define RISCV_IMSIC_EIP_BITS 32
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#define RISCV_IMSIC_EIE_BITS 32
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#define RISCV_IMSIC_DISABLE_EIDELIVERY 0
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#define RISCV_IMSIC_ENABLE_EIDELIVERY 1
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#define RISCV_IMSIC_DISABLE_EITHRESHOLD 1
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#define RISCV_IMSIC_ENABLE_EITHRESHOLD 0
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#define RISCV_IMSIC_IPI_ID 1
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/* AIA APLIC */
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#define RISCV_APLIC_MAX_DELEGATE 16
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#define RISCV_APLIC_MAX_IDC (1UL << 14)
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#define RISCV_APLIC_MAX_SOURCE 1024
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#define RISCV_APLIC_DOMAINCFG 0x0000
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#define RISCV_APLIC_DOMAINCFG_IE (1 << 8)
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#define RISCV_APLIC_DOMAINCFG_DM (1 << 2)
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#define RISCV_APLIC_DOMAINCFG_BE (1 << 0)
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#define RISCV_APLIC_SOURCECFG_BASE 0x0004
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#define RISCV_APLIC_SOURCECFG_D (1 << 10)
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#define RISCV_APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff
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#define RISCV_APLIC_SOURCECFG_SM_MASK 0x00000007
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#define RISCV_APLIC_SOURCECFG_SM_INACTIVE 0x0
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#define RISCV_APLIC_SOURCECFG_SM_DETACH 0x1
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#define RISCV_APLIC_SOURCECFG_SM_EDGE_RISE 0x4
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#define RISCV_APLIC_SOURCECFG_SM_EDGE_FALL 0x5
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#define RISCV_APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6
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#define RISCV_APLIC_SOURCECFG_SM_LEVEL_LOW 0x7
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#define RISCV_APLIC_MMSICFGADDR 0x1bc0
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#define RISCV_APLIC_MMSICFGADDRH 0x1bc4
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#define RISCV_APLIC_SMSICFGADDR 0x1bc8
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#define RISCV_APLIC_SMSICFGADDRH 0x1bcc
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#define RISCV_APLIC_MSICFGADDRH_L (1UL << 31)
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#define RISCV_APLIC_MSICFGADDRH_HHXS_SHIFT 24
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#define RISCV_APLIC_MSICFGADDRH_LHXS_SHIFT 20
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#define RISCV_APLIC_MSICFGADDRH_HHXW_SHIFT 16
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#define RISCV_APLIC_MSICFGADDRH_LHXW_SHIFT 12
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#define RISCV_APLIC_MSICFGADDR_PPN_SHIFT 12
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#define RISCV_APLIC_SETIP_BASE 0x1c00
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#define RISCV_APLIC_SETIPNUM 0x1cdc
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#define RISCV_APLIC_CLRIP_BASE 0x1d00
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#define RISCV_APLIC_CLRIPNUM 0x1ddc
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#define RISCV_APLIC_SETIE_BASE 0x1e00
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#define RISCV_APLIC_SETIENUM 0x1edc
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#define RISCV_APLIC_CLRIE_BASE 0x1f00
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#define RISCV_APLIC_CLRIENUM 0x1fdc
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#define RISCV_APLIC_SETIPNUM_LE 0x2000
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#define RISCV_APLIC_SETIPNUM_BE 0x2004
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#define RISCV_APLIC_TARGET_BASE 0x3004
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#define RISCV_APLIC_TARGET_HART_IDX_SHIFT 18
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#define RISCV_APLIC_TARGET_GUEST_IDX_SHIFT 12
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#define RISCV_APLIC_IDC_BASE 0x4000
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#define RISCV_APLIC_IDC_SIZE 32
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#define RISCV_APLIC_IDC_IDELIVERY 0x00
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#define RISCV_APLIC_IDC_IFORCE 0x04
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#define RISCV_APLIC_IDC_ITHRESHOLD 0x08
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#define RISCV_APLIC_IDC_TOPI 0x18
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#define RISCV_APLIC_IDC_TOPI_ID_SHIFT 16
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#define RISCV_APLIC_IDC_CLAIMI 0x1c
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#define RISCV_APLIC_DEFAULT_PRIORITY 1
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#define RISCV_APLIC_DISABLE_IDELIVERY 0
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#define RISCV_APLIC_ENABLE_IDELIVERY 1
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#define RISCV_APLIC_DISABLE_ITHRESHOLD 1
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||||
#define RISCV_APLIC_ENABLE_ITHRESHOLD 0
|
||||
|
||||
#define RISCV_APLIC_IDC(base, i) \
|
||||
((base) + RISCV_APLIC_IDC_BASE + RISCV_APLIC_IDC_SIZE * (i))
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
union aplic_mode_arg_u
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t idelivery;
|
||||
uint32_t ithreshold;
|
||||
} direct;
|
||||
|
||||
struct
|
||||
{
|
||||
uint64_t imsic_ppn;
|
||||
uint32_t lhxs;
|
||||
uint32_t lhxw;
|
||||
uint32_t hhxs;
|
||||
uint32_t hhxw;
|
||||
} msi;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* IMSIC */
|
||||
#define riscv_imsic_csr_write(reg, val) WRITE_INDIRECT_CSR_REG0(reg, val)
|
||||
#define riscv_imsic_csr_read(reg, val) READ_INDIRECT_CSR_REG0(reg, val)
|
||||
#define riscv_imsic_csr_set(reg, val) SET_INDIRECT_CSR_REG0(reg, val)
|
||||
#define riscv_imsic_csr_clear(reg, val) CLEAR_INDIRECT_CSR_REG0(reg, val)
|
||||
|
||||
void riscv_imsic_local_eix_update(unsigned long base_id,
|
||||
unsigned long num_id,
|
||||
bool pend, bool val);
|
||||
|
||||
static inline void riscv_imsic_local_eie_update(unsigned long base_id,
|
||||
unsigned long num_id, bool val)
|
||||
{
|
||||
return riscv_imsic_local_eix_update(base_id, num_id, false, val);
|
||||
}
|
||||
|
||||
static inline void riscv_imsic_local_eip_update(unsigned long base_id,
|
||||
unsigned long num_id, bool val)
|
||||
{
|
||||
return riscv_imsic_local_eix_update(base_id, num_id, true, val);
|
||||
}
|
||||
|
||||
static inline void riscv_imsic_local_eie_enable(unsigned long base_id)
|
||||
{
|
||||
return riscv_imsic_local_eie_update(base_id, 1, true);
|
||||
}
|
||||
|
||||
static inline void riscv_imsic_local_eie_disable(unsigned long base_id)
|
||||
{
|
||||
return riscv_imsic_local_eie_update(base_id, 1, false);
|
||||
}
|
||||
|
||||
void riscv_imsic_send_ipi(int cpu);
|
||||
|
||||
/* APLIC */
|
||||
|
||||
static inline int riscv_aplic_set_delegate(uintptr_t base,
|
||||
uint32_t first_irq,
|
||||
uint32_t last_irq,
|
||||
uint32_t child_id)
|
||||
{
|
||||
uint32_t j;
|
||||
uintptr_t sourcecfg_base = base + RISCV_APLIC_SOURCECFG_BASE;
|
||||
|
||||
if (!first_irq || !last_irq)
|
||||
return 0;
|
||||
|
||||
if (RISCV_APLIC_SOURCECFG_CHILDIDX_MASK < child_id)
|
||||
return -EINVAL;
|
||||
|
||||
for (j = first_irq; j <= last_irq; j++)
|
||||
{
|
||||
putreg32(RISCV_APLIC_SOURCECFG_D | child_id,
|
||||
sourcecfg_base + (j - 1) * sizeof(uint32_t));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void riscv_aplic_enable_irq(uintptr_t base, uint32_t irq)
|
||||
{
|
||||
putreg32(irq, base + RISCV_APLIC_SETIENUM);
|
||||
}
|
||||
|
||||
static inline void riscv_aplic_disable_irq(uintptr_t base, uint32_t irq)
|
||||
{
|
||||
putreg32(irq, base + RISCV_APLIC_CLRIENUM);
|
||||
}
|
||||
|
||||
static inline void riscv_aplic_configure_irq(uintptr_t base, uint32_t irq,
|
||||
uint32_t mode, uint32_t hartid)
|
||||
{
|
||||
uint32_t val = (hartid << RISCV_APLIC_TARGET_HART_IDX_SHIFT) | irq;
|
||||
putreg32(mode, base + RISCV_APLIC_SOURCECFG_BASE
|
||||
+ (irq - 1) * sizeof(uint32_t));
|
||||
putreg32(val, base + RISCV_APLIC_TARGET_BASE
|
||||
+ (irq - 1) * sizeof(uint32_t));
|
||||
}
|
||||
|
||||
static inline void riscv_aplic_disable_irqs(uintptr_t base,
|
||||
uint32_t num_source)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
putreg32(0, base + RISCV_APLIC_DOMAINCFG);
|
||||
|
||||
/* Disable all interrupts */
|
||||
|
||||
for (i = 0; i < num_source; i += 32)
|
||||
{
|
||||
putreg32(-1U, base + RISCV_APLIC_CLRIE_BASE
|
||||
+ (i / 32) * sizeof(uint32_t));
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: riscv_aplic_init
|
||||
*
|
||||
* Description:
|
||||
* Init APLIC to direct mode
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void riscv_aplic_init(uintptr_t base,
|
||||
uint32_t idelivery, uint32_t ithreshold);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: riscv_aplic_init
|
||||
*
|
||||
* Description:
|
||||
* Init APLIC to msi mode
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void riscv_aplic_init_msi(uintptr_t base, uint64_t imsic_addr,
|
||||
uint32_t lhxs, uint32_t lhxw,
|
||||
uint32_t hhxs, uint32_t hhxw);
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_COMMON_RISCV_AIA_H */
|
||||
61
arch/risc-v/src/common/riscv_aplic.c
Normal file
61
arch/risc-v/src/common/riscv_aplic.c
Normal file
@ -0,0 +1,61 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/common/riscv_aplic.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "riscv_internal.h"
|
||||
#include "riscv_aia.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
void riscv_aplic_init(uintptr_t base,
|
||||
uint32_t idelivery, uint32_t ithreshold)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < CONFIG_SMP_NCPUS; i++)
|
||||
{
|
||||
uintptr_t idc_base = RISCV_APLIC_IDC(base, i);
|
||||
|
||||
putreg32(idelivery, idc_base + RISCV_APLIC_IDC_IDELIVERY);
|
||||
putreg32(0, idc_base + RISCV_APLIC_IDC_IFORCE);
|
||||
putreg32(ithreshold, idc_base + RISCV_APLIC_IDC_ITHRESHOLD);
|
||||
}
|
||||
}
|
||||
|
||||
void riscv_aplic_init_msi(uintptr_t base, uint64_t imsic_addr,
|
||||
uint32_t lhxs, uint32_t lhxw,
|
||||
uint32_t hhxs, uint32_t hhxw)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
tmp = imsic_addr >> RISCV_IMSIC_MMIO_PAGE_BIT;
|
||||
putreg32(tmp, base + RISCV_APLIC_MMSICFGADDR);
|
||||
tmp = (uint32_t)(imsic_addr >> 32) |
|
||||
(lhxw << RISCV_APLIC_MSICFGADDRH_LHXW_SHIFT) |
|
||||
(lhxs << RISCV_APLIC_MSICFGADDRH_LHXS_SHIFT) |
|
||||
(hhxw << RISCV_APLIC_MSICFGADDRH_HHXW_SHIFT) |
|
||||
(hhxs << RISCV_APLIC_MSICFGADDRH_HHXS_SHIFT);
|
||||
putreg32(tmp, base + RISCV_APLIC_MMSICFGADDRH);
|
||||
}
|
||||
63
arch/risc-v/src/common/riscv_imsic.c
Normal file
63
arch/risc-v/src/common/riscv_imsic.c
Normal file
@ -0,0 +1,63 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/common/riscv_imsic.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "riscv_internal.h"
|
||||
#include "riscv_aia.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
void riscv_imsic_local_eix_update(unsigned long base_id,
|
||||
unsigned long num_id,
|
||||
bool pend, bool val)
|
||||
{
|
||||
uintptr_t i, isel, ireg;
|
||||
unsigned long id = base_id;
|
||||
unsigned long last_id = base_id + num_id;
|
||||
|
||||
while (id < last_id)
|
||||
{
|
||||
isel = id / __riscv_xlen;
|
||||
isel *= __riscv_xlen / RISCV_IMSIC_EIP_BITS;
|
||||
isel += (pend) ? ISELECT_EIP0 : ISELECT_EIE0;
|
||||
|
||||
ireg = 0;
|
||||
for (i = id & (__riscv_xlen - 1);
|
||||
(id < last_id) && (i < __riscv_xlen); i++)
|
||||
{
|
||||
ireg |= BIT(i);
|
||||
id++;
|
||||
}
|
||||
|
||||
if (val)
|
||||
{
|
||||
riscv_imsic_csr_set(isel, ireg);
|
||||
}
|
||||
else
|
||||
{
|
||||
riscv_imsic_csr_clear(isel, ireg);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -197,6 +197,38 @@ static inline void putreg64(uint64_t v, const volatile uintreg_t a)
|
||||
__asm__ __volatile__("csrc " __STR(reg) ", %0" :: "rK"(bits)); \
|
||||
})
|
||||
|
||||
#define SWAP_CSR(reg, val) \
|
||||
({ \
|
||||
uintptr_t regval; \
|
||||
__asm__ __volatile__("csrrw %0, " __STR(reg) ", %1" : "=r"(regval) \
|
||||
: "rK"(val)); \
|
||||
regval; \
|
||||
})
|
||||
|
||||
#define WRITE_INDIRECT_CSR_REG0(reg, val) \
|
||||
({ \
|
||||
WRITE_CSR(CSR_ISELECT, reg); \
|
||||
WRITE_CSR(CSR_IREG, val); \
|
||||
})
|
||||
|
||||
#define READ_INDIRECT_CSR_REG0(reg, val) \
|
||||
({ \
|
||||
WRITE_CSR(CSR_ISELECT, reg); \
|
||||
READ_CSR(CSR_IREG, val); \
|
||||
})
|
||||
|
||||
#define SET_INDIRECT_CSR_REG0(reg, val) \
|
||||
({ \
|
||||
WRITE_CSR(CSR_ISELECT, reg); \
|
||||
SET_CSR(CSR_IREG, val); \
|
||||
})
|
||||
|
||||
#define CLEAR_INDIRECT_CSR_REG0(reg, val) \
|
||||
({ \
|
||||
WRITE_CSR(CSR_ISELECT, reg); \
|
||||
CLEAR_CSR(CSR_IREG, val); \
|
||||
})
|
||||
|
||||
#define riscv_append_pmp_region(a, b, s) \
|
||||
riscv_config_pmp_region(riscv_next_free_pmp_region(), a, b, s)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user