Finishes coding of ARMv7-M high priority nested interrupt logic. Still undocumented; still not fully tested
This commit is contained in:
Gregory Nutt
parent
7bcfcb2544
commit
5f89b91ad1
@ -6250,7 +6250,11 @@
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autogenerated Documentation/NuttXConfigVariables.html file.
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This old configuration variable documentation is now a liability
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and, hence, was removed (2013-12-20).
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* nuttx/arch/Kconfig, nuttx/arch/arm/Kconfig, nuttx/arch/arm/include/x/chip.h,
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and nuttx/arch/arm/src/x/x_irq.c where x={kinetis, lm, lpc17xx, lpc43xx,
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* arch/Kconfig, arch/arm/Kconfig, arch/arm/include/x/chip.h, and
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and arch/arm/src/x/x_irq.c where x={kinetis, lm, lpc17xx, lpc43xx,
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sam34, or stm32}: Beginning of support for nested, high priority
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interrupts. Lots more still needs to be done (2013-12-21).
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* arch/arm/src/armv7-m/up_exception.S and arch/arm/src/x/x_vectors.S:
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where x={kinetis, lm, lpc17xx, lpc43xx, sam34, or stm32}: completes
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the basic implementation of nested, high priority interreupts.
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Still untested and need documentation (2013-12-21).
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17
arch/Kconfig
17
arch/Kconfig
@ -281,6 +281,23 @@ config ARCH_HIPRI_INTERRUPT
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int up_prioritize_irq(int irq, int priority)
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NOTE: ARCH_INTERRUPTSTACK must be set in kernel mode (NUTTX_KERNEL).
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In kernel mode without an interrupt stack, the interrupt handler
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will set the MSP to the stack pointer of the interrupted thread. If
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the interrupted thread was a privileged thread, that will be the MSP
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otherwise it will be the PSP. If the PSP is used, then the value of
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the MSP will be invalid when the interrupt handler returns because
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it will be a pointer to an old position in the unprivileged stack.
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Then when the high priority interrupt occurs and uses this stale MSP,
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there will most likely be a system failure.
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If the interrupt stack is selected, on the other hand, then the
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interrupt handler will always set the the MSP to the interrupt
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stack. So when the high priority interrupt occurs, it will either
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use the MSP of the last privileged thread to run or, in the case of
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the nested interrupt, the interrupt stack if no privileged task has
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run
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config ARCH_INT_DISABLEALL
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bool "Disable high priority interrupts"
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default y
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@ -45,6 +45,40 @@
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
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/* In kernel mode without an interrupt stack, this interrupt handler will set the
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* MSP to the stack pointer of the interrupted thread. If the interrupted thread
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* was a privileged thread, that will be the MSP otherwise it will be the PSP. If
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* the PSP is used, then the value of the MSP will be invalid when the interrupt
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* handler returns because it will be a pointer to an old position in the
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* unprivileged stack. Then when the high priority interrupt occurs and uses this
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* stale MSP, there will most likely be a system failure.
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*
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* If the interrupt stack is selected, on the other hand, then the interrupt
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* handler will always set the the MSP to the interrupt stack. So when the high
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* priority interrupt occurs, it will either use the MSP of the last privileged
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* thread to run or, in the case of the nested interrupt, the interrupt stack if
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* no privileged task has run.
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*/
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# if defined(CONFIG_NUTTX_KERNEL) && CONFIG_ARCH_INTERRUPTSTACK < 4
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# error Interrupt stack must be used with high priority interrupts in kernel mode
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# endif
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/* Use the the BASEPRI to control interrupts is required if nested, high
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* priority interrupts are supported.
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*/
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# ifndef CONFIG_ARMV7M_USEBASEPRI
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# error CONFIG_ARMV7M_USEBASEPRI must be used with CONFIG_ARCH_HIPRI_INTERRUPT
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# endif
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#endif
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/************************************************************************************
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* Global Symbols
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************************************************************************************/
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@ -76,7 +110,7 @@
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* R14 Contains the EXC_RETURN value
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* We are in handler mode and the current SP is the MSP
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*
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* If CONFIG_ARCH_FPU is defined, the volatile FP registers and FPSCR are on the
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* If CONFIG_ARCH_FPU is defined, the volatile FP registers and FPSCR are on the
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* return stack immediately above REG_XPSR.
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*/
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@ -114,8 +148,8 @@ exception_common:
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* as they are restored before returning, so we can't assume that we can get at the
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* true values of these registers in any routine called from here.
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*
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* XXX we could do all this saving lazily on the context switch side if we knew where to put
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* the registers.
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* REVISIT: we could do all this saving lazily on the context switch side if we knew
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* where to put the registers.
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*/
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vstmdb r1!, {s16-s31} /* Save the non-volatile FP context */
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@ -124,23 +158,39 @@ exception_common:
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stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP/PRIMASK values */
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#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
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/* Disable interrupts, select the stack to use for interrupt handling
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* and call up_doirq to handle the interrupt
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*/
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cpsid i /* Disable further interrupts */
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/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt
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* stack pointer. The way that this is done here prohibits nested interrupts!
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* Otherwise, we will use the stack that was current when the interrupt was taken.
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#else
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/* Set the BASEPRI register so that further normal interrupts will be
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* masked. Nested, high priority may still occur, however.
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*/
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mov r2, #NVIC_SYSH_DISABLE_PRIORITY
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msr basepri, r2 /* Set the BASEPRI */
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#endif
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will set the MSP to use
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* a special special interrupt stack pointer. The way that this is done
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* here prohibits nested interrupts without some additional logic!
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*/
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ldr sp, =g_intstackbase
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push {r1} /* Save the MSP on the interrupt stack */
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bl up_doirq /* R0=IRQ, R1=register save area on stack */
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pop {r1} /* Recover R1=main stack pointer */
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#else
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/* Otherwise, we will re-use the interrupted thread's stack. That may
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* mean using either MSP or PSP stack for interrupt level processing (in
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* kernel mode).
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*/
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msr msp, r1 /* We are using the main stack pointer */
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bl up_doirq /* R0=IRQ, R1=register save area on stack */
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mrs r1, msp /* Recover R1=main stack pointer */
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@ -198,7 +248,7 @@ exception_common:
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#endif
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2:
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/* The EXC_RETURN value tells us whether we are returning on the MSP or PSP
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/* The EXC_RETURN value tells us whether we are returning on the MSP or PSP
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*/
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#ifdef CONFIG_NUTTX_KERNEL
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@ -230,7 +280,10 @@ exception_common:
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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msr basepri, r3 /* Restore interrupts priority masking */
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#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
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cpsie i /* Re-enable interrupts */
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#endif
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#else
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msr primask, r3 /* Restore interrupts */
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#endif
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@ -47,8 +47,37 @@
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/************************************************************************************************
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* Preprocessor Definitions
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************************************************************************************************/
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/* Memory Map:
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*
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/* Configuration ********************************************************************************/
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#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
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/* In kernel mode without an interrupt stack, this interrupt handler will set the MSP to the
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* stack pointer of the interrupted thread. If the interrupted thread was a privileged
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* thread, that will be the MSP otherwise it will be the PSP. If the PSP is used, then the
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* value of the MSP will be invalid when the interrupt handler returns because it will be a
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* pointer to an old position in the unprivileged stack. Then when the high priority
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* interrupt occurs and uses this stale MSP, there will most likely be a system failure.
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*
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* If the interrupt stack is selected, on the other hand, then the interrupt handler will
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* always set the the MSP to the interrupt stack. So when the high priority interrupt occurs,
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* it will either use the MSP of the last privileged thread to run or, in the case of the
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* nested interrupt, the interrupt stack if no privileged task has run.
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*/
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# if defined(CONFIG_NUTTX_KERNEL) && CONFIG_ARCH_INTERRUPTSTACK < 4
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# error Interrupt stack must be used with high priority interrupts in kernel mode
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# endif
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/* Use the the BASEPRI to control interrupts is required if nested, high
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* priority interrupts are supported.
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*/
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# ifndef CONFIG_ARMV7M_USEBASEPRI
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# error CONFIG_ARMV7M_USEBASEPRI must be used with CONFIG_ARCH_HIPRI_INTERRUPT
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# endif
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#endif
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/* Memory Map ***********************************************************************************/
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/*
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* 0x0000:0000 - Beginning of FLASH. Address of vectors
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* 0x1800:0000 - Start of CPU SRAM and start of .data (_sdata)
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* - End of .data (_edata) and start of .bss (_sbss)
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@ -637,23 +666,39 @@ kinetis_common:
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stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */
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#endif
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#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
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/* Disable interrupts, select the stack to use for interrupt handling
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* and call up_doirq to handle the interrupt
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*/
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cpsid i /* Disable further interrupts */
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/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt
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* stack pointer. The way that this is done here prohibits nested interrupts!
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* Otherwise, we will re-use the main stack for interrupt level processing.
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#else
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/* Set the BASEPRI register so that further normal interrupts will be
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* masked. Nested, high priority may still occur, however.
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*/
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mov r2, #NVIC_SYSH_DISABLE_PRIORITY
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msr basepri, r2 /* Set the BASEPRI */
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#endif
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will set the MSP to use
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* a special special interrupt stack pointer. The way that this is done
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* here prohibits nested interrupts without some additional logic!
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*/
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ldr sp, =g_intstackbase
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str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */
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bl up_doirq /* R0=IRQ, R1=register save (msp) */
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ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */
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#else
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/* Otherwise, we will re-use the interrupted thread's stack. That may
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* mean using either MSP or PSP stack for interrupt level processing (in
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* kernel mode).
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*/
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mov sp, r1 /* We are using the main stack pointer */
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bl up_doirq /* R0=IRQ, R1=register save (msp) */
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mov r1, sp /* Recover R1=main stack pointer */
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@ -766,7 +811,10 @@ kinetis_common:
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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msr basepri, r3 /* Restore interrupts priority masking */
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#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
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cpsie i /* Re-enable interrupts */
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#endif
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#else
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msr primask, r3 /* Restore interrupts */
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#endif
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@ -2,7 +2,7 @@
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* arch/arm/src/lm/lm_vectors.S
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* arch/arm/src/chip/lm_vectors.S
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*
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* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -52,9 +52,39 @@
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/************************************************************************************
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* Preprocessor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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/* Memory Map:
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*
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#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
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/* In kernel mode without an interrupt stack, this interrupt handler will set the
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* MSP to the stack pointer of the interrupted thread. If the interrupted thread
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* was a privileged thread, that will be the MSP otherwise it will be the PSP. If
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* the PSP is used, then the value of the MSP will be invalid when the interrupt
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* handler returns because it will be a pointer to an old position in the
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* unprivileged stack. Then when the high priority interrupt occurs and uses this
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* stale MSP, there will most likely be a system failure.
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*
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* If the interrupt stack is selected, on the other hand, then the interrupt
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* handler will always set the the MSP to the interrupt stack. So when the high
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* priority interrupt occurs, it will either use the MSP of the last privileged
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* thread to run or, in the case of the nested interrupt, the interrupt stack if
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* no privileged task has run.
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*/
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# if defined(CONFIG_NUTTX_KERNEL) && CONFIG_ARCH_INTERRUPTSTACK < 4
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# error Interrupt stack must be used with high priority interrupts in kernel mode
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# endif
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/* Use the the BASEPRI to control interrupts is required if nested, high
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* priority interrupts are supported.
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*/
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# ifndef CONFIG_ARMV7M_USEBASEPRI
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# error CONFIG_ARMV7M_USEBASEPRI must be used with CONFIG_ARCH_HIPRI_INTERRUPT
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# endif
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#endif
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/* Memory Map ***********************************************************************/
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/*
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* 0x0000:0000 - Beginning of FLASH. Address of vectors (if not using bootloader)
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* 0x0002:0000 - Address of vectors if using bootloader
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* 0x0003:ffff - End of flash
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@ -240,23 +270,39 @@ lm_irqcommon:
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stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */
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#endif
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#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
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/* Disable interrupts, select the stack to use for interrupt handling
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* and call up_doirq to handle the interrupt
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*/
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cpsid i /* Disable further interrupts */
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/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt
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* stack pointer. The way that this is done here prohibits nested interrupts!
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* Otherwise, we will re-use the main stack for interrupt level processing.
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#else
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/* Set the BASEPRI register so that further normal interrupts will be
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* masked. Nested, high priority may still occur, however.
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*/
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mov r2, #NVIC_SYSH_DISABLE_PRIORITY
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msr basepri, r2 /* Set the BASEPRI */
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#endif
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will set the MSP to use
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* a special special interrupt stack pointer. The way that this is done
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* here prohibits nested interrupts without some additional logic!
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*/
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ldr sp, =g_intstackbase
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str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */
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bl up_doirq /* R0=IRQ, R1=register save (msp) */
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ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */
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#else
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/* Otherwise, we will re-use the interrupted thread's stack. That may
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* mean using either MSP or PSP stack for interrupt level processing (in
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* kernel mode).
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*/
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mov sp, r1 /* We are using the main stack pointer */
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bl up_doirq /* R0=IRQ, R1=register save (msp) */
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mov r1, sp /* Recover R1=main stack pointer */
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@ -369,7 +415,10 @@ lm_irqcommon:
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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msr basepri, r3 /* Restore interrupts priority masking */
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#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
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cpsie i /* Re-enable interrupts */
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#endif
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#else
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msr primask, r3 /* Restore interrupts */
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#endif
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@ -48,8 +48,37 @@
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/************************************************************************************************
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* Preprocessor Definitions
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************************************************************************************************/
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/* Memory Map:
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*
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/* Configuration ********************************************************************************/
|
||||
|
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#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
|
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/* In kernel mode without an interrupt stack, this interrupt handler will set the MSP to the
|
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* stack pointer of the interrupted thread. If the interrupted thread was a privileged
|
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* thread, that will be the MSP otherwise it will be the PSP. If the PSP is used, then the
|
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* value of the MSP will be invalid when the interrupt handler returns because it will be a
|
||||
* pointer to an old position in the unprivileged stack. Then when the high priority
|
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* interrupt occurs and uses this stale MSP, there will most likely be a system failure.
|
||||
*
|
||||
* If the interrupt stack is selected, on the other hand, then the interrupt handler will
|
||||
* always set the the MSP to the interrupt stack. So when the high priority interrupt occurs,
|
||||
* it will either use the MSP of the last privileged thread to run or, in the case of the
|
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* nested interrupt, the interrupt stack if no privileged task has run.
|
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*/
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# if defined(CONFIG_NUTTX_KERNEL) && CONFIG_ARCH_INTERRUPTSTACK < 4
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# error Interrupt stack must be used with high priority interrupts in kernel mode
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# endif
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/* Use the the BASEPRI to control interrupts is required if nested, high
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* priority interrupts are supported.
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*/
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# ifndef CONFIG_ARMV7M_USEBASEPRI
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# error CONFIG_ARMV7M_USEBASEPRI must be used with CONFIG_ARCH_HIPRI_INTERRUPT
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# endif
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#endif
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/* Memory Map ***********************************************************************************/
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/*
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* 0x0000:0000 - Beginning of FLASH. Address of vectors
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* 0x0003:ffff - End of flash
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* 0x1000:0000 - Start of CPU SRAM and start of .data (_sdata)
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@ -249,23 +278,39 @@ lpc17_common:
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stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */
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#endif
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#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
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/* Disable interrupts, select the stack to use for interrupt handling
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* and call up_doirq to handle the interrupt
|
||||
*/
|
||||
|
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cpsid i /* Disable further interrupts */
|
||||
|
||||
/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt
|
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* stack pointer. The way that this is done here prohibits nested interrupts!
|
||||
* Otherwise, we will re-use the main stack for interrupt level processing.
|
||||
#else
|
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/* Set the BASEPRI register so that further normal interrupts will be
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* masked. Nested, high priority may still occur, however.
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*/
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mov r2, #NVIC_SYSH_DISABLE_PRIORITY
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msr basepri, r2 /* Set the BASEPRI */
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#endif
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will set the MSP to use
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* a special special interrupt stack pointer. The way that this is done
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* here prohibits nested interrupts without some additional logic!
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*/
|
||||
|
||||
ldr sp, =g_intstackbase
|
||||
str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */
|
||||
bl up_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */
|
||||
|
||||
#else
|
||||
/* Otherwise, we will re-use the interrupted thread's stack. That may
|
||||
* mean using either MSP or PSP stack for interrupt level processing (in
|
||||
* kernel mode).
|
||||
*/
|
||||
|
||||
mov sp, r1 /* We are using the main stack pointer */
|
||||
bl up_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
mov r1, sp /* Recover R1=main stack pointer */
|
||||
@ -378,7 +423,10 @@ lpc17_common:
|
||||
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
msr basepri, r3 /* Restore interrupts priority masking */
|
||||
#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
|
||||
cpsie i /* Re-enable interrupts */
|
||||
#endif
|
||||
|
||||
#else
|
||||
msr primask, r3 /* Restore interrupts */
|
||||
#endif
|
||||
|
||||
@ -46,9 +46,37 @@
|
||||
/************************************************************************************************
|
||||
* Preprocessor Definitions
|
||||
************************************************************************************************/
|
||||
/* Configuration ********************************************************************************/
|
||||
|
||||
/* Memory Map:
|
||||
*
|
||||
#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
|
||||
/* In kernel mode without an interrupt stack, this interrupt handler will set the MSP to the
|
||||
* stack pointer of the interrupted thread. If the interrupted thread was a privileged
|
||||
* thread, that will be the MSP otherwise it will be the PSP. If the PSP is used, then the
|
||||
* value of the MSP will be invalid when the interrupt handler returns because it will be a
|
||||
* pointer to an old position in the unprivileged stack. Then when the high priority
|
||||
* interrupt occurs and uses this stale MSP, there will most likely be a system failure.
|
||||
*
|
||||
* If the interrupt stack is selected, on the other hand, then the interrupt handler will
|
||||
* always set the the MSP to the interrupt stack. So when the high priority interrupt occurs,
|
||||
* it will either use the MSP of the last privileged thread to run or, in the case of the
|
||||
* nested interrupt, the interrupt stack if no privileged task has run.
|
||||
*/
|
||||
|
||||
# if defined(CONFIG_NUTTX_KERNEL) && CONFIG_ARCH_INTERRUPTSTACK < 4
|
||||
# error Interrupt stack must be used with high priority interrupts in kernel mode
|
||||
# endif
|
||||
|
||||
/* Use the the BASEPRI to control interrupts is required if nested, high
|
||||
* priority interrupts are supported.
|
||||
*/
|
||||
|
||||
# ifndef CONFIG_ARMV7M_USEBASEPRI
|
||||
# error CONFIG_ARMV7M_USEBASEPRI must be used with CONFIG_ARCH_HIPRI_INTERRUPT
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Memory Map ***********************************************************************************/
|
||||
/*
|
||||
* 0x0800:0000 - Beginning of FLASH. Address of vectors. Mapped to address 0x0000:0000 at boot
|
||||
* time.
|
||||
* 0x0803:ffff - End of flash
|
||||
@ -255,23 +283,39 @@ sam_common:
|
||||
stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
|
||||
/* Disable interrupts, select the stack to use for interrupt handling
|
||||
* and call up_doirq to handle the interrupt
|
||||
*/
|
||||
|
||||
cpsid i /* Disable further interrupts */
|
||||
|
||||
/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt
|
||||
* stack pointer. The way that this is done here prohibits nested interrupts!
|
||||
* Otherwise, we will re-use the main stack for interrupt level processing.
|
||||
#else
|
||||
/* Set the BASEPRI register so that further normal interrupts will be
|
||||
* masked. Nested, high priority may still occur, however.
|
||||
*/
|
||||
|
||||
mov r2, #NVIC_SYSH_DISABLE_PRIORITY
|
||||
msr basepri, r2 /* Set the BASEPRI */
|
||||
#endif
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will set the MSP to use
|
||||
* a special special interrupt stack pointer. The way that this is done
|
||||
* here prohibits nested interrupts without some additional logic!
|
||||
*/
|
||||
|
||||
ldr sp, =g_intstackbase
|
||||
str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */
|
||||
bl up_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */
|
||||
|
||||
#else
|
||||
/* Otherwise, we will re-use the interrupted thread's stack. That may
|
||||
* mean using either MSP or PSP stack for interrupt level processing (in
|
||||
* kernel mode).
|
||||
*/
|
||||
|
||||
mov sp, r1 /* We are using the main stack pointer */
|
||||
bl up_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
mov r1, sp /* Recover R1=main stack pointer */
|
||||
@ -384,7 +428,10 @@ sam_common:
|
||||
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
msr basepri, r3 /* Restore interrupts priority masking */
|
||||
#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
|
||||
cpsie i /* Re-enable interrupts */
|
||||
#endif
|
||||
|
||||
#else
|
||||
msr primask, r3 /* Restore interrupts */
|
||||
#endif
|
||||
|
||||
@ -52,8 +52,39 @@
|
||||
/************************************************************************************
|
||||
* Preprocessor Definitions
|
||||
************************************************************************************/
|
||||
/* Memory Map:
|
||||
*
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
|
||||
/* In kernel mode without an interrupt stack, this interrupt handler will set the
|
||||
* MSP to the stack pointer of the interrupted thread. If the interrupted thread
|
||||
* was a privileged thread, that will be the MSP otherwise it will be the PSP. If
|
||||
* the PSP is used, then the value of the MSP will be invalid when the interrupt
|
||||
* handler returns because it will be a pointer to an old position in the
|
||||
* unprivileged stack. Then when the high priority interrupt occurs and uses this
|
||||
* stale MSP, there will most likely be a system failure.
|
||||
*
|
||||
* If the interrupt stack is selected, on the other hand, then the interrupt
|
||||
* handler will always set the the MSP to the interrupt stack. So when the high
|
||||
* priority interrupt occurs, it will either use the MSP of the last privileged
|
||||
* thread to run or, in the case of the nested interrupt, the interrupt stack if
|
||||
* no privileged task has run.
|
||||
*/
|
||||
|
||||
# if defined(CONFIG_NUTTX_KERNEL) && CONFIG_ARCH_INTERRUPTSTACK < 4
|
||||
# error Interrupt stack must be used with high priority interrupts in kernel mode
|
||||
# endif
|
||||
|
||||
/* Use the the BASEPRI to control interrupts is required if nested, high
|
||||
* priority interrupts are supported.
|
||||
*/
|
||||
|
||||
# ifndef CONFIG_ARMV7M_USEBASEPRI
|
||||
# error CONFIG_ARMV7M_USEBASEPRI must be used with CONFIG_ARCH_HIPRI_INTERRUPT
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Memory Map ***********************************************************************/
|
||||
/*
|
||||
* 0x0800:0000 - Beginning of FLASH. Address of vectors (if not using bootloader)
|
||||
* Mapped to address 0x0000:0000 at boot time.
|
||||
* 0x0800:3000 - Address of vectors if using bootloader
|
||||
@ -262,23 +293,39 @@ stm32_common:
|
||||
stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
|
||||
/* Disable interrupts, select the stack to use for interrupt handling
|
||||
* and call up_doirq to handle the interrupt
|
||||
*/
|
||||
|
||||
cpsid i /* Disable further interrupts */
|
||||
|
||||
/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt
|
||||
* stack pointer. The way that this is done here prohibits nested interrupts!
|
||||
* Otherwise, we will re-use the main stack for interrupt level processing.
|
||||
#else
|
||||
/* Set the BASEPRI register so that further normal interrupts will be
|
||||
* masked. Nested, high priority may still occur, however.
|
||||
*/
|
||||
|
||||
mov r2, #NVIC_SYSH_DISABLE_PRIORITY
|
||||
msr basepri, r2 /* Set the BASEPRI */
|
||||
#endif
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will set the MSP to use
|
||||
* a special special interrupt stack pointer. The way that this is done
|
||||
* here prohibits nested interrupts without some additional logic!
|
||||
*/
|
||||
|
||||
ldr sp, =g_intstackbase
|
||||
str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */
|
||||
bl up_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */
|
||||
|
||||
#else
|
||||
/* Otherwise, we will re-use the interrupted thread's stack. That may
|
||||
* mean using either MSP or PSP stack for interrupt level processing (in
|
||||
* kernel mode).
|
||||
*/
|
||||
|
||||
mov sp, r1 /* We are using the main stack pointer */
|
||||
bl up_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
mov r1, sp /* Recover R1=main stack pointer */
|
||||
@ -391,7 +438,10 @@ stm32_common:
|
||||
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
msr basepri, r3 /* Restore interrupts priority masking */
|
||||
#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
|
||||
cpsie i /* Re-enable interrupts */
|
||||
#endif
|
||||
|
||||
#else
|
||||
msr primask, r3 /* Restore interrupts */
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user