From 5f8cde796c75f91c675641039270572818e645a2 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Sun, 29 Apr 2007 22:17:11 +0000
Subject: [PATCH] Fix several typos.

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@195 42af7a65-404d-4744-a932-0658087f49c3
---
 arch/arm/src/lpc214x/lpc214x_head.S | 25 ++++++++-----------------
 1 file changed, 8 insertions(+), 17 deletions(-)

diff --git a/arch/arm/src/lpc214x/lpc214x_head.S b/arch/arm/src/lpc214x/lpc214x_head.S
index f52d6730ae..3d7c54db01 100644
--- a/arch/arm/src/lpc214x/lpc214x_head.S
+++ b/arch/arm/src/lpc214x/lpc214x_head.S
@@ -80,22 +80,14 @@
 
 /* Phase Locked Loop (PLL) initialization values
  *
- * <e> PLL Setup
- * <i> 
- * <i> CCLK - Processor Clock
- * <i> Fcco - PLL Oscillator
- *   <o1.0..4>   MSEL: PLL Multiplier Selection
- *               <1-32><#-1>
- *               <i> PLL Multiplier "M" Value
- *               <i> CCLK = M * Fosc
- *   <o1.5..6>   PSEL: PLL Divider Selection
- *               <0=> 1   <1=> 2   <2=> 4   <3=> 8
- *               <i> PLL Divider "P" Value
- *               <i> Fcco = CCLK * 2 * P
- *               <i> 156MHz <= Fcco <= 320MHz
- * </e>
-*/
-#defin LPC214X_PLLCFG_VALUE 0x00000024
+ * BIT 0:4 MSEL: PLL Multiplier "M" Value
+ *               CCLK = M * Fosc
+ * BIT 5:6 PSEL: PLL Divider "P" Value 
+ *               Fcco = CCLK * 2 * P
+ *               156MHz <= Fcco <= 320MHz
+ */
+
+#define LPC214X_PLLCFG_VALUE 0x00000024
 
 /* Memory Accelerator Module (MAM) initialization values
  *
@@ -333,7 +325,6 @@ _vector_table:
 .Lfiqhandler:
 	.long	up_vectorfiq
 	.size	_vector_table, . - _vector_table
-	.end
 
 /********************************************************************
  * Name: __start