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Changes from review of last PR

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This commit is contained in:
Gregory Nutt 2016-05-17 17:39:27 -06:00
parent 4aeb06a79d
commit 5fc619eb1b
6 changed files with 29 additions and 30 deletions
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3
arch/arm/src/stm32/Kconfig
View File

@ -5653,7 +5653,8 @@ config STM32_SERIALBRK_BSDCOMPAT
The current STM32 U[S]ARTS have no way to leave the break (TX=LOW)
on because the SW starts the break and then the HW automatically clears
the break. This makes it is difficult to sent a long break.
endmenu
endmenu # U[S]ART Configuration
config STM32_USART_SINGLEWIRE
bool "Single Wire Support"

17
arch/arm/src/stm32/stm32_serial.c
View File

@ -255,8 +255,7 @@
# define PM_IDLE_DOMAIN 0 /* Revisit */
#endif
/*
* Keep track if a Break was set
/* Keep track if a Break was set
*
* Note:
*
@ -264,12 +263,12 @@
* register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE
* 2) USART_CR3_EIE is also carried in the up_dev_s ie member.
*
* see up_restoreusartint where the masking is done.
* See up_restoreusartint where the masking is done.
*/
#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
#endif
#ifdef USE_SERIALDRIVER
@ -2075,7 +2074,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
#endif /* CONFIG_SERIAL_TERMIOS */
#ifdef CONFIG_STM32_USART_BREAKS
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
{
irqstate_t flags;
@ -2100,7 +2099,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
{
uint32_t cr1;
irqstate_t flags;
flags = enter_critical_section();
@ -2118,7 +2116,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
leave_critical_section(flags);
}
break;
# else
# else
case TIOCSBRK: /* No BSD compatibility: Turn break on for M bit times */
{
uint32_t cr1;
@ -2142,7 +2140,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
leave_critical_section(flags);
}
break;
# endif
# endif
#endif
default:
@ -2531,6 +2529,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
ie |= USART_CR1_TCIE;
}
# endif
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
{

3
arch/arm/src/stm32f7/Kconfig
View File

@ -681,7 +681,8 @@ config STM32F7_SERIALBRK_BSDCOMPAT
The current STM32 U[S]ARTS have no way to leave the break (TX=LOW)
on because the SW starts the break and then the HW automatically clears
the break. This makes it is difficult to sent a long break.
endmenu
endmenu # U[S]ART Configuration
config STM32F7_CUSTOM_CLOCKCONFIG
bool "Custom clock configuration"

17
arch/arm/src/stm32f7/stm32_serial.c
View File

@ -208,8 +208,7 @@
# define PM_IDLE_DOMAIN 0 /* Revisit */
#endif
/*
* Keep track if a Break was set
/* Keep track if a Break was set
*
* Note:
*
@ -217,12 +216,12 @@
* register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE
* 2) USART_CR3_EIE is also carried in the up_dev_s ie member.
*
* see up_restoreusartint where the masking is done.
* See up_restoreusartint where the masking is done.
*/
#ifdef CONFIG_STM32F7_SERIALBRK_BSDCOMPAT
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
#endif
#ifdef USE_SERIALDRIVER
@ -1982,7 +1981,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
#endif /* CONFIG_SERIAL_TERMIOS */
#ifdef CONFIG_STM32F7_USART_BREAKS
# ifdef CONFIG_STM32F7_SERIALBRK_BSDCOMPAT
# ifdef CONFIG_STM32F7_SERIALBRK_BSDCOMPAT
case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
{
irqstate_t flags;
@ -2007,7 +2006,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
{
uint32_t cr1;
irqstate_t flags;
flags = enter_critical_section();
@ -2025,7 +2023,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
leave_critical_section(flags);
}
break;
# else
# else
case TIOCSBRK: /* No BSD compatibility: Turn break on for M bit times */
{
uint32_t cr1;
@ -2049,7 +2047,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
leave_critical_section(flags);
}
break;
# endif
# endif
#endif
default:
@ -2461,6 +2459,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
ie |= USART_CR1_TCIE;
}
# endif
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
{

2
arch/arm/src/stm32l4/Kconfig
View File

@ -802,7 +802,7 @@ config STM32L4_SERIALBRK_BSDCOMPAT
on because the SW starts the break and then the HW automatically clears
the break. This makes it is difficult to sent a long break.
endmenu
endmenu # U[S]ART Configuration
menu "SPI Configuration"
depends on STM32L4_SPI

17
arch/arm/src/stm32l4/stm32l4_serial.c
View File

@ -208,8 +208,7 @@
# define PM_IDLE_DOMAIN 0 /* Revisit */
#endif
/*
* Keep track if a Break was set
/* Keep track if a Break was set
*
* Note:
*
@ -217,12 +216,12 @@
* register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE
* 2) USART_CR3_EIE is also carried in the up_dev_s ie member.
*
* see up_restoreusartint where the masking is done.
* See up_restoreusartint where the masking is done.
*/
#ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
#endif
#ifdef USE_SERIALDRIVER
@ -1738,7 +1737,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
#endif /* CONFIG_SERIAL_TERMIOS */
#ifdef CONFIG_STM32L4_USART_BREAKS
# ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT
# ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT
case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
{
irqstate_t flags;
@ -1763,7 +1762,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
{
uint32_t cr1;
irqstate_t flags;
flags = enter_critical_section();
@ -1781,7 +1779,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
leave_critical_section(flags);
}
break;
# else
# else
case TIOCSBRK: /* No BSD compatibility: Turn break on for M bit times */
{
uint32_t cr1;
@ -1805,7 +1803,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
leave_critical_section(flags);
}
break;
# endif
# endif
#endif
default:
@ -2194,6 +2192,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
ie |= USART_CR1_TCIE;
}
# endif
# ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT
if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
{