basic RTC functionality implemented
This commit is contained in:
ziggurat29
parent
998dc0b474
commit
600a9b6981
@ -421,6 +421,28 @@ config ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG
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---help---
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Enables special, board-specific STM32 clock configuration.
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choice
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prompt "RTC clock source"
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default STM32L4_RTC_LSECLOCK
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depends on RTC
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config STM32L4_RTC_LSECLOCK
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bool "LSE clock"
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---help---
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Drive the RTC with the LSE clock
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config STM32L4_RTC_LSICLOCK
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bool "LSI clock"
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---help---
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Drive the RTC with the LSI clock
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config STM32L4_RTC_HSECLOCK
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bool "HSE clock"
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---help---
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Drive the RTC with the HSE clock, divided down to 1MHz.
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endchoice
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config STM32L4_SAI1PLL
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bool "SAI1PLL"
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default n
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@ -141,9 +141,13 @@ CHIP_CSRCS += stm32l4_exti_pwr.c
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endif
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ifeq ($(CONFIG_RTC),y)
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CHIP_CSRCS += stm32l4_rtcc.c
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ifeq ($(CONFIG_RTC_ALARM),y)
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CHIP_CSRCS += stm32l4_exti_alarm.c
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endif
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ifeq ($(CONFIG_RTC_DRIVER),y)
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CHIP_CSRCS += stm32l4_rtc_lowerhalf.c
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endif
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endif
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ifeq ($(CONFIG_DEBUG),y)
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@ -19,7 +19,7 @@ HSI : OK
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HSE : To be tested
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PLL : Works @ 80 MHz
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MSI : TODO
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LSE : TODO, including calibration
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LSE : works, but TODO autotrim of MSI, etc
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RCC : All registers defined, peripherals enabled, basic clock working
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SYSCTL : All registers defined
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USART : Working in normal mode (no DMA, to be tested, code is written)
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@ -28,7 +28,7 @@ SRAM2 : Should work with enough MM regions
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FIREWALL : Code written, to be tested, requires support from ldscript
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SPI : Code written, to be tested, including DMA
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I2C : Registers defined
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RTC : TODO
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RTC : works
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QSPI : TODO (port from stm32f7)
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CAN : TODO
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OTGFS : TODO
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402
arch/arm/src/stm32l4/chip/stm32l4_rtcc.h
Normal file
402
arch/arm/src/stm32l4/chip/stm32l4_rtcc.h
Normal file
@ -0,0 +1,402 @@
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/************************************************************************************
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* arch/arm/src/stm32l4/chip/stm32l4_rtcc.h.h
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*
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* Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.
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* Author: dev@ziggurat29.com
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_RTCC_H
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#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_RTCC_H
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32L4_RTC_TR_OFFSET 0x0000 /* RTC time register */
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#define STM32L4_RTC_DR_OFFSET 0x0004 /* RTC date register */
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#define STM32L4_RTC_CR_OFFSET 0x0008 /* RTC control register */
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#define STM32L4_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */
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#define STM32L4_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */
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#define STM32L4_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */
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#define STM32L4_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */
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#define STM32L4_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */
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#define STM32L4_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */
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#define STM32L4_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */
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#define STM32L4_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */
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#define STM32L4_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */
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#define STM32L4_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */
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#define STM32L4_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */
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#define STM32L4_RTC_CALR_OFFSET 0x003c /* RTC calibration register */
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#define STM32L4_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */
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#define STM32L4_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */
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#define STM32L4_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */
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#define STM32L4_RTC_OR_OFFSET 0x004c /* RTC option register */
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#define STM32L4_RTC_BKR_OFFSET(n) (0x0050+((n)<<2))
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#define STM32L4_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */
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#define STM32L4_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */
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#define STM32L4_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */
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#define STM32L4_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */
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#define STM32L4_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */
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#define STM32L4_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */
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#define STM32L4_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */
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#define STM32L4_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */
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#define STM32L4_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */
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#define STM32L4_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */
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#define STM32L4_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */
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#define STM32L4_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */
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#define STM32L4_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */
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#define STM32L4_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */
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#define STM32L4_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */
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#define STM32L4_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */
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#define STM32L4_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */
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#define STM32L4_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */
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#define STM32L4_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */
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#define STM32L4_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */
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#define STM32L4_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */
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#define STM32L4_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */
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#define STM32L4_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */
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#define STM32L4_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */
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#define STM32L4_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */
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#define STM32L4_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */
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#define STM32L4_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */
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#define STM32L4_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */
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#define STM32L4_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */
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#define STM32L4_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */
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#define STM32L4_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */
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#define STM32L4_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */
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/* Register Addresses ***************************************************************/
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#define STM32L4_RTC_TR (STM32L4_RTC_BASE+STM32L4_RTC_TR_OFFSET)
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#define STM32L4_RTC_DR (STM32L4_RTC_BASE+STM32L4_RTC_DR_OFFSET)
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#define STM32L4_RTC_CR (STM32L4_RTC_BASE+STM32L4_RTC_CR_OFFSET)
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#define STM32L4_RTC_ISR (STM32L4_RTC_BASE+STM32L4_RTC_ISR_OFFSET)
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#define STM32L4_RTC_PRER (STM32L4_RTC_BASE+STM32L4_RTC_PRER_OFFSET)
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#define STM32L4_RTC_WUTR (STM32L4_RTC_BASE+STM32L4_RTC_WUTR_OFFSET)
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#define STM32L4_RTC_ALRMAR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMAR_OFFSET)
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#define STM32L4_RTC_ALRMBR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMBR_OFFSET)
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#define STM32L4_RTC_WPR (STM32L4_RTC_BASE+STM32L4_RTC_WPR_OFFSET)
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#define STM32L4_RTC_SSR (STM32L4_RTC_BASE+STM32L4_RTC_SSR_OFFSET)
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#define STM32L4_RTC_SHIFTR (STM32L4_RTC_BASE+STM32L4_RTC_SHIFTR_OFFSET)
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#define STM32L4_RTC_TSTR (STM32L4_RTC_BASE+STM32L4_RTC_TSTR_OFFSET)
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#define STM32L4_RTC_TSDR (STM32L4_RTC_BASE+STM32L4_RTC_TSDR_OFFSET)
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#define STM32L4_RTC_TSSSR (STM32L4_RTC_BASE+STM32L4_RTC_TSSSR_OFFSET)
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#define STM32L4_RTC_CALR (STM32L4_RTC_BASE+STM32L4_RTC_CALR_OFFSET)
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#define STM32L4_RTC_TAMPCR (STM32L4_RTC_BASE+STM32L4_RTC_TAMPCR_OFFSET)
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#define STM32L4_RTC_ALRMASSR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMASSR_OFFSET)
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#define STM32L4_RTC_ALRMBSSR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMBSSR_OFFSET)
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#define STM32L4_RTC_OR (STM32L4_RTC_BASE+STM32L4_RTC_OR_OFFSET)
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#define STM32L4_RTC_BKR(n) (STM32L4_RTC_BASE+STM32L4_RTC_BKR_OFFSET(n))
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#define STM32L4_RTC_BK0R (STM32L4_RTC_BASE+STM32L4_RTC_BK0R_OFFSET)
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#define STM32L4_RTC_BK1R (STM32L4_RTC_BASE+STM32L4_RTC_BK1R_OFFSET)
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#define STM32L4_RTC_BK2R (STM32L4_RTC_BASE+STM32L4_RTC_BK2R_OFFSET)
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#define STM32L4_RTC_BK3R (STM32L4_RTC_BASE+STM32L4_RTC_BK3R_OFFSET)
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#define STM32L4_RTC_BK4R (STM32L4_RTC_BASE+STM32L4_RTC_BK4R_OFFSET)
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#define STM32L4_RTC_BK5R (STM32L4_RTC_BASE+STM32L4_RTC_BK5R_OFFSET)
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#define STM32L4_RTC_BK6R (STM32L4_RTC_BASE+STM32L4_RTC_BK6R_OFFSET)
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#define STM32L4_RTC_BK7R (STM32L4_RTC_BASE+STM32L4_RTC_BK7R_OFFSET)
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#define STM32L4_RTC_BK8R (STM32L4_RTC_BASE+STM32L4_RTC_BK8R_OFFSET)
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#define STM32L4_RTC_BK9R (STM32L4_RTC_BASE+STM32L4_RTC_BK9R_OFFSET)
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#define STM32L4_RTC_BK10R (STM32L4_RTC_BASE+STM32L4_RTC_BK10R_OFFSET)
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#define STM32L4_RTC_BK11R (STM32L4_RTC_BASE+STM32L4_RTC_BK11R_OFFSET)
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#define STM32L4_RTC_BK12R (STM32L4_RTC_BASE+STM32L4_RTC_BK12R_OFFSET)
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#define STM32L4_RTC_BK13R (STM32L4_RTC_BASE+STM32L4_RTC_BK13R_OFFSET)
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#define STM32L4_RTC_BK14R (STM32L4_RTC_BASE+STM32L4_RTC_BK14R_OFFSET)
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#define STM32L4_RTC_BK15R (STM32L4_RTC_BASE+STM32L4_RTC_BK15R_OFFSET)
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#define STM32L4_RTC_BK16R (STM32L4_RTC_BASE+STM32L4_RTC_BK16R_OFFSET)
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#define STM32L4_RTC_BK17R (STM32L4_RTC_BASE+STM32L4_RTC_BK17R_OFFSET)
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#define STM32L4_RTC_BK18R (STM32L4_RTC_BASE+STM32L4_RTC_BK18R_OFFSET)
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#define STM32L4_RTC_BK19R (STM32L4_RTC_BASE+STM32L4_RTC_BK19R_OFFSET)
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#define STM32L4_RTC_BK20R (STM32L4_RTC_BASE+STM32L4_RTC_BK20R_OFFSET)
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#define STM32L4_RTC_BK21R (STM32L4_RTC_BASE+STM32L4_RTC_BK21R_OFFSET)
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#define STM32L4_RTC_BK22R (STM32L4_RTC_BASE+STM32L4_RTC_BK22R_OFFSET)
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#define STM32L4_RTC_BK23R (STM32L4_RTC_BASE+STM32L4_RTC_BK23R_OFFSET)
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#define STM32L4_RTC_BK24R (STM32L4_RTC_BASE+STM32L4_RTC_BK24R_OFFSET)
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#define STM32L4_RTC_BK25R (STM32L4_RTC_BASE+STM32L4_RTC_BK25R_OFFSET)
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#define STM32L4_RTC_BK26R (STM32L4_RTC_BASE+STM32L4_RTC_BK26R_OFFSET)
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#define STM32L4_RTC_BK27R (STM32L4_RTC_BASE+STM32L4_RTC_BK27R_OFFSET)
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#define STM32L4_RTC_BK28R (STM32L4_RTC_BASE+STM32L4_RTC_BK28R_OFFSET)
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#define STM32L4_RTC_BK29R (STM32L4_RTC_BASE+STM32L4_RTC_BK29R_OFFSET)
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#define STM32L4_RTC_BK30R (STM32L4_RTC_BASE+STM32L4_RTC_BK30R_OFFSET)
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#define STM32L4_RTC_BK31R (STM32L4_RTC_BASE+STM32L4_RTC_BK31R_OFFSET)
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# define STM32L4_RTC_BKCOUNT 32
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/* Register Bitfield Definitions ****************************************************/
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/* RTC time register */
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#define RTC_TR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format */
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#define RTC_TR_SU_MASK (15 << RTC_TR_SU_SHIFT)
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#define RTC_TR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format */
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#define RTC_TR_ST_MASK (7 << RTC_TR_ST_SHIFT)
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#define RTC_TR_MNU_SHIFT (8) /* Bit 8-11: Minute units in BCD format */
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#define RTC_TR_MNU_MASK (15 << RTC_TR_MNU_SHIFT)
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#define RTC_TR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format */
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#define RTC_TR_MNT_MASK (7 << RTC_TR_MNT_SHIFT)
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#define RTC_TR_HU_SHIFT (16) /* Bit 16-19: Hour units in BCD format */
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#define RTC_TR_HU_MASK (15 << RTC_TR_HU_SHIFT)
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#define RTC_TR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format */
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#define RTC_TR_HT_MASK (3 << RTC_TR_HT_SHIFT)
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#define RTC_TR_PM (1 << 22) /* Bit 22: AM/PM notation */
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#define RTC_TR_RESERVED_BITS (0xff808080)
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/* RTC date register */
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#define RTC_DR_DU_SHIFT (0) /* Bits 0-3: Date units in BCD format */
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#define RTC_DR_DU_MASK (15 << RTC_DR_DU_SHIFT)
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#define RTC_DR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */
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#define RTC_DR_DT_MASK (3 << RTC_DR_DT_SHIFT)
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#define RTC_DR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */
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#define RTC_DR_MU_MASK (15 << RTC_DR_MU_SHIFT)
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#define RTC_DR_MT (1 << 12) /* Bit 12: Month tens in BCD format */
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#define RTC_DR_WDU_SHIFT (13) /* Bits 13-15: Week day units */
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#define RTC_DR_WDU_MASK (7 << RTC_DR_WDU_SHIFT)
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# define RTC_DR_WDU_MONDAY (1 << RTC_DR_WDU_SHIFT)
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# define RTC_DR_WDU_TUESDAY (2 << RTC_DR_WDU_SHIFT)
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# define RTC_DR_WDU_WEDNESDAY (3 << RTC_DR_WDU_SHIFT)
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# define RTC_DR_WDU_THURSDAY (4 << RTC_DR_WDU_SHIFT)
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# define RTC_DR_WDU_FRIDAY (5 << RTC_DR_WDU_SHIFT)
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# define RTC_DR_WDU_SATURDAY (6 << RTC_DR_WDU_SHIFT)
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# define RTC_DR_WDU_SUNDAY (7 << RTC_DR_WDU_SHIFT)
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#define RTC_DR_YU_SHIFT (16) /* Bits 16-19: Year units in BCD format */
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#define RTC_DR_YU_MASK (15 << RTC_DR_YU_SHIFT)
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#define RTC_DR_YT_SHIFT (20) /* Bits 20-23: Year tens in BCD format */
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#define RTC_DR_YT_MASK (15 << RTC_DR_YT_SHIFT)
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#define RTC_DR_RESERVED_BITS (0xff0000c0)
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/* RTC control register */
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#define RTC_CR_WUCKSEL_SHIFT (0) /* Bits 0-2: Wakeup clock selection */
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#define RTC_CR_WUCKSEL_MASK (7 << RTC_CR_WUCKSEL_SHIFT)
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# define RTC_CR_WUCKSEL_RTCDIV16 (0 << RTC_CR_WUCKSEL_SHIFT) /* 000: RTC/16 clock is selected */
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# define RTC_CR_WUCKSEL_RTCDIV8 (1 << RTC_CR_WUCKSEL_SHIFT) /* 001: RTC/8 clock is selected */
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# define RTC_CR_WUCKSEL_RTCDIV4 (2 << RTC_CR_WUCKSEL_SHIFT) /* 010: RTC/4 clock is selected */
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# define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */
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# define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */
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# define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */
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#define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */
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#define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */
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#define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */
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#define RTC_CR_FMT (1 << 6) /* Bit 6: Hour format */
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/* Bit 7: reserved */
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#define RTC_CR_ALRAE (1 << 8) /* Bit 8: Alarm A enable */
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#define RTC_CR_ALRBE (1 << 9) /* Bit 9: Alarm B enable */
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#define RTC_CR_WUTE (1 << 10) /* Bit 10: Wakeup timer enable */
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#define RTC_CR_TSE (1 << 11) /* Bit 11: Time stamp enable */
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#define RTC_CR_ALRAIE (1 << 12) /* Bit 12: Alarm A interrupt enable */
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#define RTC_CR_ALRBIE (1 << 13) /* Bit 13: Alarm B interrupt enable */
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#define RTC_CR_WUTIE (1 << 14) /* Bit 14: Wakeup timer interrupt enable */
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#define RTC_CR_TSIE (1 << 15) /* Bit 15: Timestamp interrupt enable */
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#define RTC_CR_ADD1H (1 << 16) /* Bit 16: Add 1 hour (summer time change) */
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#define RTC_CR_SUB1H (1 << 17) /* Bit 17: Subtract 1 hour (winter time change) */
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#define RTC_CR_BKP (1 << 18) /* Bit 18: Backup */
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#define RTC_CR_COSEL (1 << 19) /* Bit 19: Calibration output selection */
|
||||
#define RTC_CR_POL (1 << 20) /* Bit 20: Output polarity */
|
||||
#define RTC_CR_OSEL_SHIFT (21) /* Bits 21-22: Output selection */
|
||||
#define RTC_CR_OSEL_MASK (3 << RTC_CR_OSEL_SHIFT)
|
||||
# define RTC_CR_OSEL_DISABLED (0 << RTC_CR_OSEL_SHIFT) /* 00: Output disabled */
|
||||
# define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */
|
||||
# define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */
|
||||
# define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */
|
||||
#define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */
|
||||
#define RTC_CR_ITSE (1 << 24) /* Bit 24: Timestamp on internal event enable */
|
||||
|
||||
/* RTC initialization and status register */
|
||||
|
||||
#define RTC_ISR_ALRAWF (1 << 0) /* Bit 0: Alarm A write flag */
|
||||
#define RTC_ISR_ALRBWF (1 << 1) /* Bit 1: Alarm B write flag */
|
||||
#define RTC_ISR_WUTWF (1 << 2) /* Bit 2: Wakeup timer write flag */
|
||||
#define RTC_ISR_SHPF (1 << 3) /* Bit 3: Shift operation pending */
|
||||
#define RTC_ISR_INITS (1 << 4) /* Bit 4: Initialization status flag */
|
||||
#define RTC_ISR_RSF (1 << 5) /* Bit 5: Registers synchronization flag */
|
||||
#define RTC_ISR_INITF (1 << 6) /* Bit 6: Initialization flag */
|
||||
#define RTC_ISR_INIT (1 << 7) /* Bit 7: Initialization mode */
|
||||
#define RTC_ISR_ALRAF (1 << 8) /* Bit 8: Alarm A flag */
|
||||
#define RTC_ISR_ALRBF (1 << 9) /* Bit 9: Alarm B flag */
|
||||
#define RTC_ISR_WUTF (1 << 10) /* Bit 10: Wakeup timer flag */
|
||||
#define RTC_ISR_TSF (1 << 11) /* Bit 11: Timestamp flag */
|
||||
#define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */
|
||||
#define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper detection flag */
|
||||
#define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: TAMPER2 detection flag */
|
||||
#define RTC_ISR_TAMP3F (1 << 15) /* Bit 15: TAMPER3 detection flag */
|
||||
#define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending Flag */
|
||||
#define RTC_ISR_ITSF (1 << 17) /* Bit 17: Recalibration pending Flag */
|
||||
#define RTC_ISR_ALLFLAGS (0x0003ffff)
|
||||
|
||||
/* RTC prescaler register */
|
||||
|
||||
#define RTC_PRER_PREDIV_S_SHIFT (0) /* Bits 0-14: Synchronous prescaler factor */
|
||||
#define RTC_PRER_PREDIV_S_MASK (0x7fff << RTC_PRER_PREDIV_S_SHIFT)
|
||||
#define RTC_PRER_PREDIV_A_SHIFT (16) /* Bits 16-22: Asynchronous prescaler factor */
|
||||
#define RTC_PRER_PREDIV_A_MASK (0x7f << RTC_PRER_PREDIV_A_SHIFT)
|
||||
|
||||
/* RTC wakeup timer register */
|
||||
|
||||
#define RTC_WUTR_MASK (0xffff) /* Bits 15:0 Wakeup auto-reload value bits */
|
||||
|
||||
/* RTC alarm A/B registers */
|
||||
|
||||
#define RTC_ALRMR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */
|
||||
#define RTC_ALRMR_SU_MASK (15 << RTC_ALRMR_SU_SHIFT)
|
||||
#define RTC_ALRMR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */
|
||||
#define RTC_ALRMR_ST_MASK (7 << RTC_ALRMR_ST_SHIFT)
|
||||
#define RTC_ALRMR_MSK1 (1 << 7) /* Bit 7 : Alarm A seconds mask */
|
||||
#define RTC_ALRMR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */
|
||||
#define RTC_ALRMR_MNU_MASK (15 << RTC_ALRMR_MNU_SHIFT)
|
||||
#define RTC_ALRMR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */
|
||||
#define RTC_ALRMR_MNT_MASK (7 << RTC_ALRMR_MNT_SHIFT)
|
||||
#define RTC_ALRMR_MSK2 (1 << 15) /* Bit 15 : Alarm A minutes mask */
|
||||
#define RTC_ALRMR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */
|
||||
#define RTC_ALRMR_HU_MASK (15 << RTC_ALRMR_HU_SHIFT)
|
||||
#define RTC_ALRMR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */
|
||||
#define RTC_ALRMR_HT_MASK (3 << RTC_ALRMR_HT_SHIFT)
|
||||
#define RTC_ALRMR_PM (1 << 22) /* Bit 22 : AM/PM notation */
|
||||
#define RTC_ALRMR_MSK3 (1 << 23) /* Bit 23 : Alarm A hours mask */
|
||||
#define RTC_ALRMR_DU_SHIFT (24) /* Bits 24-27: Date units or day in BCD format. */
|
||||
#define RTC_ALRMR_DU_MASK (15 << RTC_ALRMR_DU_SHIFT)
|
||||
#define RTC_ALRMR_DT_SHIFT (28) /* Bits 28-29: Date tens in BCD format. */
|
||||
#define RTC_ALRMR_DT_MASK (3 << RTC_ALRMR_DT_SHIFT)
|
||||
#define RTC_ALRMR_WDSEL (1 << 30) /* Bit 30: Week day selection */
|
||||
#define RTC_ALRMR_MSK4 (1 << 31) /* Bit 31: Alarm A date mask */
|
||||
|
||||
/* RTC write protection register */
|
||||
|
||||
#define RTC_WPR_MASK (0xff) /* Bits 0-7: Write protection key */
|
||||
|
||||
/* RTC sub second register */
|
||||
|
||||
#define RTC_SSR_MASK (0xffff) /* Bits 0-15: Sub second value */
|
||||
|
||||
/* RTC shift control register */
|
||||
|
||||
#define RTC_SHIFTR_SUBFS_SHIFT (0) /* Bits 0-14: Subtract a fraction of a second */
|
||||
#define RTC_SHIFTR_SUBFS_MASK (0x7ffff << RTC_SHIFTR_SUBFS_SHIFT)
|
||||
#define RTC_SHIFTR_ADD1S (1 << 31) /* Bit 31: Add one second */
|
||||
|
||||
/* RTC time stamp time register */
|
||||
|
||||
#define RTC_TSTR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */
|
||||
#define RTC_TSTR_SU_MASK (15 << RTC_TSTR_SU_SHIFT)
|
||||
#define RTC_TSTR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */
|
||||
#define RTC_TSTR_ST_MASK (7 << RTC_TSTR_ST_SHIFT)
|
||||
#define RTC_TSTR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */
|
||||
#define RTC_TSTR_MNU_MASK (15 << RTC_TSTR_MNU_SHIFT)
|
||||
#define RTC_TSTR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */
|
||||
#define RTC_TSTR_MNT_MASK (7 << RTC_TSTR_MNT_SHIFT)
|
||||
#define RTC_TSTR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */
|
||||
#define RTC_TSTR_HU_MASK (15 << RTC_TSTR_HU_SHIFT)
|
||||
#define RTC_TSTR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */
|
||||
#define RTC_TSTR_HT_MASK (3 << RTC_TSTR_HT_SHIFT)
|
||||
#define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation */
|
||||
|
||||
/* RTC time stamp date register */
|
||||
|
||||
#define RTC_TSDR_DU_SHIFT (0) /* Bit 0-3: Date units in BCD format */
|
||||
#define RTC_TSDR_DU_MASK (15 << RTC_TSDR_DU_SHIFT) */
|
||||
#define RTC_TSDR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */
|
||||
#define RTC_TSDR_DT_MASK (3 << RTC_TSDR_DT_SHIFT)
|
||||
#define RTC_TSDR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */
|
||||
#define RTC_TSDR_MU_MASK (xx << RTC_TSDR_MU_SHIFT)
|
||||
#define RTC_TSDR_MT (1 << 12) /* Bit 12: Month tens in BCD format */
|
||||
#define RTC_TSDR_WDU_SHIFT (13) /* Bits 13-15: Week day units */
|
||||
#define RTC_TSDR_WDU_MASK (7 << RTC_TSDR_WDU_SHIFT)
|
||||
|
||||
/* RTC timestamp sub second register */
|
||||
|
||||
#define RTC_TSSSR_MASK (0xffff) /* Bits 0-15: Sub second value */
|
||||
|
||||
/* RTC calibration register */
|
||||
|
||||
#define RTC_CALR_CALM_SHIFT (0) /* Bits 0-8: Calibration minus */
|
||||
#define RTC_CALR_CALM_MASK (0x1ff << RTC_CALR_CALM_SHIFT)
|
||||
#define RTC_CALR_CALW16 (1 << 13) /* Bit 13: Use a 16-second calibration cycle period */
|
||||
#define RTC_CALR_CALW8 (1 << 14) /* Bit 14: Use an 8-second calibration cycle period */
|
||||
#define RTC_CALR_CALP (1 << 15) /* Bit 15: Increase frequency of RTC by 488.5 ppm */
|
||||
|
||||
/* RTC tamper configuration register */
|
||||
|
||||
#define RTC_TAMPCR_TAMP1E (1 << 0) /* Bit 0: RTC_TAMP1 input detection enable */
|
||||
#define RTC_TAMPCR_TAMP1TRG (1 << 1) /* Bit 1: Active level for RTC_TAMP1 input */
|
||||
#define RTC_TAMPCR_TAMPIE (1 << 2) /* Bit 2: Tamper interrupt enable */
|
||||
#define RTC_TAMPCR_TAMP2E (1 << 3) /* Bit 3: RTC_TAMP2 detection enable */
|
||||
#define RTC_TAMPCR_TAMP2TRG (1 << 4) /* Bit 4: Active level for RTC_TAMP2 input */
|
||||
#define RTC_TAMPCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */
|
||||
#define RTC_TAMPCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */
|
||||
#define RTC_TAMPCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */
|
||||
#define RTC_TAMPCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */
|
||||
#define RTC_TAMPCR_TAMPFREQ_MASK (7 << RTC_TAMPCR_TAMPFREQ_SHIFT)
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV32768 (0 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV16384 (1 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV8192 (2 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 8192 (4 Hz) */
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV4096 (3 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 4096 (8 Hz) */
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV2048 (4 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 2048 (16 Hz) */
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV1024 (5 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV512 (6 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV256 (7 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */
|
||||
#define RTC_TAMPCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */
|
||||
#define RTC_TAMPCR_TAMPFLT_MASK (3 << RTC_TAMPCR_TAMPFLT_SHIFT)
|
||||
#define RTC_TAMPCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */
|
||||
#define RTC_TAMPCR_TAMPPRCH_MASK (3 << RTC_TAMPCR_TAMPPRCH_SHIFT)
|
||||
# define RTC_TAMPCR_TAMPPRCH_1CYCLE (0 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 1 RTCCLK cycle */
|
||||
# define RTC_TAMPCR_TAMPPRCH_2CYCLES (1 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */
|
||||
# define RTC_TAMPCR_TAMPPRCH_4CYCLES (2 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */
|
||||
# define RTC_TAMPCR_TAMPPRCH_5CYCLES (3 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */
|
||||
#define RTC_TAMPCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */
|
||||
#define RTC_TAMPCR_TAMP1IE (1 << 16) /* Bit 16: RTC_TAMP1 interrupt enable */
|
||||
#define RTC_TAMPCR_TAMP1NOERASE (1 << 17) /* Bit 17: RTC_TAMP1 no erase */
|
||||
#define RTC_TAMPCR_TAMP1F (1 << 18) /* Bit 18: RTC_TAMP1 mask flag */
|
||||
#define RTC_TAMPCR_TAMP2IE (1 << 19) /* Bit 19: RTC_TAMP2 interrupt enable */
|
||||
#define RTC_TAMPCR_TAMP2NOERASE (1 << 20) /* Bit 20: RTC_TAMP2 no erase */
|
||||
#define RTC_TAMPCR_TAMP2MF (1 << 21) /* Bit 21: RTC_TAMP2 mask flag */
|
||||
#define RTC_TAMPCR_TAMP3IE (1 << 22) /* Bit 22: RTC_TAMP3 interrupt enable */
|
||||
#define RTC_TAMPCR_TAMP3NOERASE (1 << 23) /* Bit 23: RTC_TAMP3 no erase */
|
||||
#define RTC_TAMPCR_TAMP3MF (1 << 24) /* Bit 24: RTC_TAMP3 mask flag */
|
||||
|
||||
/* RTC alarm A/B sub second register */
|
||||
|
||||
#define RTC_ALRMSSR_SS_SHIFT (0) /* Bits 0-14: Sub second value */
|
||||
#define RTC_ALRMSSR_SS_MASK (0x7fff << RTC_ALRMSSR_SS_SHIFT)
|
||||
#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */
|
||||
#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT)
|
||||
|
||||
/* RTC option register */
|
||||
|
||||
#define RTC_OR_ALARMTYPE (1 << 0) /* Bit 0: RTC alarm type on PC13/PB14, pushpull/OD */
|
||||
#define RTC_OR_OUTRMP (1 << 1) /* Bit 1: remap output to PB14 */
|
||||
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_RTCC_H */
|
||||
@ -4,6 +4,7 @@
|
||||
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Diego Sanchez <dsanchez@nx-engineering.com>
|
||||
* dev@ziggurat29.com (adaptation to stm32l4)
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@ -77,7 +77,7 @@ void stm32l4_rcc_enablelse(void)
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32L4_RCC_BDCR);
|
||||
regval |= RCC_BDCR_LSEON | RCC_BDCR_LSEDRV_MIDHI;
|
||||
regval |= RCC_BDCR_LSEON;
|
||||
putreg32(regval,STM32L4_RCC_BDCR);
|
||||
|
||||
/* Wait for the LSE clock to be ready */
|
||||
|
||||
@ -0,0 +1,203 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l4/stm32l4_rtc.h
|
||||
*
|
||||
* Copyright (C) 2011 Uros Platise. All rights reserved.
|
||||
* Copyright (C) 2011-2013, 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Uros Platise <uros.platise@isotel.eu> (Original for the F1)
|
||||
* Gregory Nutt <gnutt@nuttx.org> (On-going support and development)
|
||||
* dev@ziggurat29.com (adaptations for STM32L4)
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_RTC_H
|
||||
#define __ARCH_ARM_SRC_STM32L4_STM32L4_RTC_H
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#include "chip/stm32l4_rtcc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */
|
||||
#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* The form of an alarm callback */
|
||||
|
||||
typedef CODE void (*alarmcb_t)(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_rtc_getdatetime_with_subseconds
|
||||
*
|
||||
* Description:
|
||||
* Get the current date and time from the date/time RTC. This interface
|
||||
* is only supported by the date/time RTC hardware implementation.
|
||||
* It is used to replace the system timer. It is only used by the RTOS
|
||||
* during initialization to set up the system time when CONFIG_RTC and
|
||||
* CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not).
|
||||
*
|
||||
* NOTE: Some date/time RTC hardware is capability of sub-second accuracy.
|
||||
* That sub-second accuracy is returned through 'nsec'.
|
||||
*
|
||||
* Input Parameters:
|
||||
* tp - The location to return the high resolution time value.
|
||||
* nsec - The location to return the subsecond time value.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
|
||||
int stm32l4_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_rtc_setdatetime
|
||||
*
|
||||
* Description:
|
||||
* Set the RTC to the provided time. RTC implementations which provide
|
||||
* up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide
|
||||
* this function.
|
||||
*
|
||||
* Input Parameters:
|
||||
* tp - the time to use
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_RTC_DATETIME
|
||||
struct tm;
|
||||
int stm32l4_rtc_setdatetime(FAR const struct tm *tp);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_rtc_setalarm
|
||||
*
|
||||
* Description:
|
||||
* Set up an alarm.
|
||||
*
|
||||
* Input Parameters:
|
||||
* tp - the time to set the alarm
|
||||
* callback - the function to call when the alarm expires.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_RTC_ALARM
|
||||
struct timespec;
|
||||
int stm32l4_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_rtc_cancelalarm
|
||||
*
|
||||
* Description:
|
||||
* Cancel a pending alarm alarm
|
||||
*
|
||||
* Input Parameters:
|
||||
* none
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_RTC_ALARM
|
||||
int stm32l4_rtc_cancelalarm(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_rtc_lowerhalf
|
||||
*
|
||||
* Description:
|
||||
* Instantiate the RTC lower half driver for the STM32L4. General usage:
|
||||
*
|
||||
* #include <nuttx/timers/rtc.h>
|
||||
* #include "stm32l4_rtc.h>
|
||||
*
|
||||
* struct rtc_lowerhalf_s *lower;
|
||||
* lower = stm32l4_rtc_lowerhalf();
|
||||
* rtc_initialize(0, lower);
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* On success, a non-NULL RTC lower interface is returned. NULL is
|
||||
* returned on any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_RTC_DRIVER
|
||||
struct rtc_lowerhalf_s;
|
||||
FAR struct rtc_lowerhalf_s *stm32l4_rtc_lowerhalf(void);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_RTC_H */
|
||||
225
arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c
Normal file
225
arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c
Normal file
@ -0,0 +1,225 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* dev@ziggurat29.com (adaptations for stm32l4)
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/timers/rtc.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32l4_rtc.h"
|
||||
|
||||
#ifdef CONFIG_RTC_DRIVER
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
/* This is the private type for the RTC state. It must be cast compatible
|
||||
* with struct rtc_lowerhalf_s.
|
||||
*/
|
||||
|
||||
struct stm32l4_lowerhalf_s
|
||||
{
|
||||
/* This is the contained reference to the read-only, lower-half
|
||||
* operations vtable (which may lie in FLASH or ROM)
|
||||
*/
|
||||
|
||||
FAR const struct rtc_ops_s *ops;
|
||||
|
||||
/* Data following is private to this driver and not visible outside of
|
||||
* this file.
|
||||
*/
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
/* Prototypes for static methods in struct rtc_ops_s */
|
||||
|
||||
static int stm32l4_rdtime(FAR struct rtc_lowerhalf_s *lower,
|
||||
FAR struct rtc_time *rtctime);
|
||||
static int stm32l4_settime(FAR struct rtc_lowerhalf_s *lower,
|
||||
FAR const struct rtc_time *rtctime);
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
/* STM32 RTC driver operations */
|
||||
|
||||
static const struct rtc_ops_s g_rtc_ops =
|
||||
{
|
||||
.rdtime = stm32l4_rdtime,
|
||||
.settime = stm32l4_settime,
|
||||
#ifdef CONFIG_RTC_ALARM
|
||||
.almread = NULL,
|
||||
.almset = NULL,
|
||||
#endif
|
||||
#ifdef CONFIG_RTC_PERIODIC
|
||||
.irqpread = NULL,
|
||||
.irqpset = NULL,
|
||||
#endif
|
||||
#ifdef CONFIG_RTC_ALARM
|
||||
.aie = NULL,
|
||||
#endif
|
||||
#ifdef CONFIG_RTC_ONESEC
|
||||
.uie = NULL,
|
||||
#endif
|
||||
#ifdef CONFIG_RTC_PERIODIC
|
||||
.pie = NULL,
|
||||
#endif
|
||||
#ifdef CONFIG_RTC_EPOCHYEAR
|
||||
.rdepoch = NULL,
|
||||
.setepoch = NULL,
|
||||
#endif
|
||||
#ifdef CONFIG_RTC_ALARM
|
||||
.rdwkalm = NULL,
|
||||
.setwkalm = NULL,
|
||||
#endif
|
||||
#ifdef CONFIG_RTC_IOCTL
|
||||
.ioctl = NULL,
|
||||
#endif
|
||||
#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
|
||||
.destroy = NULL,
|
||||
#endif
|
||||
};
|
||||
|
||||
/* STM32L4 RTC device state */
|
||||
|
||||
static struct stm32l4_lowerhalf_s g_rtc_lowerhalf =
|
||||
{
|
||||
.ops = &g_rtc_ops,
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_rdtime
|
||||
*
|
||||
* Description:
|
||||
* Implements the rdtime() method of the RTC driver interface
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A reference to RTC lower half driver state structure
|
||||
* rcttime - The location in which to return the current RTC time.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success; a negated errno value is returned
|
||||
* on any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int stm32l4_rdtime(FAR struct rtc_lowerhalf_s *lower,
|
||||
FAR struct rtc_time *rtctime)
|
||||
{
|
||||
/* This operation depends on the fact that struct rtc_time is cast
|
||||
* compatible with struct tm.
|
||||
*/
|
||||
|
||||
return up_rtc_getdatetime((FAR struct tm *)rtctime);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_settime
|
||||
*
|
||||
* Description:
|
||||
* Implements the settime() method of the RTC driver interface
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A reference to RTC lower half driver state structure
|
||||
* rcttime - The new time to set
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success; a negated errno value is returned
|
||||
* on any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int stm32l4_settime(FAR struct rtc_lowerhalf_s *lower,
|
||||
FAR const struct rtc_time *rtctime)
|
||||
{
|
||||
/* This operation depends on the fact that struct rtc_time is cast
|
||||
* compatible with struct tm.
|
||||
*/
|
||||
|
||||
return stm32l4_rtc_setdatetime((FAR const struct tm *)rtctime);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_rtc_lowerhalf
|
||||
*
|
||||
* Description:
|
||||
* Instantiate the RTC lower half driver for the STM32. General usage:
|
||||
*
|
||||
* #include <nuttx/timers/rtc.h>
|
||||
* #include "stm32l4_rtc.h>
|
||||
*
|
||||
* struct rtc_lowerhalf_s *lower;
|
||||
* lower = stm32l4_rtc_lowerhalf();
|
||||
* rtc_initialize(0, lower);
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* On success, a non-NULL RTC lower interface is returned. NULL is
|
||||
* returned on any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct rtc_lowerhalf_s *stm32l4_rtc_lowerhalf(void)
|
||||
{
|
||||
return (FAR struct rtc_lowerhalf_s *)&g_rtc_lowerhalf;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_RTC_DRIVER */
|
||||
1073
arch/arm/src/stm32l4/stm32l4_rtcc.c
Normal file
1073
arch/arm/src/stm32l4/stm32l4_rtcc.c
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user