From 60232190781b715838ae51a6af6144e4ffb3a2b8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 7 Oct 2014 15:05:30 -0600 Subject: [PATCH] Integrates OTGHS support into the STM32; Eliminates the older OTGHS in FS mode logic. From Brennan Ashton --- arch/arm/src/stm32/Kconfig | 62 ++++++++++++---- arch/arm/src/stm32/Make.defs | 7 +- arch/arm/src/stm32/chip/stm32_otgfs.h | 7 -- arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h | 4 + arch/arm/src/stm32/stm32_otgfs.h | 2 +- arch/arm/src/stm32/stm32_otgfsdev.c | 21 +----- arch/arm/src/stm32/stm32_otgfshost.c | 15 +--- arch/arm/src/stm32/stm32_usbhost.c | 62 ++++++++++++++++ arch/arm/src/stm32/stm32_usbhost.h | 78 +++++++++++++++++++- arch/arm/src/stm32/stm32f40xxx_rcc.c | 4 - 10 files changed, 194 insertions(+), 68 deletions(-) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 7f2888763f..4dcdc0a5a0 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -1161,19 +1161,6 @@ config STM32_OTGHS default n depends on STM32_STM32F207 || STM32_STM32F40XX || STM32_STM32F429 -config STM32_OTGHS_FS_MODE - bool "Use OTG HS in FS mode" - default n - depends on STM32_OTGHS && !STM32_OTGFS - select STM32_OTGFS2 - ---help--- - The STM32 USB HS module can operate in legacy FS mode using the - built-in FS PHY in the HS module. This mode can only be used if - the OTG FS block is not being used since they use on the same - driver, and all the base address are different (the driver - uses #define defined addresses which are re-mapped when this - option is selected). - config STM32_PWR bool "PWR" default n @@ -3370,7 +3357,7 @@ config STM32_ETHMAC_REGDEBUG endmenu endif -menu "USB Host Configuration" +menu "USB FS Host Configuration" config STM32_OTGFS_RXFIFO_SIZE int "Rx Packet Size" @@ -3407,17 +3394,60 @@ config STM32_OTGFS_SOFINTR ---help--- Enable SOF interrupts. Why would you ever want to do that? +endmenu + +menu "USB HS Host Configuration" + +config STM32_OTGHS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + depends on USBHOST && STM32_OTGHS + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGHS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + depends on USBHOST && STM32_OTGHS + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + depends on USBHOST && STM32_OTGHS + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_DESCSIZE + int "Descriptor Size" + default 128 + depends on USBHOST && STM32_OTGHS + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGHS_SOFINTR + bool "Enable SOF interrupts" + default n + depends on USBHOST && STM32_OTGHS + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +endmenu + +menu "USB Host Debug Configuration" + config STM32_USBHOST_REGDEBUG bool "Register-Level Debug" default n - depends on USBHOST && STM32_OTGFS + depends on USBHOST && (STM32_OTGFS || STM32_OTGHS) ---help--- Enable very low-level register access debug. Depends on DEBUG. config STM32_USBHOST_PKTDUMP bool "Packet Dump Debug" default n - depends on USBHOST && STM32_OTGFS + depends on USBHOST && (STM32_OTGFS || STM32_OTGHS) ---help--- Dump all incoming and outgoing USB packets. Depends on DEBUG. diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 2cbf01cc90..f02a9d5195 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -130,17 +130,14 @@ endif ifeq ($(CONFIG_STM32_OTGFS),y) CHIP_CSRCS += stm32_otgfsdev.c endif -ifeq ($(CONFIG_STM32_OTGFS2),y) -CHIP_CSRCS += stm32_otgfsdev.c -endif endif ifeq ($(CONFIG_USBHOST),y) ifeq ($(CONFIG_STM32_OTGFS),y) CHIP_CSRCS += stm32_otgfshost.c endif -ifeq ($(CONFIG_STM32_OTGFS2),y) -CHIP_CSRCS += stm32_otgfshost.c +ifeq ($(CONFIG_STM32_OTGHS),y) +CHIP_CSRCS += stm32_otghshost.c endif endif diff --git a/arch/arm/src/stm32/chip/stm32_otgfs.h b/arch/arm/src/stm32/chip/stm32_otgfs.h index d389897060..f86552014d 100644 --- a/arch/arm/src/stm32/chip/stm32_otgfs.h +++ b/arch/arm/src/stm32/chip/stm32_otgfs.h @@ -59,13 +59,6 @@ #define OTGFS_PID_MDATA (3) /* Non-control */ #define OTGFS_PID_SETUP (3) /* Control */ -/* If OTGFS2 is defined (FS mode of the HS module), then remap the OTGFS base address */ - -#ifdef CONFIG_STM32_OTGFS2 -# undef STM32_OTGFS_BASE -# define STM32_OTGFS_BASE STM32_OTGHS_BASE -#endif - /* Register Offsets *********************************************************************************/ /* Core global control and status registers */ diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h index 47a731dc18..79c9789a21 100644 --- a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h @@ -396,6 +396,10 @@ #define GPIO_OTGFS_SDA (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN9) #define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_OTGHSFS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_OTGHSFS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_OTGHSFS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12) + #ifdef CONFIG_STM32_OTGFS2 # define GPIO_OTGFS2_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) # define GPIO_OTGFS2_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) diff --git a/arch/arm/src/stm32/stm32_otgfs.h b/arch/arm/src/stm32/stm32_otgfs.h index 658fe67a13..79258168fc 100644 --- a/arch/arm/src/stm32/stm32_otgfs.h +++ b/arch/arm/src/stm32/stm32_otgfs.h @@ -47,7 +47,7 @@ #include "stm32.h" #include "chip/stm32_otgfs.h" -#if defined(CONFIG_STM32_OTGFS) || defined (CONFIG_STM32_OTGFS2) +#if defined(CONFIG_STM32_OTGFS) /************************************************************************************ * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c index 3acd5ced4a..051cf5510f 100644 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/arch/arm/src/stm32/stm32_otgfsdev.c @@ -62,7 +62,7 @@ #include "stm32_otgfs.h" -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGFS2)) +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS)) /******************************************************************************* * Definitions @@ -276,13 +276,6 @@ # define MAX(a,b) ((a) > (b) ? (a) : (b)) #endif -/* For OTGFS2 mode (FS mode of HS module), remap the IRQ number *****************/ - -#ifdef CONFIG_STM32_OTGFS2 -# undef STM32_IRQ_OTGFS -# define STM32_IRQ_OTGFS STM32_IRQ_OTGHS -#endif - /******************************************************************************* * Private Types *******************************************************************************/ @@ -5143,12 +5136,6 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) * mode prior to issuing a soft reset. */ -#ifdef CONFIG_STM32_OTGFS2 - regval = stm32_getreg(STM32_OTGFS_GUSBCFG); - regval |= OTGFS_GUSBCFG_PHYSEL; - stm32_putreg(regval, STM32_OTGFS_GUSBCFG); -#endif - /* Common USB OTG core initialization */ /* Reset after a PHY select and set Host mode. First, wait for AHB master * IDLE state. @@ -5406,15 +5393,9 @@ void up_usbinitialize(void) * *Pins may vary from device-to-device. */ -#ifdef CONFIG_STM32_OTGFS2 - stm32_configgpio(GPIO_OTGFS2_DM); - stm32_configgpio(GPIO_OTGFS2_DP); - stm32_configgpio(GPIO_OTGFS2_ID); /* Only needed for OTG */ -#else stm32_configgpio(GPIO_OTGFS_DM); stm32_configgpio(GPIO_OTGFS_DP); stm32_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ -#endif /* SOF output pin configuration is configurable. */ diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c index 86934beabf..1d700c5ad0 100644 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ b/arch/arm/src/stm32/stm32_otgfshost.c @@ -66,7 +66,7 @@ #include "stm32_usbhost.h" -#if defined(CONFIG_USBHOST) && (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGFS2)) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS) /******************************************************************************* * Pre-processor Definitions @@ -164,13 +164,6 @@ # define MAX(a, b) (((a) > (b)) ? (a) : (b)) #endif -/* For OTGFS2 mode (FS mode of HS module), remap the IRQ number *****************/ - -#ifdef CONFIG_STM32_OTGFS2 -# undef STM32_IRQ_OTGFS -# define STM32_IRQ_OTGFS STM32_IRQ_OTGHS -#endif - /******************************************************************************* * Private Types *******************************************************************************/ @@ -4399,15 +4392,9 @@ FAR struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) * *Pins may vary from device-to-device. */ -#ifdef CONFIG_STM32_OTGFS2 - stm32_configgpio(GPIO_OTGFS2_DM); - stm32_configgpio(GPIO_OTGFS2_DP); - stm32_configgpio(GPIO_OTGFS2_ID); /* Only needed for OTG */ -#else stm32_configgpio(GPIO_OTGFS_DM); stm32_configgpio(GPIO_OTGFS_DP); stm32_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ -#endif /* SOF output pin configuration is configurable */ diff --git a/arch/arm/src/stm32/stm32_usbhost.c b/arch/arm/src/stm32/stm32_usbhost.c index 74782e6b9d..cfd33c1d9a 100755 --- a/arch/arm/src/stm32/stm32_usbhost.c +++ b/arch/arm/src/stm32/stm32_usbhost.c @@ -113,6 +113,39 @@ static const struct stm32_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = # endif #endif +#ifdef CONFIG_STM32_OTGHS + + TRENTRY(OTGHS_TRACE1_DEVDISCONN, TR_FMT1, "OTGHS ERROR: Host Port %d. Device disconnected\n"), + TRENTRY(OTGHS_TRACE1_IRQATTACH, TR_FMT1, "OTGHS ERROR: Failed to attach IRQ\n"), + TRENTRY(OTGHS_TRACE1_TRNSFRFAILED, TR_FMT1, "OTGHS ERROR: Transfer Failed. ret=%d\n"), + TRENTRY(OTGHS_TRACE1_SENDSETUP, TR_FMT1, "OTGHS ERROR: ctrl_sendsetup() failed with: %d\n"), + TRENTRY(OTGHS_TRACE1_SENDDATA, TR_FMT1, "OTGHS ERROR: ctrl_senddata() failed with: %d\n"), + TRENTRY(OTGHS_TRACE1_RECVDATA, TR_FMT1, "OTGHS ERROR: ctrl_recvdata() failed with: %d\n"), + +# ifdef HAVE_USBHOST_TRACE_VERBOSE + + TRENTRY(OTGHS_VTRACE1_CONNECTED, TR_FMT1, "OTGHS Host Port %d connected.\n"), + TRENTRY(OTGHS_VTRACE1_DISCONNECTED, TR_FMT1, "OTGHS Host Port %d disconnected.\n"), + TRENTRY(OTGHS_VTRACE1_GINT, TR_FMT1, "OTGHS Handling Interrupt. Entry Point.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_SOF, TR_FMT1, "OTGHS Handle the start of frame interrupt.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_RXFLVL, TR_FMT1, "OTGHS Handle the RxFIFO non-empty interrupt.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_NPTXFE, TR_FMT1, "OTGHS Handle the non-periodic TxFIFO empty interrupt.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_PTXFE, TR_FMT1, "OTGHS Handle the periodic TxFIFO empty interrupt.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HC, TR_FMT1, "OTGHS Handle the host channels interrupt.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT, TR_FMT1, "OTGHS Handle the host port interrupt.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT_POCCHNG, TR_FMT1, "OTGHS HPRT: Port Over-Current Change.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT_PCDET, TR_FMT1, "OTGHS HPRT: Port Connect Detect.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT_PENCHNG, TR_FMT1, "OTGHS HPRT: Port Enable Changed.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT_LSDEV, TR_FMT1, "OTGHS HPRT: Low Speed Device Connected.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT_HSDEV, TR_FMT1, "OTGHS HPRT: Full Speed Device Connected.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT_LSHSSW, TR_FMT1, "OTGHS HPRT: Host Switch: LS -> HS.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT_HSLSSW, TR_FMT1, "OTGHS HPRT: Host Switch: HS -> LS.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_DISC, TR_FMT1, "OTGHS Handle the disconnect detected interrupt.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_IPXFR, TR_FMT1, "OTGHS Handle the incomplete periodic transfer.\n"), + +# endif +#endif + }; static const struct stm32_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = @@ -144,6 +177,35 @@ static const struct stm32_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_OUT, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,OUT,ISOC)\n"), TRENTRY(OTGFS_VTRACE2_CHANHALT, TR_FMT2, "OTGFS Channel halted. chidx: %d, reason: %d\n"), +# endif +#endif +#ifdef CONFIG_STM32_OTGHS + + TRENTRY(OTGHS_TRACE2_CLIP, TR_FMT2, "OTGHS CLIP: chidx: %d buflen: %d\n"), + +# ifdef HAVE_USBHOST_TRACE_VERBOSE + + TRENTRY(OTGHS_VTRACE2_CHANWAKEUP_IN, TR_FMT2, "OTGHS EP%d(IN) wake up with result: %d\n"), + TRENTRY(OTGHS_VTRACE2_CHANWAKEUP_OUT, TR_FMT2, "OTGHS EP%d(OUT) wake up with result: %d\n"), + TRENTRY(OTGHS_VTRACE2_CTRLIN, TR_FMT2, "OTGHS CTRL_IN type: %02x req: %02x\n"), + TRENTRY(OTGHS_VTRACE2_CTRLOUT, TR_FMT2, "OTGHS CTRL_OUT type: %02x req: %02x\n"), + TRENTRY(OTGHS_VTRACE2_INTRIN, TR_FMT2, "OTGHS INTR_IN chidx: %02x len: %02x\n"), + TRENTRY(OTGHS_VTRACE2_INTROUT, TR_FMT2, "OTGHS INTR_OUT chidx: %02x len: %02x\n"), + TRENTRY(OTGHS_VTRACE2_BULKIN, TR_FMT2, "OTGHS BULK_IN chidx: %02x len: %02x\n"), + TRENTRY(OTGHS_VTRACE2_BULKOUT, TR_FMT2, "OTGHS BULK_OUT chidx: %02x len: %02x\n"), + TRENTRY(OTGHS_VTRACE2_ISOCIN, TR_FMT2, "OTGHS ISOC_IN chidx: %02x len: %04d\n"), + TRENTRY(OTGHS_VTRACE2_ISOCOUT, TR_FMT2, "OTGHS ISOC_OUT chidx: %02x req: %02x\n"), + TRENTRY(OTGHS_VTRACE2_STARTTRANSFER, TR_FMT2, "OTGHS Transfer chidx: %d buflen: %d\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_CTRL_IN, TR_FMT2, "OTGHS Channel configured. chidx: %d: (EP%d,IN ,CTRL)\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_CTRL_OUT, TR_FMT2, "OTGHS Channel configured. chidx: %d: (EP%d,OUT,CTRL)\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_INTR_IN, TR_FMT2, "OTGHS Channel configured. chidx: %d: (EP%d,IN ,INTR)\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_INTR_OUT, TR_FMT2, "OTGHS Channel configured. chidx: %d: (EP%d,OUT,INTR)\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_BULK_IN, TR_FMT2, "OTGHS Channel configured. chidx: %d: (EP%d,IN ,BULK)\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_BULK_OUT, TR_FMT2, "OTGHS Channel configured. chidx: %d: (EP%d,OUT,BULK)\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_ISOC_IN, TR_FMT2, "OTGHS Channel configured. chidx: %d: (EP%d,IN ,ISOC)\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_ISOC_OUT, TR_FMT2, "OTGHS Channel configured. chidx: %d: (EP%d,OUT,ISOC)\n"), + TRENTRY(OTGHS_VTRACE2_CHANHALT, TR_FMT2, "OTGHS Channel halted. chidx: %d, reason: %d\n"), + # endif #endif }; diff --git a/arch/arm/src/stm32/stm32_usbhost.h b/arch/arm/src/stm32/stm32_usbhost.h index 0b28c6920a..ff3ee23455 100644 --- a/arch/arm/src/stm32/stm32_usbhost.h +++ b/arch/arm/src/stm32/stm32_usbhost.h @@ -47,8 +47,9 @@ #include "chip.h" #include "chip/stm32_otgfs.h" +#include "chip/stm32_otghs.h" -#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) +#if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS)) && defined(CONFIG_USBHOST) #ifdef HAVE_USBHOST_TRACE enum usbhost_trace1codes_e @@ -85,6 +86,39 @@ enum usbhost_trace1codes_e OTGFS_VTRACE1_GINT_DISC, /* OTGFS Handle the disconnect detected interrupt */ OTGFS_VTRACE1_GINT_IPXFR, /* OTGFS Handle the incomplete periodic transfer */ +# endif +#endif + +#ifdef CONFIG_STM32_OTGHS + + OTGHS_TRACE1_DEVDISCONN, /* OTGHS ERROR: Host Port Device disconnected */ + OTGHS_TRACE1_IRQATTACH, /* OTGHS ERROR: Failed to attach IRQ */ + OTGHS_TRACE1_TRNSFRFAILED, /* OTGHS ERROR: Host Port Transfer Failed */ + OTGHS_TRACE1_SENDSETUP, /* OTGHS ERROR: sendsetup() failed with: */ + OTGHS_TRACE1_SENDDATA, /* OTGHS ERROR: senddata() failed with: */ + OTGHS_TRACE1_RECVDATA, /* OTGHS ERROR: recvdata() failed with: */ + +# ifdef HAVE_USBHOST_TRACE_VERBOSE + + OTGHS_VTRACE1_CONNECTED, /* OTGHS Host Port connected */ + OTGHS_VTRACE1_DISCONNECTED, /* OTGHS Host Port disconnected */ + OTGHS_VTRACE1_GINT, /* OTGHS Handling Interrupt. Entry Point */ + OTGHS_VTRACE1_GINT_SOF, /* OTGHS Handle the start of frame interrupt */ + OTGHS_VTRACE1_GINT_RXFLVL, /* OTGHS Handle the RxFIFO non-empty interrupt */ + OTGHS_VTRACE1_GINT_NPTXFE, /* OTGHS Handle the non-periodic TxFIFO empty interrupt */ + OTGHS_VTRACE1_GINT_PTXFE, /* OTGHS Handle the periodic TxFIFO empty interrupt */ + OTGHS_VTRACE1_GINT_HC, /* OTGHS Handle the host channels interrupt */ + OTGHS_VTRACE1_GINT_HPRT, /* OTGHS Handle the host port interrupt */ + OTGHS_VTRACE1_GINT_HPRT_POCCHNG, /* OTGHS HPRT: Port Over-Current Change*/ + OTGHS_VTRACE1_GINT_HPRT_PCDET, /* OTGHS HPRT: Port Connect Detect */ + OTGHS_VTRACE1_GINT_HPRT_PENCHNG, /* OTGHS HPRT: Port Enable Changed */ + OTGHS_VTRACE1_GINT_HPRT_LSDEV, /* OTGHS HPRT: Low Speed Device Connected */ + OTGHS_VTRACE1_GINT_HPRT_FSDEV, /* OTGHS HPRT: Full Speed Device Connected */ + OTGHS_VTRACE1_GINT_HPRT_LSFSSW, /* OTGHS HPRT: Host Switch: LS -> FS */ + OTGHS_VTRACE1_GINT_HPRT_FSLSSW, /* OTGHS HPRT: Host Switch: FS -> LS */ + OTGHS_VTRACE1_GINT_DISC, /* OTGHS Handle the disconnect detected interrupt */ + OTGHS_VTRACE1_GINT_IPXFR, /* OTGHS Handle the incomplete periodic transfer */ + # endif #endif @@ -117,6 +151,36 @@ enum usbhost_trace1codes_e OTGFS_VTRACE2_CHANCONF_ISOC_OUT, OTGFS_VTRACE2_CHANHALT, /* Channel halted. chidx: , reason: */ +# endif +#endif + +#ifdef CONFIG_STM32_OTGHS + + OTGHS_TRACE2_CLIP, /* OTGHS CLIP: chidx: buflen: */ + +# ifdef HAVE_USBHOST_TRACE_VERBOSE + + OTGHS_VTRACE2_CHANWAKEUP_IN, /* OTGHS IN Channel wake up with result */ + OTGHS_VTRACE2_CHANWAKEUP_OUT, /* OTGHS OUT Channel wake up with result */ + OTGHS_VTRACE2_CTRLIN, /* OTGHS CTRLIN */ + OTGHS_VTRACE2_CTRLOUT, /* OTGHS CTRLOUT */ + OTGHS_VTRACE2_INTRIN, /* OTGHS INTRIN */ + OTGHS_VTRACE2_INTROUT, /* OTGHS INTROUT */ + OTGHS_VTRACE2_BULKIN, /* OTGHS BULKIN */ + OTGHS_VTRACE2_BULKOUT, /* OTGHS BULKOUT */ + OTGHS_VTRACE2_ISOCIN, /* OTGHS ISOCIN */ + OTGHS_VTRACE2_ISOCOUT, /* OTGHS ISOCOUT */ + OTGHS_VTRACE2_STARTTRANSFER, /* OTGHS EP buflen */ + OTGHS_VTRACE2_CHANCONF_CTRL_IN, + OTGHS_VTRACE2_CHANCONF_CTRL_OUT, + OTGHS_VTRACE2_CHANCONF_INTR_IN, + OTGHS_VTRACE2_CHANCONF_INTR_OUT, + OTGHS_VTRACE2_CHANCONF_BULK_IN, + OTGHS_VTRACE2_CHANCONF_BULK_OUT, + OTGHS_VTRACE2_CHANCONF_ISOC_IN, + OTGHS_VTRACE2_CHANCONF_ISOC_OUT, + OTGHS_VTRACE2_CHANHALT, /* Channel halted. chidx: , reason: */ + # endif #endif @@ -143,6 +207,8 @@ enum usbhost_trace1codes_e * * CONFIG_USBHOST - Enable general USB host support * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * or + * CONFIG_STM32_OTGHS - Enable the STM32 USB OTG HS block * CONFIG_STM32_SYSCFG - Needed * * Options: @@ -155,6 +221,16 @@ enum usbhost_trace1codes_e * words. Default 96 (384 bytes) * CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? + * + * CONFIG_STM32_OTGHS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * Default 128 (512 bytes) + * CONFIG_STM32_OTGHS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * in 32-bit words. Default 96 (384 bytes) + * CONFIG_STM32_OTGHS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * words. Default 96 (384 bytes) + * CONFIG_STM32_OTGHS_SOFINTR - Enable SOF interrupts. Why would you ever + * want to do that? + * * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG. */ diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c index 9bb6e99e8f..0f8847f101 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -201,11 +201,7 @@ static inline void rcc_enableahb1(void) #ifdef CONFIG_STM32_OTGHS /* USB OTG HS */ -#ifdef CONFIG_STM32_OTGFS2 regval |= RCC_AHB1ENR_OTGHSEN; -#else - regval |= RCC_AHB1ENR_OTGHSULPIEN; -#endif #endif /* CONFIG_STM32_OTGHS */