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XMC4xxx: Fix a pin configuration problem. Fix some mispellings.

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This commit is contained in:
Gregory Nutt 2017-03-21 11:24:04 -06:00
parent 21a626878a
commit 602bdd13fb
5 changed files with 25 additions and 25 deletions
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22
arch/arm/src/xmc4/chip/xmc4_ports.h
View File

@ -79,7 +79,7 @@
#define XMC4_PORT_IN_OFFSET 0x0024 /* Port Input Register */
#define XMC4_PORT_PDR_OFFSET(n) (0x0010 + (((n) >> 1) & ~3))
#define XMC4_PORT_PDR_OFFSET(n) (0x0040 + (((n) >> 1) & ~3))
#define XMC4_PORT_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */
#define XMC4_PORT_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */
@ -399,19 +399,19 @@
#define PORT_PDR0_PD2_SHIFT (8) /* Bit 8-10: Pad Driver Mode for Port n Pin 2 */
#define PORT_PDR0_PD2_MASK (7 << PORT_PDR0_PD2_SHIFT)
# define PORT_PDR0_PD2(n) ((uint32_t)(n) << PORT_PDR0_PD2_SHIFT)
#define PORT_PDR0_PD3_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port 0 Pin 3 */
#define PORT_PDR0_PD3_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port n Pin 3 */
#define PORT_PDR0_PD3_MASK (7 << PORT_PDR0_PD3_SHIFT)
# define PORT_PDR0_PD3(n) ((uint32_t)(n) << PORT_PDR0_PD3_SHIFT)
#define PORT_PDR0_PD4_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port 0 Pin 4 */
#define PORT_PDR0_PD4_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port n Pin 4 */
#define PORT_PDR0_PD4_MASK (7 << PORT_PDR0_PD4_SHIFT)
# define PORT_PDR0_PD4(n) ((uint32_t)(n) << PORT_PDR0_PD4_SHIFT)
#define PORT_PDR0_PD5_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port 0 Pin 5 */
#define PORT_PDR0_PD5_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port n Pin 5 */
#define PORT_PDR0_PD5_MASK (7 << PORT_PDR0_PD5_SHIFT)
# define PORT_PDR0_PD5(n) ((uint32_t)(n) << PORT_PDR0_PD5_SHIFT)
#define PORT_PDR0_PD6_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port 0 Pin 6 */
#define PORT_PDR0_PD6_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port n Pin 6 */
#define PORT_PDR0_PD6_MASK (7 << PORT_PDR0_PD6_SHIFT)
# define PORT_PDR0_PD6(n) ((uint32_t)(n) << PORT_PDR0_PD6_SHIFT)
#define PORT_PDR0_PD7_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port 0 Pin 7 */
#define PORT_PDR0_PD7_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port n Pin 7 */
#define PORT_PDR0_PD7_MASK (7 << PORT_PDR0_PD7_SHIFT)
# define PORT_PDR0_PD7(n) ((uint32_t)(n) << PORT_PDR0_PD7_SHIFT)
@ -429,19 +429,19 @@
#define PORT_PDR1_PD10_SHIFT (8) /* Bit 8-10: Pad Driver Mode for Port n Pin 10 */
#define PORT_PDR1_PD10_MASK (7 << PORT_PDR1_PD10_SHIFT)
# define PORT_PDR1_PD10(n) ((uint32_t)(n) << PORT_PDR1_PD10_SHIFT)
#define PORT_PDR1_PD11_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port 0 Pin 11 */
#define PORT_PDR1_PD11_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port n Pin 11 */
#define PORT_PDR1_PD11_MASK (7 << PORT_PDR1_PD11_SHIFT)
# define PORT_PDR1_PD11(n) ((uint32_t)(n) << PORT_PDR1_PD11_SHIFT)
#define PORT_PDR1_PD12_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port 0 Pin 12 */
#define PORT_PDR1_PD12_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port n Pin 12 */
#define PORT_PDR1_PD12_MASK (7 << PORT_PDR1_PD12_SHIFT)
# define PORT_PDR1_PD12(n) ((uint32_t)(n) << PORT_PDR1_PD12_SHIFT)
#define PORT_PDR1_PD13_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port 0 Pin 13 */
#define PORT_PDR1_PD13_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port n Pin 13 */
#define PORT_PDR1_PD13_MASK (7 << PORT_PDR1_PD13_SHIFT)
# define PORT_PDR1_PD13(n) ((uint32_t)(n) << PORT_PDR1_PD13_SHIFT)
#define PORT_PDR1_PD14_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port 0 Pin 14 */
#define PORT_PDR1_PD14_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port n Pin 14 */
#define PORT_PDR1_PD14_MASK (7 << PORT_PDR1_PD14_SHIFT)
# define PORT_PDR1_PD14(n) ((uint32_t)(n) << PORT_PDR1_PD14_SHIFT)
#define PORT_PDR1_PD15_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port 0 Pin 15 */
#define PORT_PDR1_PD15_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port n Pin 15 */
#define PORT_PDR1_PD15_MASK (7 << PORT_PDR1_PD15_SHIFT)
# define PORT_PDR1_PD15(n) ((uint32_t)(n) << PORT_PDR1_PD15_SHIFT)

18
arch/arm/src/xmc4/xmc4_gpio.c
View File

@ -247,7 +247,7 @@ static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin,
*
* Disable = set
* Analog = set
* Enable = clear
* Enable = clear
*/
mask = PORT_PIN(pin);
@ -272,7 +272,7 @@ static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin,
****************************************************************************/
static inline void xmc4_gpio_pps(uintptr_t portbase, unsigned int pin,
bool value)
bool powersave)
{
uint32_t regval;
uint32_t mask;
@ -281,10 +281,10 @@ static inline void xmc4_gpio_pps(uintptr_t portbase, unsigned int pin,
regval = xmc4_gpio_getreg(portbase, XMC4_PORT_PPS_OFFSET);
/* Set/clear the enable/disable (or analg) value for this field */
/* Set/clear the enable/disable power save value for this field */
mask = PORT_PIN(pin);
if (value)
if (powersave)
{
regval |= mask;
}
@ -312,7 +312,7 @@ static void xmc4_gpio_pdr(uintptr_t portbase, unsigned int pin,
unsigned int offset;
unsigned int shift;
/* Read the PDRregister */
/* Read the PDR register */
offset = XMC4_PORT_PDR_OFFSET(pin);
regval = xmc4_gpio_getreg(portbase, offset);
@ -417,18 +417,18 @@ int xmc4_gpio_config(gpioconfig_t pinconfig)
value = xmc4_gpio_pinctrl(pinconfig);
xmc4_gpio_hwsel(portbase, pin, value);
/* Select drive strength */
/* Select drive strength (PDR) */
value = xmc4_gpio_padtype(pinconfig);
xmc4_gpio_pdr(portbase, pin, value);
/* Enable/enable pad or Analog only (PDISC) */
xmc4_gpio_pdisc(portbase, pin, ((pinconfig & GPIO_PAD_DISABLE) != 0));
xmc4_gpio_pdisc(portbase, pin, ((pinconfig & GPIO_PAD_DISABLE) == 0));
/* Make sure pin is not in power save mode (PDR) */
/* Make sure pin is not in power save mode (PPS) */
xmc4_gpio_pdisc(portbase, pin, false);
xmc4_gpio_pps(portbase, pin, false);
leave_critical_section(flags);
return OK;

2
arch/arm/src/xmc4/xmc4_lowputc.c
View File

@ -275,7 +275,7 @@ int xmc4_uart_configure(enum usic_channel_e channel,
* the config structure.
*/
ret = xmc4_uisc_baudrate(channel, config->baud, UART_OVERSAMPLING);
ret = xmc4_usic_baudrate(channel, config->baud, UART_OVERSAMPLING);
/* Configure frame format.
*

4
arch/arm/src/xmc4/xmc4_usic.c
View File

@ -385,7 +385,7 @@ int xmc4_disable_usic_channel(enum usic_channel_e channel)
}
/****************************************************************************
* Name: xmc4_uisc_baudrate
* Name: xmc4_usic_baudrate
*
* Description:
* Set the USIC baudrate for the USIC channel
@ -396,7 +396,7 @@ int xmc4_disable_usic_channel(enum usic_channel_e channel)
*
****************************************************************************/
int xmc4_uisc_baudrate(enum usic_channel_e channel, uint32_t baud,
int xmc4_usic_baudrate(enum usic_channel_e channel, uint32_t baud,
uint32_t oversampling)
{
uintptr_t base;

4
arch/arm/src/xmc4/xmc4_usic.h
View File

@ -177,7 +177,7 @@ int xmc4_enable_usic_channel(enum usic_channel_e channel);
int xmc4_disable_usic_channel(enum usic_channel_e channel);
/****************************************************************************
* Name: xmc4_uisc_baudrate
* Name: xmc4_usic_baudrate
*
* Description:
* Set the USIC baudrate for the USIC channel
@ -188,7 +188,7 @@ int xmc4_disable_usic_channel(enum usic_channel_e channel);
*
****************************************************************************/
int xmc4_uisc_baudrate(enum usic_channel_e channel, uint32_t baud,
int xmc4_usic_baudrate(enum usic_channel_e channel, uint32_t baud,
uint32_t oversampling);
#endif /* __ARCH_ARM_SRC_XMC4_XMC4_USIC_H */