More PIC32 header files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3591 42af7a65-404d-4744-a932-0658087f49c3
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arch/mips/src/pic32mx/pic32mx-spi.h
Executable file
175
arch/mips/src/pic32mx/pic32mx-spi.h
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/****************************************************************************
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* arch/mips/src/pic32mx/pic32mx-spi.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_SPI_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_SPI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "pic32mx-memorymap.h"
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/****************************************************************************
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* Pre-Processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define PIC32MX_SPI_CON_OFFSET 0x0000 /* SPI control register */
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#define PIC32MX_SPI_CONCLR_OFFSET 0x0004 /* SPI control clear register */
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#define PIC32MX_SPI_CONSET_OFFSET 0x0008 /* SPI control set register */
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#define PIC32MX_SPI_CONINV_OFFSET 0x000c /* SPI control invert register */
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#define PIC32MX_SPI_STAT_OFFSET 0x0010 /* SPI status register */
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#define PIC32MX_SPI_STATSET_OFFSET 0x0018 /* SPI status set register */
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#define PIC32MX_SPI_BUF_OFFSET 0x0020 /* SPI buffer register */
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#define PIC32MX_SPI_BRG_OFFSET 0x0030 /* SPI baud rate register */
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#define PIC32MX_SPI_BRGCLR_OFFSET 0x0034 /* SPI baud rate clear register */
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#define PIC32MX_SPI_BRGSET_OFFSET 0x0038 /* SPI baud rate set register */
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#define PIC32MX_SPI_BRGINV_OFFSET 0x003c /* SPI baud rate invert register */
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/* Register Addresses *******************************************************/
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#define PIC32MX_SPI1_CON (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CON_OFFSET)
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#define PIC32MX_SPI1_CONCLR (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CONCLR_OFFSET)
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#define PIC32MX_SPI1_CONSET (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CONSET_OFFSET)
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#define PIC32MX_SPI1_CONINV (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CONINV_OFFSET)
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#define PIC32MX_SPI1_STAT (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_STAT_OFFSET)
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#define PIC32MX_SPI1_STATSET (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_STATSET_OFFSET)
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#define PIC32MX_SPI1_BUF (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BUF_OFFSET)
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#define PIC32MX_SPI1_BRG (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRG_OFFSET)
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#define PIC32MX_SPI1_BRGCLR (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGCLR_OFFSET)
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#define PIC32MX_SPI1_BRGSET (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGSET_OFFSET)
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#define PIC32MX_SPI1_BRGINV (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGINV_OFFSET)
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#define PIC32MX_SPI2_CON (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CON_OFFSET)
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#define PIC32MX_SPI2_CONCLR (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CONCLR_OFFSET)
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#define PIC32MX_SPI2_CONSET (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CONSET_OFFSET)
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#define PIC32MX_SPI2_CONINV (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CONINV_OFFSET)
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#define PIC32MX_SPI2_STAT (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_STAT_OFFSET)
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#define PIC32MX_SPI2_STATSET (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_STATSET_OFFSET)
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#define PIC32MX_SPI2_BUF (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BUF_OFFSET)
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#define PIC32MX_SPI2_BRG (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRG_OFFSET)
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#define PIC32MX_SPI2_BRGCLR (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGCLR_OFFSET)
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#define PIC32MX_SPI2_BRGSET (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGSET_OFFSET)
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#define PIC32MX_SPI2_BRGINV (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGINV_OFFSET)
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/* Register Bit-Field Definitions *******************************************/
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/* SPI control register */
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#define SPI_CON_MSTEN (1 << 5) /* Bits 5: Master mode enable */
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#define SPI_CON_CKP (1 << 6) /* Bits 6: Clock polarity select */
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#define SPI_CON_SSEN (1 << 7) /* Bits 7: Slave select enable (slave mode) */
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#define SPI_CON_CKE (1 << 8) /* Bits 8: SPI clock edge select */
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#define SPI_CON_SMP (1 << 9) /* Bits 9: SPI data input sample phase */
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#define SPI_CON_MODE_SHIFT (10) /* Bits 10-11: 32/16-Bit Communication Select */
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#define SPI_CON_MODE_MASK (3 << SPI_CON_MODE_SHIFT)
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#define SPI_CON_MODE32 (1 << 11) /* Bits 11: xx */
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# define SPI_CON_MODE_8BIT (0 << SPI_CON_MODE_SHIFT) /* 8-bit data width */
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# define SPI_CON_MODE_16BIT (1 << SPI_CON_MODE_SHIFT) /* 16-bit data width */
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# define SPI_CON_MODE_32BIT (2 << SPI_CON_MODE_SHIFT) /* 2-bit data width */
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#define SPI_CON_DISSDO (1 << 12) /* Bits 12: Disable SDOx pin */
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#define SPI_CON_SIDL (1 << 13) /* Bits 13: Stop in idle mode */
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#define SPI_CON_FRZ (1 << 14) /* Bits 14: Freeze in debug exception */
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#define SPI_CON_ON (1 << 15) /* Bits 15: SPI peripheral on */
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#define SPI_CON_ENHBUF (1 << 16) /* Bits 16: Enhanced buffer enable */
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#define SPI_CON_SPIFE (1 << 17) /* Bits 17: Frame sync pulse edge select */
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#define SPI_CON_FRMCNT_SHIFT (24) /* Bits 24-26: Frame Sync Pulse Counter bits */
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#define SPI_CON_FRMCNT_MASK (7 << SPI_CON_FRMCNT_SHIFT)
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# define SPI_CON_FRMCNT_CHAR1 (0 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse each char */
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# define SPI_CON_FRMCNT_CHAR2 (1 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 2 chars */
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# define SPI_CON_FRMCNT_CHAR4 (2 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 4 chars */
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# define SPI_CON_FRMCNT_CHAR8 (3 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 8 chars */
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# define SPI_CON_FRMCNT_CHAR16 (4 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 16 chars */
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# define SPI_CON_FRMCNT_CHAR32 (5 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 32 chars */
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#define SPI_CON_FRMSYPW (1 << 27) /* Bits 27: Frame sync pulse width */
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#define SPI_CON_MSSEN (1 << 28) /* Bits 28: Master mode slave select enable */
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#define SPI_CON_FRMPOL (1 << 29) /* Bits 29: Frame sync polarity */
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#define SPI_CON_FRMSYNC (1 << 30) /* Bits 30: Frame sync pulse direction control on SSx pin */
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#define SPI_CON_FRMEN (1 << 31) /* Bits 31: Framed SPI support */
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/* SPI status register */
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#define SPI_STAT_SPIRBF (1 << 0) /* Bits 0: SPI receive buffer full status */
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#define SPI_STAT_SPITBF (1 << 1) /* Bits 1: SPI transmit buffer full status */
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#define SPI_STAT_SPITBE (1 << 3) /* Bits 3: SPI transmit buffer empty status */
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#define SPI_STAT_SPIRBE (1 << 5) /* Bits 5: RX FIFO Empty */
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#define SPI_STAT_SPIROV (1 << 6) /* Bits 6: Receive overflow flag */
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#define SPI_STAT_SRMT (1 << 7) /* Bits 6: Shift Register Empty */
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#define SPI_STAT_SPITUR (1 << 6) /* Bits 8: Transmit under run */
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#define SPI_STAT_SPIBUSY (1 << 11) /* Bits 11: SPI activity status */
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#define SPI_STAT_TXBUFELM_SHIFT (16) /* Bits 16-20: Transmit Buffer Element Count bits */
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#define SPI_STAT_TXBUFELM_MASK (31 << SPI_STAT_TXBUFELM_SHIFT)
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#define SPI_STAT_RXBUFELM_SHIFT (24) /* Bits 24-28: Receive Buffer Element Count bits */
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#define SPI_STAT_RXBUFELM_MASK (31 << SPI_STAT_RXBUFELM_SHIFT)
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/* SPI buffer register (May be 31-bits wide on some parts) */
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#define SPI_BUF_MASK 0x1ff
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/* SPI baud rate register (This register holds 32-bits of data with other
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* bit-fields
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*/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_SPI_H */
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@ -42,6 +42,7 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#include "pic32mx-memorymap.h"
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/************************************************************************************
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