armv8-m: make the securefault handled by non-securefult
tee is secure cpu and ap is non-secure cpu. The crash PC can get by IP (R12). [ EMERG] [tee] arm_hardfault: Hard Fault escalation: [ EMERG] [tee] arm_securefault: PANIC!!! Secure Fault: [ EMERG] [tee] arm_securefault: IRQ: 3 regs: 0x2400ff00 [ EMERG] [tee] arm_securefault: BASEPRI: 000000e0 PRIMASK: 00000000 IPSR: 00000003 CONTROL: 0000000c [ EMERG] [tee] arm_securefault: CFSR: 00000000 HFSR: 40000000 DFSR: 00000000 [ EMERG] [tee] arm_securefault: BFAR: 08006008 AFSR: 00000000 SFAR: 3c049ea0 [ EMERG] [tee] arm_securefault: Secure Fault Reason: [ EMERG] [tee] arm_securefault: Attribution unit violation [ EMERG] [tee] arm_securefault_handled_by_ns: Non-sec sp 3c475678 [ EMERG] [ap] arm_busfault: PANIC!!! Bus Fault: [ EMERG] [ap] arm_busfault: IRQ: 5 regs: 0x3c475608 [ EMERG] [ap] arm_busfault: BASEPRI: 000000e0 PRIMASK: 00000000 IPSR: 00000005 CONTROL: 00000004 [ EMERG] [ap] arm_busfault: CFSR: 00000100 HFSR: 40000000 DFSR: 00000000 BFAR: 08006008 AFSR: 20000000 [ EMERG] [ap] arm_busfault: Bus Fault Reason: [ EMERG] [ap] arm_busfault: Instruction bus error [ EMERG] [ap] up_assert: Assertion failed at file:armv8-m/arm_busfault.c line: 105 task: nsh_main [ EMERG] [ap] backtrace: [ EMERG] [ap] [ 9] [<0x2c565246>] up_backtrace+0xa/0x168 [ EMERG] [ap] [ 9] [<0x2c550118>] sched_dumpstack+0x1c/0x60 [ EMERG] [ap] [ 9] [<0x2c5645d6>] up_assert+0x4e/0x324 [ EMERG] [ap] [ 9] [<0x2c54a98e>] _assert+0x2/0x10 [ EMERG] [ap] [ 9] [<0x2c5636d4>] arm_busfault+0xc8/0x15c [ EMERG] [ap] [ 9] [<0x2c523070>] irq_dispatch+0x40/0x11c [ EMERG] [ap] [ 9] [<0x2c563424>] arm_doirq+0x28/0x3c [ EMERG] [ap] [ 9] [<0x2c55c892>] exception_common+0x4a/0xac [ EMERG] [ap] [ 9] [<0x2c58668e>] nsh_parse_command+0x976/0x12b4 [ EMERG] [ap] [ 9] [<0x2c849cee>] write+0x52/0x74 [ EMERG] [ap] [ 9] [<0x2c58c0ac>] nsh_session+0x2c/0x1c8 [ EMERG] [ap] [ 9] [<0x2c58d82c>] nsh_consolemain+0x28/0x54 [ EMERG] [ap] [ 9] [<0x2c590352>] nsh_main+0x2a/0x48 [ EMERG] [ap] [ 9] [<0x2c5500da>] cxx_initialize+0x2a/0x4c [ EMERG] [ap] [ 9] [<0x2c550090>] nxtask_startup+0x14/0x34 [ EMERG] [ap] [ 9] [<0x2c52966a>] nxtask_start+0x92/0xb8 [ EMERG] [ap] arm_registerdump: R0: 3c049ea0 R1: 00000004 R2: 3c448f98 R3: 00000000 [ EMERG] [ap] arm_registerdump: R4: 3c476a98 R5: 3c049ea0 R6: 00000000 FP: 3c476aac [ EMERG] [ap] arm_registerdump: R8: 2c5873c9 SB: 3c049ea0 SL: 3c2e98fc R11: 3c284c2c [ EMERG] [ap] arm_registerdump: IP: 2c58ba4a SP: 3c4756e0 LR: 3c049ea4 PC: 00000000 [ EMERG] [ap] arm_registerdump: xPSR: 610f0000 BASEPRI: 000000e0 CONTROL: 00000004 [ EMERG] [ap] arm_registerdump: EXC_RETURN: ffffffa8 [ EMERG] [ap] arm_dump_stack: IRQ Stack: [ EMERG] [ap] arm_dump_stack: sp: 3c41c900 Signed-off-by: ligd <liguiding1@xiaomi.com>
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@ -41,6 +41,38 @@
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#ifdef CONFIG_DEBUG_SECUREFAULT
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# define sfalert(format, ...) _alert(format, ##__VA_ARGS__)
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# define OFFSET_R0 (0 * 4) /* R0 */
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# define OFFSET_R1 (1 * 4) /* R1 */
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# define OFFSET_R2 (2 * 4) /* R2 */
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# define OFFSET_R3 (3 * 4) /* R3 */
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# define OFFSET_R12 (4 * 4) /* R12 */
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# define OFFSET_R14 (5 * 4) /* R14 = LR */
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# define OFFSET_R15 (6 * 4) /* R15 = PC */
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# define OFFSET_XPSR (7 * 4) /* xPSR */
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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static void generate_nonsecure_busfault(void)
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{
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uint32_t nsp;
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/* Get non-secure SP */
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__asm__ __volatile__ ("mrs %0, msp_ns" : "=r" (nsp));
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sfalert("Non-sec sp %08" PRIx32 "\n", nsp);
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syslog_flush();
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/* Force set return ReturnAddress to 0, then non-secure cpu will crash.
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* Also, the ReturnAddress is very important, so move it to R12.
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*/
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putreg32(getreg32(nsp + OFFSET_R15), nsp + OFFSET_R12);
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putreg32(0, nsp + OFFSET_R15);
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}
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#else
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# define sfalert(...)
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#endif
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@ -112,7 +144,12 @@ int arm_securefault(int irq, FAR void *context, FAR void *arg)
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putreg32(0xff, SAU_SFSR);
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#ifdef CONFIG_DEBUG_SECUREFAULT
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generate_nonsecure_busfault();
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#else
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up_irq_save();
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PANIC();
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#endif
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return OK;
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}
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