ARMv7-A: Add global timer header file
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Gregory Nutt
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a2052d006c
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613786ff3d
@ -12,6 +12,13 @@ config ARMV7A_HAVE_GIC
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Selected by the configuration tool if the architecture supports the
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Generic Interrupt Controller (GIC)
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config ARMV7A_HAVE_GTM
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bool
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default n
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---help---
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Selected by the configuration tool if the architecture supports the
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Global Timer (GTM)
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config ARMV7A_HAVE_L2CC
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bool
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default n
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143
arch/arm/src/armv7-a/gtm.h
Normal file
143
arch/arm/src/armv7-a/gtm.h
Normal file
@ -0,0 +1,143 @@
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/****************************************************************************
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* arch/arm/src/armv7-a/gtm.h
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* Global Timer Definitions
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Reference:
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* Cortex™-A9 MPCore, Revision: r4p1, Technical Reference Manual, ARM DDI
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* 0407I (ID091612).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV7_A_GTM_H
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#define __ARCH_ARM_SRC_ARMV7_A_GTM_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "nuttx/config.h"
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#include <stdint.h>
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#include "mpcore.h"
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#ifdef CONFIG_ARMV7A_HAVE_GTM
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* GIC Register Offsets *****************************************************/
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#define GTM_COUNT0_OFFSET 0x0000 /* Global Timer Counter Register 0 */
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#define GTM_COUNT1_OFFSET 0x0004 /* Global Timer Counter Register 1 */
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#define GTM_CTRL_OFFSET 0x0008 /* Global Timer Control Register */
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#define GTM_STA_OFFSET 0x000c /* Global Timer Interrupt Status Register */
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#define GTM_COMP0_OFFSET 0x0010 /* Comparator Value Register 0 */
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#define GTM_COMP1_OFFSET 0x0014 /* Comparator Value Register 1 */
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#define GTM_AUTO_OFFSET 0x0018 /* Auto-increment Register */
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/* GIC Register Addresses ***************************************************/
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#define GTM_COUNT0 (MPCORE_GTM_VBASE+GTM_COUNT0_OFFSET)
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#define GTM_COUNT1 (MPCORE_GTM_VBASE+GTM_COUNT1_OFFSET)
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#define GTM_CTRL (MPCORE_GTM_VBASE+GTM_CTRL_OFFSET)
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#define GTM_STA (MPCORE_GTM_VBASE+GTM_STA_OFFSET)
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#define GTM_COMP0 (MPCORE_GTM_VBASE+GTM_COMP0_OFFSET)
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#define GTM_COMP1 (MPCORE_GTM_VBASE+COMPARE1_OFFSET)
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#define GTM_AUTO (MPCORE_GTM_VBASE+AUTO_OFFSET)
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/* GIC Register Bit Definitions *********************************************/
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/* Global Timer Counter Register 0/1 -- 64-bit timer counter value */
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/* Global Timer Control Register */
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#define GTM_CTRL_TIMEN (1 << 0) /* Bit 0: Timer comparator */
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#define GTM_CTRL_CMPEN (1 << 1) /* Bit 1: Enable comparator */
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#define GTM_CTRL_INTEN (1 << 2) /* Bit 2: Enable timer interrupt ID 27 */
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#define GTM_CTRL_AUTO (1 << 3) /* Bit 3: Auto-increment comparator register */
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/* Bits 4-7: Reserved */
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#define GTM_CTRL_PRESC_SHIFT (8) /* Bits 8-15: PERIPHCLK prescaler */
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#define GTM_CTRL_PRESC_MASK (0xff << GTM_CTRL_PRESC_SHIFT)
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# define GTM_CTRL_PRESC(n) ((uint32_t)(n) << GTM_CTRL_PRESC_SHIFT)
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/* Bits 16-31: Reserved */
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/* Global Timer Interrupt Status Register */
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#define GTM_STA_EVENT (1 << 0) /* Timer event flag */
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/* Bits 1-31: Reserved */
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/* Comparator Value Register 0/1 -- 64-bit timer compare value */
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/* Auto-increment Register -- 32-bit auto-increment value */
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Name:
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*
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* Description:
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*
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* Input Parameters:
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*
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* Returned Value:
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*
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****************************************************************************/
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/* Clocking:
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* CLK - This is the main clock of the Cortex-A9 processor. All Cortex-A9
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* processors in the Cortex-A9 MPCore processor and the SCU are clocked
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* with a distributed version of CLK.
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* PERIPHCLK - The Interrupt Controller, global timer, private timers, and
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* watchdogs are clocked with PERIPHCLK. PERIPHCLK must be synchronous
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* with CLK, and the PERIPHCLK clock period, N, must be configured as a
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* multiple of the CLK clock period. This multiple N must be equal to,
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* or greater than two.
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*/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_ARMV7A_HAVE_GIC */
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#endif /* __ARCH_ARM_SRC_ARMV7_A_GTM_H */
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@ -21,16 +21,19 @@ config ARCH_CHIP_IMX6_6DUALLITE
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bool "i.MX 6DualLite"
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select ARCH_HAVE_MULTICPU
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select ARMV7A_HAVE_GIC
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select ARMV7A_HAVE_GTM
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config ARCH_CHIP_IMX6_6DUAL
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bool "i.MX 6Dual"
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select ARCH_HAVE_MULTICPU
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select ARMV7A_HAVE_GIC
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select ARMV7A_HAVE_GTM
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config ARCH_CHIP_IMX6_6QUAD
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bool "i.MX 6Quad"
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select ARCH_HAVE_MULTICPU
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select ARMV7A_HAVE_GIC
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select ARMV7A_HAVE_GTM
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endchoice # iMX.6 Chip Selection
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