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SAM4L: Extend interrupt support for the larger number of NVIC interrupts of the SAM4L

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This commit is contained in:
Gregory Nutt 2013-06-09 13:00:38 -06:00
parent 2f4ae2f2b0
commit 617a0225cc
3 changed files with 75 additions and 16 deletions
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4
arch/arm/src/armv7-m/nvic.h
View File

@ -399,8 +399,8 @@
/* Interrrupt controller type (INCTCTL_TYPE) */ /* Interrrupt controller type (INCTCTL_TYPE) */
#define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 4-0: Number of interrupt intputs / 32 */ #define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 0-3: Number of interrupt inputs / 32 - 1 */
#define NVIC_ICTR_INTLINESNUM_MASK (0x1f << NVIC_ICTR_INTLINESNUM_SHIFT) #define NVIC_ICTR_INTLINESNUM_MASK (15 << NVIC_ICTR_INTLINESNUM_SHIFT)
/* SysTick control and status register (SYSTICK_CTRL) */ /* SysTick control and status register (SYSTICK_CTRL) */

86
arch/arm/src/sam34/sam_irq.c
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@ -221,18 +221,51 @@ static inline void sam_prioritize_syscall(int priority)
static int sam_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) static int sam_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
{ {
unsigned int extint = irq - SAM_IRQ_EXTINT;
DEBUGASSERT(irq >= SAM_IRQ_NMI && irq < NR_IRQS); DEBUGASSERT(irq >= SAM_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */ /* Check for external interrupt */
if (irq >= SAM_IRQ_EXTINT) if (irq >= SAM_IRQ_EXTINT)
{ {
if (irq < SAM_IRQ_NIRQS) #if SAM_IRQ_NEXTINT <= 32
if (extint < SAM_IRQ_NEXTINT)
{ {
*regaddr = NVIC_IRQ0_31_ENABLE; *regaddr = NVIC_IRQ0_31_ENABLE;
*bit = 1 << (irq - SAM_IRQ_EXTINT); *bit = 1 << extint;
} }
else else
#elif SAM_IRQ_NEXTINT <= 64
if (extint < 32)
{
*regaddr = NVIC_IRQ0_31_ENABLE;
*bit = 1 << extint;
}
else if (extint < SAM_IRQ_NEXTINT)
{
*regaddr = NVIC_IRQ32_63_ENABLE;
*bit = 1 << (extint - 32);
}
else
#elif SAM_IRQ_NEXTINT <= 96
if (extint < 32)
{
*regaddr = NVIC_IRQ0_31_ENABLE;
*bit = 1 << extint;
}
else if (extint < 64)
{
*regaddr = NVIC_IRQ32_63_ENABLE;
*bit = 1 << (extint - 32);
}
else if (extint < SAM_IRQ_NEXTINT)
{
*regaddr = NVIC_IRQ64_95_ENABLE;
*bit = 1 << (extint - 64);
}
else
#endif
{ {
return ERROR; /* Invalid interrupt */ return ERROR; /* Invalid interrupt */
} }
@ -279,9 +312,32 @@ static int sam_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
void up_irqinitialize(void) void up_irqinitialize(void)
{ {
/* Disable all interrupts */ uintptr_t regaddr;
int nintlines;
int i;
putreg32(0, NVIC_IRQ0_31_ENABLE); /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt
* lines that the NVIC supports, defined in groups of 32. That is,
* the total number of interrupt lines is up to (32*(INTLINESNUM+1)).
*
* 0 -> 32 interrupt lines, 1 enable register, 8 priority registers
* 1 -> 64 " " " ", 2 enable registers, 16 priority registers
* 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers
* ...
*/
nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1;
/* Disable all interrupts. There are nintlines interrupt enable
* registers.
*/
for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE;
i > 0;
i--, regaddr += 4)
{
putreg32(0, regaddr);
}
/* Set up the vector table address. /* Set up the vector table address.
* *
@ -291,24 +347,26 @@ void up_irqinitialize(void)
#if defined(CONFIG_ARCH_RAMVECTORS) #if defined(CONFIG_ARCH_RAMVECTORS)
up_ramvec_initialize(); up_ramvec_initialize();
#elif defined(CONFIG_STM32_DFU) #elif defined(CONFIG_SAM_BOOTLOADER)
putreg32((uint32_t)sam_vectors, NVIC_VECTAB); putreg32((uint32_t)sam_vectors, NVIC_VECTAB);
#endif #endif
/* Set all interrrupts (and exceptions) to the default priority */ /* Set all interrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); /* Now set all of the interrupt lines to the default priority. There are
putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); * nintlines * 8 priority registers.
putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); */
putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY;
putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); i > 0;
putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); i--, regaddr += 4)
putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); {
putreg32(0, regaddr);
}
/* currents_regs is non-NULL only while processing an interrupt */ /* currents_regs is non-NULL only while processing an interrupt */

1
arch/arm/src/sam34/sam_serial.c
View File

@ -1310,6 +1310,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
priv->imr &= ~UART_INT_TXRDY; priv->imr &= ~UART_INT_TXRDY;
up_disableint(priv); up_disableint(priv);
} }
irqrestore(flags); irqrestore(flags);
} }