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LPC17xx GPIO interrupt fixes: lpc17_setintedge() must be atomic. Can't disable interrupts from interrupt handlers because they are automatically re-enabled. Try re-configuring pin instead.

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This commit is contained in:
Gregory Nutt 2013-04-07 13:46:05 -06:00
parent 7fcbf3f151
commit 617ab59c5a
2 changed files with 11 additions and 4 deletions
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2
arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h
View File

@ -99,7 +99,7 @@
#define GPIO_SSP1_MISO_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
#define GPIO_MAT2p2_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
#define GPIO_RTC_EV1_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
#define GPIO_LCD_VD16 (GPIO_ALT7 | GPIO_FLOA | GPIO_HYSTERESIST | GPIO_PORT0 | GPIO_PIN8)
#define GPIO_LCD_VD16 (GPIO_ALT7 | GPIO_FLOAT | GPIO_HYSTERESIS | GPIO_PORT0 | GPIO_PIN8)
#define GPIO_I2S_TXSDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
#define GPIO_SSP1_MOSI_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)

13
arch/arm/src/lpc17xx/lpc17_gpioint.c
View File

@ -116,8 +116,13 @@ static unsigned int lpc17_getintedge(unsigned int port, unsigned int pin)
static void lpc17_setintedge(uint32_t intbase, unsigned int pin,
unsigned int edges)
{
irqstate_t flags;
int regval;
/* These must be atomic */
flags = irqsave();
/* Set/clear the rising edge enable bit */
regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET);
@ -145,6 +150,7 @@ static void lpc17_setintedge(uint32_t intbase, unsigned int pin,
}
putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET);
irqrestore(flags);
}
/****************************************************************************
@ -389,9 +395,10 @@ static void lpc17_gpiodemux(uint32_t intbase, uint32_t intmask,
* Name: lpc17_gpiointerrupt
*
* Description:
* Handle the EINT3 interrupt that also indicates that a GPIO interrupt has
* occurred. NOTE: This logic will have to be extended if EINT3 is
* actually used for External Interrupt 3.
* Handle the GPIO interrupt. For the LPC176x family, that interrupt could
* also that also indicates that an EINT3 interrupt has occurred. NOTE:
* This logic would have to be extended if EINT3 is actually used for
* External Interrupt 3 on an LPC176x platform.
*
****************************************************************************/