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Merged nuttx/nuttx into master

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This commit is contained in:
Matt Thompson 2018-01-28 21:08:51 -08:00
commit 621567507c
33 changed files with 183 additions and 103 deletions
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2
ChangeLog
View File

@ -17445,7 +17445,7 @@
* The lcdrw example has been removed because it violates the portable OS
interface (2017-10-14).
* All configurations that use NXIMAGE or NXHELLO must select
NX_MULTIUSER. All configuratinos that use examples/nxterm must enable
NX_MULTIUSER. All configurations that use examples/nxterm must enable
CONFIG_LIB_BOARDCTL (2017-10-14).
* configs/stm32f103-minimum: Add support for LM75 in the
stm32f103-minimum board. From Alan Carvalho de Assis (2017-10-14).

2
ReleaseNotes
View File

@ -16669,7 +16669,7 @@ detailed bugfix information):
* Examples/Tests: apps/examples:
- All configurations that use NXIMAGE or NXHELLO must select
NX_MULTIUSER. All configuratinos that use examples/nxterm must
NX_MULTIUSER. All configurations that use examples/nxterm must
enable CONFIG_LIB_BOARDCTL.
- All configurations that use NXLINES must select NX_MULTIUSER. All
configurations that use the NX server need to have larger POSIX

2
arch/arm/src/sama5/Kconfig
View File

@ -165,7 +165,7 @@ config SAMA5_HAVE_VDEC
bool
default n
# Summary configuratinos
# Summary configurations
config SAMA5_FLEXCOM
bool

8
arch/arm/src/samv7/sam_config.h
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/samv7/sam-config.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -144,7 +144,11 @@
# undef CONFIG_SAMV7_USART2
#endif
/* Are any USARTs enabled? */
/* Are any USARTs enabled?
*
* REVISIT: Setting HAVE_UART_DEVICE only makes sense of the USART is being
* used as a UART.
*/
#if defined(CONFIG_SAMV7_USART0) || defined(CONFIG_SAMV7_USART1) || \
defined(CONFIG_SAMV7_USART2)

23
arch/arm/src/samv7/sam_lowputc.c
View File

@ -172,26 +172,6 @@
#endif /* HAVE_SERIAL_CONSOLE */
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
@ -277,6 +257,9 @@ void sam_lowsetup(void)
uint64_t divb3;
uint32_t intpart;
uint32_t fracpart;
#endif
#if (defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)) || \
defined(CONFIG_SAMV7_USART1)
uint32_t regval;
#endif

2
arch/arm/src/samv7/sam_qspi.c
View File

@ -1737,7 +1737,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
#ifdef CONFIG_SAMV7_QSPI
if (intf == 0)
{
/* If this function is called multiple times, the following operatinos
/* If this function is called multiple times, the following operations
* will be performed multiple times.
*/

32
arch/arm/src/stm32/Kconfig
View File

@ -2195,7 +2195,7 @@ config STM32_COMP6
config STM32_COMP7
bool "COMP7"
default n
depends on STM32_HAVE_COMP6
depends on STM32_HAVE_COMP7
config STM32_BKP
bool "BKP"
@ -5864,6 +5864,11 @@ config STM32_HRTIM_DEADTIME
depends on STM32_HRTIM_PWM
default n
config STM32_HRTIM_PUSHPULL
bool "HRTIM push-pull mode"
depends on STM32_HRTIM_PWM
default n
config STM32_HRTIM_DMA
bool "HRTIM DMA"
default n
@ -6041,6 +6046,11 @@ config STM32_HRTIM_TIMA_DT
default n
depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMA_PWM)
config STM32_HRTIM_TIMA_PSHPLL
bool "HRTIM TIMA PWM Push-pull mode"
default n
depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMA_PWM)
endmenu # "HRTIM Timer A Configuration"
menu "HRTIM Timer B Configuration"
@ -6106,6 +6116,11 @@ config STM32_HRTIM_TIMB_DT
default n
depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMB_PWM)
config STM32_HRTIM_TIMB_PSHPLL
bool "HRTIM TIMB PWM Push-pull mode"
default n
depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMB_PWM)
endmenu # "HRTIM Timer B Configuration"
menu "HRTIM Timer C Configuration"
@ -6171,6 +6186,11 @@ config STM32_HRTIM_TIMC_DT
default n
depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMC_PWM)
config STM32_HRTIM_TIMC_PSHPLL
bool "HRTIM TIMC PWM Push-pull mode"
default n
depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMC_PWM)
endmenu # "HRTIM Timer C Configuration"
menu "HRTIM Timer D Configuration"
@ -6236,6 +6256,11 @@ config STM32_HRTIM_TIMD_DT
default n
depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMD_PWM)
config STM32_HRTIM_TIMD_PSHPLL
bool "HRTIM TIMD PWM Push-pull mode"
default n
depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMD_PWM)
endmenu # "HRTIM Timer D Configuration"
menu "HRTIM Timer E Configuration"
@ -6301,6 +6326,11 @@ config STM32_HRTIM_TIME_DT
default n
depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIME_PWM)
config STM32_HRTIM_TIME_PSHPLL
bool "HRTIM TIME PWM Push-pull mode"
default n
depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIME_PWM)
endmenu # "HRTIM Timer E Configuration"
endif # STM32_HRTIM1

1
arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h
View File

@ -129,7 +129,6 @@
#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff: TIM13 timer */
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 timer */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP registers */
#define STM32_BKP_BASE 0x40002850
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: Window watchdog (WWDG) */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: Independent watchdog (IWDG) */
#define STM32_I2S2EXT_BASE 0x40003400 /* 0x40003400-0x400037ff: I2S2ext */

3
arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
View File

@ -92,8 +92,7 @@
#define STM32_TIM4_BASE 0x40000800 /* 0x40000800-0x40000bff TIM4 */
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
#define STM32_BKP_BASE 0x40002850 /* 0x40002850-0x4000288c BKP */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC and BKP */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32_I2S2EXT_BASE 0x40003400 /* 0x40003400-0x400037ff I2S2ext */

3
arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h
View File

@ -93,8 +93,7 @@
#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
#define STM32_BKP_BASE 0x40002850 /* 0x40002850-0x400028cc BKP */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC and BKP */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */

3
arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
View File

@ -93,8 +93,7 @@
#define STM32_TIM12_BASE 0x40001800 /* 0x40001800-0x40001bff TIM12 */
#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff TIM13 */
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff TIM14 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
#define STM32_BKP_BASE 0x40002850 /* 0x40002850-0x400028cc BKP */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC and BKP */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */

1
arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h
View File

@ -129,7 +129,6 @@
#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff: TIM13 timer */
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 timer */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP registers */
#define STM32_BKP_BASE 0x40002850
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: Window watchdog (WWDG) */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: Independent watchdog (IWDG) */
#define STM32_I2S2EXT_BASE 0x40003400 /* 0x40003400-0x400037ff: I2S2ext */

1
arch/arm/src/stm32/stm32.h
View File

@ -57,7 +57,6 @@
#include "chip.h"
#include "stm32_adc.h"
//#include "stm32_bkp.h"
#include "stm32_can.h"
#include "stm32_comp.h"
#include "stm32_dbgmcu.h"

12
arch/arm/src/stm32/stm32_bkp.h
View File

@ -42,8 +42,18 @@
#include <nuttx/config.h>
/* Only the STM32 F1 family has a dedicated address region for BKP memory. For F2,
* F3, and F4 parts, the bKP registers lie in the same address region as the RTCC
* and the definitions in chip/stm32_rtcc.h should be used to access backup
* registers. NOTE: These definitions are not interchangeable!
*/
#include "chip.h"
#include "chip/stm32_bkp.h"
#ifdef CONFIG_STM32_STM32F10XX
# include "chip/stm32_bkp.h"
#else
# include "chip/stm32_rtcc.h"
#endif
/************************************************************************************
* Pre-processor Definitions

65
arch/arm/src/stm32/stm32_hrtim.c
View File

@ -180,6 +180,29 @@
# error "CONFIG_STM32_HRTIM_CHOPPER must be set"
# endif
#endif
#if defined(CONFIG_STM32_HRTIM_TIMA_PSHPLL) || defined(CONFIG_STM32_HRTIM_TIMB_PSHPLL) || \
defined(CONFIG_STM32_HRTIM_TIMC_PSHPLL) || defined(CONFIG_STM32_HRTIM_TIMD_PSHPLL) || \
defined(CONFIG_STM32_HRTIM_TIME_PSHPLL)
# ifndef CONFIG_STM32_HRTIM_PUSHPULL
# error "CONFIG_STM32_HRTIM_PUSHPULL must be set"
# endif
#endif
#if defined(CONFIG_STM32_HRTIM_TIMA_DT) && defined(CONFIG_STM32_HRTIM_TIMA_PSHPLL)
# error "The deadtime cannot be used simultaneously with the push-pull mode"
#endif
#if defined(CONFIG_STM32_HRTIM_TIMB_DT) && defined(CONFIG_STM32_HRTIM_TIMB_PSHPLL)
# error "The deadtime cannot be used simultaneously with the push-pull mode"
#endif
#if defined(CONFIG_STM32_HRTIM_TIMC_DT) && defined(CONFIG_STM32_HRTIM_TIMC_PSHPLL)
# error "The deadtime cannot be used simultaneously with the push-pull mode"
#endif
#if defined(CONFIG_STM32_HRTIM_TIMD_DT) && defined(CONFIG_STM32_HRTIM_TIMD_PSHPLL)
# error "The deadtime cannot be used simultaneously with the push-pull mode"
#endif
#if defined(CONFIG_STM32_HRTIM_TIME_DT) && defined(CONFIG_STM32_HRTIM_TIME_PSHPLL)
# error "The deadtime cannot be used simultaneously with the push-pull mode"
#endif
#if defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || defined(CONFIG_STM32_HRTIM_ADC1_TRG2) || \
defined(CONFIG_STM32_HRTIM_ADC1_TRG3) || defined(CONFIG_STM32_HRTIM_ADC1_TRG4) || \
@ -305,7 +328,7 @@ struct stm32_hrtim_timout_s
#ifdef CONFIG_STM32_HRTIM_CHOPPER
struct stm32_hrtim_chopper_s
{
uint16_t start:4; /* Chopper start pulsewidth */
uint16_t start_pulse:4; /* Chopper start pulsewidth */
uint16_t freq:4; /* Chopper carrier frequency value */
uint16_t duty:3; /* Chopper duty cycle */
uint16_t _res:5; /* Reserved */
@ -345,6 +368,8 @@ struct stm32_hrtim_tim_burst_s
struct stm32_hrtim_pwm_s
{
uint8_t pushpull:1;
uint8_t res:7;
struct stm32_hrtim_timout_s ch1; /* Channel 1 Set/Reset configuration*/
struct stm32_hrtim_timout_s ch2; /* Channel 2 Set/Reset configuration */
@ -786,6 +811,9 @@ static struct stm32_hrtim_slave_priv_s g_tima_priv =
#ifdef CONFIG_STM32_HRTIM_TIMA_PWM
.pwm =
{
#ifdef CONFIG_STM32_HRTIM_TIMA_PSHPLL
.pushpull = 1,
#endif
#ifdef CONFIG_STM32_HRTIM_TIMA_PWM_CH1
.ch1 =
{
@ -883,6 +911,9 @@ static struct stm32_hrtim_slave_priv_s g_timb_priv =
#ifdef CONFIG_STM32_HRTIM_TIMB_PWM
.pwm =
{
#ifdef CONFIG_STM32_HRTIM_TIMB_PSHPLL
.pushpull = 1,
#endif
#ifdef CONFIG_STM32_HRTIM_TIMB_PWM_CH1
.ch1 =
{
@ -980,6 +1011,9 @@ static struct stm32_hrtim_slave_priv_s g_timc_priv =
#ifdef CONFIG_STM32_HRTIM_TIMC_PWM
.pwm =
{
#ifdef CONFIG_STM32_HRTIM_TIMC_PSHPLL
.pushpull = 1,
#endif
#ifdef CONFIG_STM32_HRTIM_TIMC_PWM_CH1
.ch1 =
{
@ -1077,6 +1111,9 @@ static struct stm32_hrtim_slave_priv_s g_timd_priv =
#ifdef CONFIG_STM32_HRTIM_TIMD_PWM
.pwm =
{
#ifdef CONFIG_STM32_HRTIM_TIMD_PSHPLL
.pushpull = 1,
#endif
#ifdef CONFIG_STM32_HRTIM_TIMD_PWM_CH1
.ch1 =
{
@ -1174,6 +1211,9 @@ static struct stm32_hrtim_slave_priv_s g_time_priv =
#ifdef CONFIG_STM32_HRTIM_TIME_PWM
.pwm =
{
#ifdef CONFIG_STM32_HRTIM_TIME_PSHPLL
.pushpull = 1,
#endif
#ifdef CONFIG_STM32_HRTIM_TIME_PWM_CH1
.ch1 =
{
@ -1518,7 +1558,7 @@ static const struct stm32_hrtim_ops_s g_hrtim1ops =
.burst_pre_get = hrtim_burst_pre_get,
#endif
#ifdef CONFIG_STM32_HRTIM_CHOPPER
.chopper_enable = hrtim_chopper_enable
.chopper_enable = hrtim_chopper_enable,
#endif
#ifdef CONFIG_STM32_HRTIM_DEADTIME
.deadtime_update = hrtim_deadtime_update,
@ -2808,6 +2848,15 @@ static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t time
}
#endif
#ifdef CONFIG_STM32_HRTIM_PUSHPULL
if (slave->pwm.pushpull == 1)
{
/* Enable push-pull mode */
hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, 0, HRTIM_TIMCR_PSHPLL);
}
#endif
errout:
return ret;
}
@ -3640,13 +3689,13 @@ static int hrtim_chopper_enable(FAR struct hrtim_dev_s *dev, uint8_t timer,
{
/* Set enable bit */
hrtim_tim_modifyreg(priv, index, STM32_HRTIM_TIM_OUTR_OFFSET, 0, val);
hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, 0, val);
}
else
{
/* Clear enable bit */
hrtim_tim_modifyreg(priv, index, STM32_HRTIM_TIM_OUTR_OFFSET, val, 0);
hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, val, 0);
}
errout:
@ -3698,6 +3747,7 @@ static int hrtim_tim_chopper_cfg(FAR struct stm32_hrtim_s *priv,
hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CHPR_OFFSET, regval);
errout:
return OK;
}
@ -4511,13 +4561,6 @@ static void hrtim_tim_mode_set(FAR struct stm32_hrtim_s *priv, uint8_t timer,
regval |= HRTIM_CMNCR_CONT;
}
/* Configure push-pull mode. Only Slaves */
if (mode & HRTIM_MODE_PSHPLL && timer != HRTIM_TIMER_MASTER)
{
regval |= HRTIM_TIMCR_PSHPLL;
}
/* Write register */
hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval);

4
arch/arm/src/stm32/stm32_hrtim.h
View File

@ -415,10 +415,6 @@ enum stm32_hrtim_mode_e
HRTIM_MODE_HALF = (1 << 1), /* Half mode */
HRTIM_MODE_RETRIG = (1 << 2), /* Re-triggerable mode */
HRTIM_MODE_CONT = (1 << 3), /* Continuous mode */
/* Only slave Timers */
HRTIM_MODE_PSHPLL = (1 << 7), /* Push-Pull mode */
};
/* HRTIM Slave Timer auto-delayed mode

1
arch/arm/src/stm32f7/chip/stm32f72xx73xx_memorymap.h
View File

@ -112,7 +112,6 @@
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 */
#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
#define STM32_BKP_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */

1
arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
View File

@ -113,7 +113,6 @@
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 */
#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
#define STM32_BKP_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */

1
arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h
View File

@ -113,7 +113,6 @@
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 */
#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
#define STM32_BKP_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */
#define STM32_CAN3_BASE 0x40003400 /* 0x40003400-0x400037ff: CAN3 */

4
configs/flipnclick-pic32mz/README.txt
View File

@ -218,8 +218,8 @@ LEDs and Buttons
LED_PANIC The system has crashed 2Hz N/C N/C N/C N/C
LED_IDLE MCU is is sleep mode ---- Not used -----
Thus if LED L is glowing on and all other LEDs are off (except LED D which
was left on but is no longer controlled by NuttX and so may be in any
Thus if LED L is glowing faintly and all other LEDs are off (except LED D
which was left on but is no longer controlled by NuttX and so may be in any
state), NuttX has successfully booted and is, apparently, running normally
and taking interrupts. If any of LEDs A-D are statically set, then NuttX
failed to boot and the LED indicates the initialization phase where the

2
configs/flipnclick-pic32mz/include/board.h
View File

@ -240,7 +240,7 @@
#define LED_PANIC 4 /* The system has crashed 2Hz N/C N/C N/C N/C */
#undef LED_IDLE /* MCU is is sleep mode ---- Not used ----- */
/* Thus if LED L is glowing on and all other LEDs are off (except LED D which
/* Thus if LED L is faintly glowing and all other LEDs are off (except LED D which
* was left on but is no longer controlled by NuttX and so may be in any state),
* NuttX has successfully booted and is, apparently, running normally and taking
* interrupts. If any of LEDs A-D are statically set, then NuttX failed to boot

9
configs/flipnclick-pic32mz/src/pic32mz_autoleds.c
View File

@ -57,6 +57,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* There are four LEDs on the top, red side of the board. Only one can be
* controlled by software:
*
@ -89,8 +90,8 @@
* LED_PANIC The system has crashed 2Hz N/C N/C N/C N/C
* LED_IDLE MCU is is sleep mode ---- Not used -----
*
* Thus if LED L is glowing on and all other LEDs are off (except LED D
* which was left on but is no longer controlled by NuttX and so may be in
* Thus if LED L is faintly glowing and all other LEDs are off (except LED
* D which was left on but is no longer controlled by NuttX and so may be in
* any state), NuttX has successfully booted and is, apparently, running
* normally and taking interrupts. If any of LEDs A-D are statically set,
* then NuttX failed to boot and the LED indicates the initialization phase
@ -122,7 +123,7 @@ static void board_autoled_setone(int ledndx)
pic32mz_gpiowrite(GPIO_LED_L, ledon[INDEX_LED_L]);
pic32mz_gpiowrite(GPIO_LED_A, ledon[INDEX_LED_A]);
pic32mz_gpiowrite(GPIO_LED_B, ledon[INDEX_LED_B]);
pic32mz_gpiowrite(GPIO_LED_C, ledon[INDEX_LED_D]);
pic32mz_gpiowrite(GPIO_LED_C, ledon[INDEX_LED_C]);
pic32mz_gpiowrite(GPIO_LED_D, ledon[INDEX_LED_D]);
}
@ -175,7 +176,7 @@ void board_autoled_on(int led)
board_autoled_setone(INDEX_LED_B);
break;
case 2:
case 2:
board_autoled_setone(INDEX_LED_C);
break;

6
configs/flipnclick-sam3x/README.txt
View File

@ -71,8 +71,8 @@ Buttons and LEDs
LED_PANIC The system has crashed 2Hz N/C N/C N/C N/C
LED_IDLE MCU is is sleep mode ---- Not used -----
Thus if LED L is glowing on and all other LEDs are off (except LED D which
was left on but is no longer controlled by NuttX and so may be in any
Thus if LED L is glowing faintly and all other LEDs are off (except LED D
which was left on but is no longer controlled by NuttX and so may be in any
state), NuttX has successfully booted and is, apparently, running normally
and taking interrupts. If any of LEDs A-D are statically set, then NuttX
failed to boot and the LED indicates the initialization phase where the
@ -397,7 +397,7 @@ Loading Code
3 GND GND
4 JTAG_TCK SWDCLK/TCK SAM3X pin 28, Pulled up on board
5 GND GND
6 JTAG_TDO SWO/EXta/TRACECTL SAM3X pin 30, ulled up on board
6 JTAG_TDO SWO/EXta/TRACECTL SAM3X pin 30, Pulled up on board
7 N/C Key
8 JTAG_TDI NC/EXTb/TDI SAM3X pin 29, Pulled up on board
9 GND GNDDetect

2
configs/flipnclick-sam3x/include/board.h
View File

@ -211,7 +211,7 @@
#define LED_PANIC 4 /* The system has crashed 2Hz N/C N/C N/C N/C */
#undef LED_IDLE /* MCU is is sleep mode ---- Not used ----- */
/* Thus if LED L is glowing on and all other LEDs are off (except LED D which
/* Thus if LED L is faintly glowing and all other LEDs are off (except LED D which
* was left on but is no longer controlled by NuttX and so may be in any state),
* NuttX has successfully booted and is, apparently, running normally and taking
* interrupts. If any of LEDs A-D are statically set, then NuttX failed to boot

16
configs/flipnclick-sam3x/src/flipnclick-sam3x.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __CONFIGS_FLIPNCLICK_SAM3X_SRC_ARDUNO_DUE_H
#define __CONFIGS_FLIPNCLICK_SAM3X_SRC_ARDUNO_DUE_H
#ifndef __CONFIGS_FLIPNCLICK_SAM3X_SRC_FLIPNCLICK_SAM3X_H
#define __CONFIGS_FLIPNCLICK_SAM3X_SRC_FLIPNCLICK_SAM3X_H
/************************************************************************************
* Included Files
@ -68,15 +68,15 @@
* A high output value illuminates the LEDs.
*/
#define GPIO_LED_L (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \
#define GPIO_LED_L (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
GPIO_PORT_PIOB | GPIO_PIN27)
#define GPIO_LED_A (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \
#define GPIO_LED_A (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
GPIO_PORT_PIOC | GPIO_PIN6)
#define GPIO_LED_B (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \
#define GPIO_LED_B (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
GPIO_PORT_PIOC | GPIO_PIN5)
#define GPIO_LED_C (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \
#define GPIO_LED_C (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
GPIO_PORT_PIOC | GPIO_PIN7)
#define GPIO_LED_D (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \
#define GPIO_LED_D (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
GPIO_PORT_PIOC | GPIO_PIN8)
/* SPI chip select pins.
@ -159,5 +159,5 @@
int sam_bringup(void);
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_FLIPNCLICK_SAM3X_SRC_ARDUNO_DUE_H */
#endif /* __CONFIGS_FLIPNCLICK_SAM3X_SRC_FLIPNCLICK_SAM3X_H */

10
configs/flipnclick-sam3x/src/sam_autoleds.c
View File

@ -64,8 +64,8 @@
* LED_PANIC The system has crashed 2Hz N/C N/C N/C N/C
* LED_IDLE MCU is is sleep mode ---- Not used -----
*
* Thus if LED L is glowing on and all other LEDs are off (except LED D
* which was left on but is no longer controlled by NuttX and so may be in
* Thus if LED L is faintly glowing and all other LEDs are off (except LED
* D which was left on but is no longer controlled by NuttX and so may be in
* any state), NuttX has successfully booted and is, apparently, running
* normally and taking interrupts. If any of LEDs A-D are statically set,
* then NuttX failed to boot and the LED indicates the initialization phase
@ -99,7 +99,7 @@
#ifdef CONFIG_ARCH_LEDS
/****************************************************************************
* Processor Definitinos
* Processor Definitions
****************************************************************************/
/* LED indices */
@ -123,7 +123,7 @@ static void board_autoled_setone(int ledndx)
sam_gpiowrite(GPIO_LED_L, ledon[INDEX_LED_L]);
sam_gpiowrite(GPIO_LED_A, ledon[INDEX_LED_A]);
sam_gpiowrite(GPIO_LED_B, ledon[INDEX_LED_B]);
sam_gpiowrite(GPIO_LED_C, ledon[INDEX_LED_D]);
sam_gpiowrite(GPIO_LED_C, ledon[INDEX_LED_C]);
sam_gpiowrite(GPIO_LED_D, ledon[INDEX_LED_D]);
}
@ -176,7 +176,7 @@ void board_autoled_on(int led)
board_autoled_setone(INDEX_LED_B);
break;
case 2:
case 2:
board_autoled_setone(INDEX_LED_C);
break;

26
configs/stm32f334-disco/src/stm32_smps.c
View File

@ -748,7 +748,6 @@ static void smps_duty_set(struct smps_priv_s *priv, struct smps_lower_dev_s *low
{
per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA);
if (out < priv->v_in) out = priv->v_in;
if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX;
@ -767,9 +766,24 @@ static void smps_duty_set(struct smps_priv_s *priv, struct smps_lower_dev_s *low
case CONVERTER_MODE_BUCKBOOST:
{
/* do something */
/* Buck converter is set to fixed duty cycle (80%).
* Now we need set boost converter
*/
#warning TODO: buck boost mode
per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA);
if (out < priv->v_in) out = priv->v_in;
if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX;
duty = 1.0 - priv->v_in/out;
#warning TODO: current limit in buck boost mode
cmp = (uint16_t)(per * duty);
/* Set T12 duty cycle. T5 is complementary to T12 */
HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMB, HRTIM_CMP1, cmp);
break;
}
@ -857,6 +871,12 @@ static void smps_conv_mode_set(struct smps_priv_s *priv, struct smps_lower_dev_s
HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_SET_PER);
HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_RST_CMP1);
/* Set fixed duty cycle (80%) on buck converter (T4 and T11) */
HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP1,
0.8 * ((uint16_t)HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA)));
break;
}

4
sched/irq/irq_csection.c
View File

@ -99,7 +99,7 @@ volatile uint8_t g_cpu_nestcount[CONFIG_SMP_NCPUS];
* spinlock.
* - Another task on CPUm attempts to enter the critical section but has
* to wait, spinning to get g_cpu_irqlock with interrupts disabled.
* - The task on CPUn causes a new task to become ready-torun and the
* - The task on CPUn causes a new task to become ready-to-run and the
* scheduler selects CPUm. CPUm is requested to pause via a pause
* interrupt.
* - But the task on CPUm is also attempting to enter the critical
@ -641,7 +641,7 @@ bool irq_cpu_locked(int cpu)
{
/* In this case g_cpu_irqlock should be unlocked. However, if
* the lock was established in the interrupt handler AND there are
* no bits set in g_cpu_irqset, that probabaly means only that
* no bits set in g_cpu_irqset, that probably means only that
* critical section was established from an interrupt handler.
* Return false in either case.
*/

2
sched/module/mod_procfs.c
View File

@ -286,7 +286,7 @@ static int modprocfs_dup(FAR const struct file *oldp, FAR struct file *newp)
return -ENOMEM;
}
/* The copy the file attribtes from the old attributes to the new */
/* The copy the file attributes from the old attributes to the new */
memcpy(newpriv, oldpriv, sizeof(struct modprocfs_file_s));

4
sched/sched/sched_addreadytorun.c
View File

@ -141,7 +141,7 @@ bool sched_addreadytorun(FAR struct tcb_s *btcb)
*
* If the currently active task has preemption disabled and the new TCB
* would cause this task to be pre-empted, the new task is added to the
* g_pendingtasks list instead. Thepending tasks will be made
* g_pendingtasks list instead. The pending tasks will be made
* ready-to-run when preemption isunlocked.
*
* Inputs:
@ -405,7 +405,7 @@ bool sched_addreadytorun(FAR struct tcb_s *btcb)
/* No context switch. Assign the CPU and set the assigned state.
*
* REVISIT: I have seen this assertion fire. Apparently another
* CPU may add another, higher prioirity task to the same
* CPU may add another, higher priority task to the same
* g_assignedtasks[] list sometime after sched_cpu_select() was
* called above, leaving this TCB in the wrong task list if task_state
* is TSTATE_TASK_ASSIGNED).

3
sched/task/task_posixspawn.c
View File

@ -351,7 +351,8 @@ int posix_spawn(FAR pid_t *pid, FAR const char *path,
pid, path, file_actions, attr, argv);
/* If there are no file actions to be performed and there is no change to
* the signal mask, then start the new child task directly from the parent task.
* the signal mask, then start the new child task directly from the parent
* task.
*/
#ifndef CONFIG_DISABLE_SIGNALS

30
sched/task/task_setup.c
View File

@ -57,6 +57,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* This is an artificial limit to detect error conditions where an argv[]
* list is not properly terminated.
*/
@ -445,8 +446,8 @@ static int thread_schedsetup(FAR struct tcb_s *tcb, int priority,
* Assign the task name.
*
* Input Parameters:
* tcb - Address of the new task's TCB
* name - Name of the new task
* tcb - Address of the new task's TCB
* name - Name of the new task
*
* Return Value:
* None
@ -657,11 +658,11 @@ int task_schedsetup(FAR struct task_tcb_s *tcb, int priority, start_t start,
* pthread_schedsetup() is called from pthread_create(),
*
* Input Parameters:
* tcb - Address of the new task's TCB
* priority - Priority of the new task
* start - Start-up function (probably pthread_start())
* entry - Entry point of the new pthread
* ttype - Type of the new thread: task, pthread, or kernel thread
* tcb - Address of the new task's TCB
* priority - Priority of the new task
* start - Start-up function (probably pthread_start())
* entry - Entry point of the new pthread
* ttype - Type of the new thread: task, pthread, or kernel thread
*
* Return Value:
* OK on success; ERROR on failure.
@ -700,14 +701,13 @@ int pthread_schedsetup(FAR struct pthread_tcb_s *tcb, int priority,
* task runs in.
*
* Input Parameters:
* tcb - Address of the new task's TCB
* name - Name of the new task (not used)
* argv - A pointer to an array of input parameters.
* Up to CONFIG_MAX_TASK_ARG parameters may be
* provided. If fewer than CONFIG_MAX_TASK_ARG
* parameters are passed, the list should be
* terminated with a NULL argv[] value.
* If no parameters are required, argv may be NULL.
* tcb - Address of the new task's TCB
* name - Name of the new task (not used)
* argv - A pointer to an array of input parameters. Up to
* CONFIG_MAX_TASK_ARG parameters may be provided. If fewer than
* CONFIG_MAX_TASK_ARG parameters are passed, the list should be
* terminated with a NULL argv[] value. If no parameters are
* required, argv may be NULL.
*
* Return Value:
* OK

1
sched/task/task_vfork.c
View File

@ -57,6 +57,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* vfork() requires architecture-specific support as well as waipid(). */
#if defined(CONFIG_ARCH_HAVE_VFORK) && defined(CONFIG_SCHED_WAITPID)