Merged in raiden00/nuttx (pull request #407)
stm32_hrtim Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni
Gregory Nutt
commit
623d8a4337
@ -132,79 +132,6 @@
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#define STM32_HRTIM_CMN_BDTEUPR_OFFSET 0x006C /* HRTIM Timer E Update Register */
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#define STM32_HRTIM_CMN_BDMADR_OFFSET 0x0070 /* HRTIM DMA Data Register */
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/* Register Addresses *******************************************************************************/
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/* HRTIM1 Timer A */
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/* remove ? */
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#define STM32_HRTIM1_TIMERA_CR (STM32_HRTIM_TIM_CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_ISR (STM32_HRTIM_TIM_ISR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_ICR (STM32_HRTIM_TIM_ICR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_DIER (STM32_HRTIM_TIM_DIER_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_CNTR (STM32_HRTIM_TIM_CNTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_PER (STM32_HRTIM_TIM_PER_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_REP (STM32_HRTIM_TIM_REP_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_CMP1R (STM32_HRTIM_TIM_CMP1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_CMP1CR (STM32_HRTIM_TIM_CMP1CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_CMP2R (STM32_HRTIM_TIM_CMP2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_CMP3R (STM32_HRTIM_TIM_CMP3R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_CMP4R (STM32_HRTIM_TIM_CMP4R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_CPT1R (STM32_HRTIM_TIM_CMPT1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_CPT2R (STM32_HRTIM_TIM_CMPT2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_DTR (STM32_HRTIM_TIM_DTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_SET1R (STM32_HRTIM_TIM_SET1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_RST1R (STM32_HRTIM_TIM_RST1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_SET2R (STM32_HRTIM_TIM_SET2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_RST2R (STM32_HRTIM_TIM_RST2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_EEFR1 (STM32_HRTIM_TIM_EEFR1_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_EEFR2 (STM32_HRTIM_TIM_EEFR2_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_RSTR (STM32_HRTIM_TIM_RSTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_CHPR (STM32_HRTIM_TIM_CHPR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_CPT1CR (STM32_HRTIM_TIM_CPT1CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_CPT2CR (STM32_HRTIM_TIM_CPT2CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_OUTR (STM32_HRTIM_TIM_OUTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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#define STM32_HRTIM1_TIMERA_FLTR (STM32_HRTIM_TIM_FLTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
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/* HRTIM1 Timer B */
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/* HRTIM1 Timer C */
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/* HRTIM1 Timer D */
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/* HRTIM1 Timer E */
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/* HRTIM1 Common Registers */
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#define STM32_HRTIM_CMN_CR1 (STM32_HRTIM_CMN_CR1_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_CR2 (STM32_HRTIM_CMN_CR2_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_ISR (STM32_HRTIM_CMN_ISR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_ICR (STM32_HRTIM_CMN_ICR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_IER (STM32_HRTIM_CMN_IER_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_OENR (STM32_HRTIM_CMN_OENR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_DISR (STM32_HRTIM_CMN_DISR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_ODSR (STM32_HRTIM_CMN_ODSR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_BMCR (STM32_HRTIM_CMN_BMCR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_BMTGR (STM32_HRTIM_CMN_BMTGR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_BMCMPR (STM32_HRTIM_CMN_MBCMPR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_BMPER (STM32_HRTIM_CMN_BMPER_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_EECR1 (STM32_HRTIM_CMN_EECR1_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_EECR2 (STM32_HRTIM_CMN_EECR2_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_EECR3 (STM32_HRTIM_CMN_EECR3_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_ADC1R (STM32_HRTIM_CMN_ADC1R_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_ADC2R (STM32_HRTIM_CMN_ADC2R_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_ADC3R (STM32_HRTIM_CMN_ADC3R_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_ADC4R (STM32_HRTIM_CMN_ADC4R_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_DLLCR (STM32_HRTIM_CMN_DLLCR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_FLTINR1 (STM32_HRTIM_CMN_FTLINR1_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_FLTINR2 (STM32_HRTIM_CMN_FLTINR2_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_BDMUPDR (STM32_HRTIM_CMN_BDMUPDR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_BDTAUPR (STM32_HRTIM_CMN_BDTAUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_BDTBUPR (STM32_HRTIM_CMN_BDTBUR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_BDTCUPR (STM32_HRTIM_CMN_BDTCUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_BDTDUPR (STM32_HRTIM_CMN_BDTDUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_BDTEUPR (STM32_HRTIM_CMN_BDTEUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
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#define STM32_HRTIM_CMN_BDMADR (STM32_HRTIM_CMN_BDMADR_OFFSET+STM32_HRTIM1_CMN_BASE)
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/* Register Bitfield Definitions ****************************************************/
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/* Control Register Bits Common to Master Timer and Timer A-E */
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File diff suppressed because it is too large
Load Diff
@ -56,6 +56,66 @@
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* Pre-processor definitions
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************************************************************************************/
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#if defined(CONFIG_STM32_HRTIM_TIMA) || defined(CONFIG_STM32_HRTIM_TIMB) || \
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defined(CONFIG_STM32_HRTIM_TIMC) || defined(CONFIG_STM32_HRTIM_TIMD) || \
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defined(CONFIG_STM32_HRTIM_TIME)
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# define HRTIM_HAVE_SLAVE 1
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#endif
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#if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_PWM) || \
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defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_PWM) || \
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defined(CONFIG_STM32_HRTIM_TIME_PWM)
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# define HRTIM_HAVE_PWM 1
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#endif
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#if defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_CAP) || \
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defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_CAP) || \
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defined(CONFIG_STM32_HRTIM_TIME_CAP)
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# define HRTIM_HAVE_CAPTURE 1
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#endif
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#if defined(CONFIG_STM32_HRTIM_TIMA_DT) || defined(CONFIG_STM32_HRTIM_TIMB_DT) || \
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defined(CONFIG_STM32_HRTIM_TIMC_DT) || defined(CONFIG_STM32_HRTIM_TIMD_DT) || \
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defined(CONFIG_STM32_HRTIM_TIME_DT)
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# define HRTIM_HAVE_DEADTIME 1
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#endif
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#if defined(CONFIG_STM32_HRTIM_TIMA_CHOP) || defined(CONFIG_STM32_HRTIM_TIMB_CHOP) || \
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defined(CONFIG_STM32_HRTIM_TIMC_CHOP) || defined(CONFIG_STM32_HRTIM_TIMD_CHOP) || \
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defined(CONFIG_STM32_HRTIM_TIME_CHOP)
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# define HRTIM_HAVE_CHOPPER 1
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#endif
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#if defined(CONFIG_STM32_HRTIM_SCOUT) || defined(CONFIG_STM32_HRTIM_SCIN)
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# define HRTIM_HAVE_SYNC 1
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#endif
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#if defined(CONFIG_STM32_HRTIM_FAULT1) || defined(CONFIG_STM32_HRTIM_FAULT2) || \
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defined(CONFIG_STM32_HRTIM_FAULT3) || defined(CONFIG_STM32_HRTIM_FAULT4) || \
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defined(CONFIG_STM32_HRTIM_FAULT5)
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# define HRTIM_HAVE_FAULTS 1
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#endif
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#if defined(CONFIG_STM32_HRTIM_EEV1) || defined(CONFIG_STM32_HRTIM_EEV2) || \
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defined(CONFIG_STM32_HRTIM_EEV3) || defined(CONFIG_STM32_HRTIM_EEV4) || \
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defined(CONFIG_STM32_HRTIM_EEV5) || defined(CONFIG_STM32_HRTIM_EEV6) || \
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defined(CONFIG_STM32_HRTIM_EEV7) || defined(CONFIG_STM32_HRTIM_EEV8) || \
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defined(CONFIG_STM32_HRTIM_EEV9) || defined(CONFIG_STM32_HRTIM_EEV10)
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# define HRTIM_HAVE_EEV 1
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#endif
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#if defined(CONFIG_STM32_HRTIM_MASTER_IRQ) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || \
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defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || \
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defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) || \
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defined(CONFIG_STM32_HRTIM_CMN_IRQ)
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# defined HRTIM_HAVE_INTERRUPTS
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#endif
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#if defined(CONFIG_STM32_HRTIM_ADC_TRG1) || defined(CONFIG_STM32_HRTIM_ADC_TRG2) || \
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defined(CONFIG_STM32_HRTIM_ADC_TRG3) || defined(CONFIG_STM32_HRTIM_ADC_TRG4)
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# define HRTIM_HAVE_ADC
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#endif
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/************************************************************************************
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* Public Types
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************************************************************************************/
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@ -223,6 +283,39 @@ enum stm32_hrtim_tim_prescaler_e
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HRTIM_PRESCALER_128
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};
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/* HRTIM Timer Master/Slave mode */
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enum stm32_hrtim_mode_e
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{
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HRTIM_MODE_PRELOAD = (1 << 0), /* Preload enable */
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HRTIM_MODE_HALF = (1 << 1), /* Half mode */
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HRTIM_MODE_RETRIG = (1 << 2), /* Re-triggerable mode */
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HRTIM_MODE_CONT = (1 << 3), /* Continuous mode */
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/* Only slave Timers */
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HRTIM_MODE_PSHPLL = (1 << 7), /* Push-Pull mode */
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};
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/* HRTIM Slave Timer auto-delayed mode
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* NOTE: details in STM32F334 Manual
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*/
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enum stm32_hrtim_autodelayed_e
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{
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/* CMP2 auto-delayed mode */
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HRTIM_AUTODELAYED_CMP2_MODE1 = 1, /* DELCMP2 = 01 */
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HRTIM_AUTODELAYED_CMP2_MODE2 = 2, /* DELCMP2 = 10 */
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HRTIM_AUTODELAYED_CMP2_MODE3 = 3, /* DELCMP2 = 11 */
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/* CMP4 auto-delayed mode */
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HRTIM_AUTODELAYED_CMP4_MODE1 = (1 << 2), /* DELCMP4 = 01 */
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HRTIM_AUTODELAYED_CMP4_MODE2 = (2 << 2), /* DELCMP4 = 10 */
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HRTIM_AUTODELAYED_CMP4_MODE3 = (3 << 2), /* DELCMP4 = 11 */
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};
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/* HRTIM Slave Timer fault sources Lock */
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enum stm32_hrtim_tim_fault_lock_e
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@ -371,7 +464,7 @@ enum stm32_hrtim_dacsync_e
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/* HRTIM Deadtime Locks */
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enum stm32_deadtime_lock_e
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enum stm32_hrtim_deadtime_lock_e
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{
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HRTIM_DT_VALUE_LOCK = (1 << 0), /* Lock Deadtime value */
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HRTIM_DT_SIGN_LOCK = (1 << 1) /* Lock Deadtime sign */
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@ -379,7 +472,7 @@ enum stm32_deadtime_lock_e
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/* HRTIM Deadtime types */
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enum stm32_deadtime_edge_e
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enum stm32_hrtim_deadtime_edge_e
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{
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HRTIM_DT_RISING = 0,
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HRTIM_DT_FALLING = 1
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@ -387,7 +480,7 @@ enum stm32_deadtime_edge_e
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/* Chopper start pulsewidth */
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enum stm32_chopper_start_e
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enum stm32_hrtim_chopper_start_e
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{
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HRTIM_CHP_START_16,
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HRTIM_CHP_START_32,
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@ -408,7 +501,7 @@ enum stm32_chopper_start_e
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/* Chopper duty cycle */
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enum stm32_chopper_duty_e
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enum stm32_hrtim_chopper_duty_e
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{
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HRTIM_CHP_DUTY_0,
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HRTIM_CHP_DUTY_1,
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@ -422,7 +515,7 @@ enum stm32_chopper_duty_e
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/* Chopper carrier frequency */
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enum stm32_chopper_freq_e
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enum stm32_hrtim_chopper_freq_e
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{
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HRTIM_CHP_FREQ_d16,
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HRTIM_CHP_FREQ_d32,
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@ -442,7 +535,172 @@ enum stm32_chopper_freq_e
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HRTIM_CHP_FREQ_d256
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};
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/* */
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/* HRTIM ADC Trigger 1/3 */
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enum stm32_hrtim_adc_trq13_e
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{
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HRTIM_ADCTRG13_MC1 = (1 << 0),
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HRTIM_ADCTRG13_MC2 = (1 << 1),
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HRTIM_ADCTRG13_MC3 = (1 << 2),
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HRTIM_ADCTRG13_MC4 = (1 << 3),
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HRTIM_ADCTRG13_MPER = (1 << 4),
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HRTIM_ADCTRG13_EEV1 = (1 << 5),
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HRTIM_ADCTRG13_EEV2 = (1 << 6),
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HRTIM_ADCTRG13_EEV3 = (1 << 7),
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HRTIM_ADCTRG13_EEV4 = (1 << 8),
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HRTIM_ADCTRG13_EEV5 = (1 << 9),
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HRTIM_ADCTRG13_AC2 = (1 << 10),
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HRTIM_ADCTRG13_AC3 = (1 << 11),
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HRTIM_ADCTRG13_AC4 = (1 << 12),
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HRTIM_ADCTRG13_APER = (1 << 13),
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HRTIM_ADCTRG13_ARST = (1 << 14),
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HRTIM_ADCTRG13_BC2 = (1 << 15),
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HRTIM_ADCTRG13_BC3 = (1 << 16),
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HRTIM_ADCTRG13_BC4 = (1 << 17),
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HRTIM_ADCTRG13_BPER = (1 << 18),
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HRTIM_ADCTRG13_BRST = (1 << 19),
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HRTIM_ADCTRG13_CC2 = (1 << 20),
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HRTIM_ADCTRG13_CC3 = (1 << 21),
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HRTIM_ADCTRG13_CC4 = (1 << 22),
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HRTIM_ADCTRG13_CPER = (1 << 23),
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HRTIM_ADCTRG13_DC2 = (1 << 24),
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HRTIM_ADCTRG13_DC3 = (1 << 25),
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HRTIM_ADCTRG13_DC4 = (1 << 26),
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HRTIM_ADCTRG13_DPER = (1 << 27),
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HRTIM_ADCTRG13_EC2 = (1 << 28),
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HRTIM_ADCTRG13_EC3 = (1 << 29),
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HRTIM_ADCTRG13_EC4 = (1 << 30),
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HRTIM_ADCTRG13_ERST = (1 << 31),
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};
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/* HRTIM ADC Trigger 2/4 */
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enum stm32_hrtim_adc_trq24_e
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{
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HRTIM_ADCTRG24_MC1 = (1 << 0),
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HRTIM_ADCTRG24_MC2 = (1 << 1),
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HRTIM_ADCTRG24_MC3 = (1 << 2),
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HRTIM_ADCTRG24_MC4 = (1 << 3),
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HRTIM_ADCTRG24_MPER = (1 << 4),
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HRTIM_ADCTRG24_EEV6 = (1 << 5),
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HRTIM_ADCTRG24_EEV7 = (1 << 6),
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HRTIM_ADCTRG24_EEV8 = (1 << 7),
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HRTIM_ADCTRG24_EEV9 = (1 << 8),
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HRTIM_ADCTRG24_EEV10 = (1 << 9),
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HRTIM_ADCTRG24_AC2 = (1 << 10),
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HRTIM_ADCTRG24_AC3 = (1 << 11),
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HRTIM_ADCTRG24_AC4 = (1 << 12),
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||||
HRTIM_ADCTRG24_APER = (1 << 13),
|
||||
|
||||
HRTIM_ADCTRG24_BC2 = (1 << 14),
|
||||
HRTIM_ADCTRG24_BC3 = (1 << 15),
|
||||
HRTIM_ADCTRG24_BC4 = (1 << 16),
|
||||
HRTIM_ADCTRG24_BPER = (1 << 17),
|
||||
|
||||
HRTIM_ADCTRG24_CC2 = (1 << 18),
|
||||
HRTIM_ADCTRG24_CC3 = (1 << 19),
|
||||
HRTIM_ADCTRG24_CC4 = (1 << 20),
|
||||
HRTIM_ADCTRG24_CPER = (1 << 21),
|
||||
HRTIM_ADCTRG24_CRST = (1 << 22),
|
||||
|
||||
HRTIM_ADCTRG24_DC2 = (1 << 23),
|
||||
HRTIM_ADCTRG24_DC3 = (1 << 24),
|
||||
HRTIM_ADCTRG24_DC4 = (1 << 25),
|
||||
HRTIM_ADCTRG24_DPER = (1 << 26),
|
||||
HRTIM_ADCTRG24_DRST = (1 << 27),
|
||||
|
||||
HRTIM_ADCTRG24_EC2 = (1 << 28),
|
||||
HRTIM_ADCTRG24_EC3 = (1 << 29),
|
||||
HRTIM_ADCTRG24_EC4 = (1 << 30),
|
||||
HRTIM_ADCTRG24_ERST = (1 << 31),
|
||||
};
|
||||
|
||||
/* HRTIM DAC synchronization */
|
||||
|
||||
enum stm32_hrtim_dac_e
|
||||
{
|
||||
HRTIM_DAC_SYNC_DIS = 0,
|
||||
HRTIM_DAC_SYNC_1 = 1,
|
||||
HRTIM_DAC_SYNC_2 = 2,
|
||||
HRTIM_DAC_SYNC_3 = 3
|
||||
};
|
||||
|
||||
/* HRTIM Master Timer interrupts */
|
||||
|
||||
enum stm32_irq_master_e
|
||||
{
|
||||
HRTIM_IRQ_MCMP1 = (1 << 0), /* Master Compare 1 Interrupt */
|
||||
HRTIM_IRQ_MCMP2 = (1 << 1), /* Master Compare 2 Interrupt */
|
||||
HRTIM_IRQ_MCMP3 = (1 << 2), /* Master Compare 3 Interrupt */
|
||||
HRTIM_IRQ_MCMP4 = (1 << 3), /* Master Compare 4 Interrupt */
|
||||
HRTIM_IRQ_MREP = (1 << 4), /* Master Repetition Interrupt */
|
||||
HRTIM_IRQ_MSYNC = (1 << 5), /* Sync Input Interrupt */
|
||||
HRTIM_IRQ_MUPD = (1 << 6) /* Master Update Interrupt */
|
||||
};
|
||||
|
||||
/* HRTIM Slave Timer interrupts */
|
||||
|
||||
enum stm32_irq_slave_e
|
||||
{
|
||||
HRTIM_IRQ_CMP1 = (1 << 0), /* Slave Compare 1 Interrupt */
|
||||
HRTIM_IRQ_CMP2 = (1 << 1), /* Slave Compare 2 Interrupt */
|
||||
HRTIM_IRQ_CMP3 = (1 << 2), /* Slave Compare 3 Interrupt */
|
||||
HRTIM_IRQ_CMP4 = (1 << 3), /* Slave Compare 4 Interrupt */
|
||||
HRTIM_IRQ_REP = (1 << 4), /* Slave Repetition Interrupt */
|
||||
HRTIM_IRQ_UPD = (1 << 6), /* Slave Update Interrupt */
|
||||
HRTIM_IRQ_CPT1 = (1 << 7), /* Slave Capture 1 Interrupt */
|
||||
HRTIM_IRQ_CPT2 = (1 << 8), /* Slave Capture 2 Interrupt */
|
||||
HRTIM_IRQ_SETX1 = (1 << 9), /* Slave Output 1 Set Interrupt */
|
||||
HRTIM_IRQ_RSTX1 = (1 << 10), /* Slave Output 1 Reset Interrupt */
|
||||
HRTIM_IRQ_SETX2 = (1 << 11), /* Slave Output 2 Set Interrupt */
|
||||
HRTIM_IRQ_RSTX2 = (1 << 12), /* Slave Output 2 Reset Interrupt */
|
||||
HRTIM_IRQ_RST = (1 << 13), /* Slave Reset/roll-over Interrupt */
|
||||
HRTIM_IRQ_DLYPRT = (1 << 14) /* Slave Delayed Protection Interrupt */
|
||||
};
|
||||
|
||||
/* HRTIM Common Interrupts */
|
||||
|
||||
enum stm32_irq_cmn_e
|
||||
{
|
||||
HRTIM_IRQ_FLT1 = (1 << 0), /* Fault 1 Interrupt */
|
||||
HRTIM_IRQ_FLT2 = (1 << 1), /* Fault 2 Interrupt */
|
||||
HRTIM_IRQ_FLT3 = (1 << 2), /* Fault 3 Interrupt */
|
||||
HRTIM_IRQ_FLT4 = (1 << 3), /* Fault 4 Interrupt */
|
||||
HRTIM_IRQ_FLT5 = (1 << 4), /* Fault 5 Interrupt */
|
||||
HRTIM_IRQ_SYSFLT = (1 << 5), /* System Fault Interrupt */
|
||||
HRTIM_IRQ_DLLRDY = (1 << 16), /* DLL Ready Interrupt */
|
||||
HRTIM_IRQ_BMPER = (1 << 17) /* Burst Mode Period Interrupt */
|
||||
};
|
||||
|
||||
/* HRTIM vtable */
|
||||
|
||||
struct hrtim_dev_s;
|
||||
struct stm32_hrtim_ops_s
|
||||
{
|
||||
int (*cmp_update)(FAR struct hrtim_dev_s *dev, uint8_t timer,
|
||||
uint8_t index, uint16_t cmp);
|
||||
int (*per_update)(FAR struct hrtim_dev_s *dev, uint8_t timer, uint16_t per);
|
||||
uint16_t (*per_get)(FAR struct hrtim_dev_s *dev, uint8_t timer);
|
||||
uint16_t (*cmp_get)(FAR struct hrtim_dev_s *dev, uint8_t timer,
|
||||
uint8_t index);
|
||||
#ifdef HRTIM_HAVE_INTERRUPTS
|
||||
void (*irq_ack)(FAR struct hrtim_dev_s *dev, uint8_t timer, int source);
|
||||
#endif
|
||||
#ifdef HRTIM_HAVE_PWM
|
||||
int (*outputs_enable)(FAR struct hrtim_dev_s *dev, uint16_t outputs,
|
||||
bool state);
|
||||
#endif
|
||||
};
|
||||
|
||||
/* HRTIM device structure */
|
||||
|
||||
struct hrtim_dev_s
|
||||
{
|
||||
@ -455,8 +713,9 @@ struct hrtim_dev_s
|
||||
|
||||
/* Fields provided by lower half HRTIM logic */
|
||||
|
||||
FAR void *hd_priv; /* Used by the arch-specific logic */
|
||||
bool initialized; /* true: HRTIM driver has been initialized */
|
||||
FAR const struct stm32_hrtim_ops_s *hd_ops; /* HRTIM operations */
|
||||
FAR void *hd_priv; /* Used by the arch-specific logic */
|
||||
bool initialized; /* true: HRTIM driver has been initialized */
|
||||
};
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
Loading…
Reference in New Issue
Block a user