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Merged in paulpatience/nuttx-boards (pull request #7)

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Fix typo
This commit is contained in:
Gregory Nutt 2015-09-11 08:03:37 -06:00
commit 62447003a6
12 changed files with 12 additions and 12 deletions
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2
configs/fire-stm32v2/src/stm32_selectlcd.c
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@ -193,7 +193,7 @@ void stm32_selectlcd(void)
/* Bank1 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTRUN(0)|
putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTURN(0)|
FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR1);
putreg32(0xffffffff, STM32_FSMC_BWTR4);

2
configs/hymini-stm32v/src/stm32_r61505u.c
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@ -353,7 +353,7 @@ static void stm32_selectlcd(void)
/* Bank1 NOR/SRAM timing register configuration */
putreg32(
FSMC_BTR_ADDSET(2)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTRUN(0)|
FSMC_BTR_ADDSET(2)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTURN(0)|
FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA,
STM32_FSMC_BTR1);

2
configs/hymini-stm32v/src/stm32_ssd1289.c
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@ -406,7 +406,7 @@ static void stm32_selectlcd(void)
/* Bank1 NOR/SRAM timing register configuration */
putreg32(
FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTRUN(0)| FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA,
FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTURN(0)| FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA,
STM32_FSMC_BTR1);
/* As ext mode is not active the write timing is ignored!! */

2
configs/stm3210e-eval/src/stm32_selectlcd.c
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@ -130,7 +130,7 @@ void stm32_selectlcd(void)
/* Bank4 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTRUN(0)|
putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTURN(0)|
FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR4);
putreg32(0xffffffff, STM32_FSMC_BWTR4);

2
configs/stm3210e-eval/src/stm32_selectnor.c
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@ -127,7 +127,7 @@ void stm32_selectnor(void)
/* Bank1 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(3)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(6)|FSMC_BTR_BUSTRUN(1)|
putreg32(FSMC_BTR_ADDSET(3)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(6)|FSMC_BTR_BUSTURN(1)|
FSMC_BTR_CLKDIV(1)|FSMC_BTR_DATLAT(2)|FSMC_BTR_ACCMODB, STM32_FSMC_BTR2);
putreg32(0x0fffffff, STM32_FSMC_BWTR2);

2
configs/stm3210e-eval/src/stm32_selectsram.c
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@ -130,7 +130,7 @@ void stm32_selectsram(void)
/* Bank1 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(3)|FSMC_BTR_BUSTRUN(1)|
putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(3)|FSMC_BTR_BUSTURN(1)|
FSMC_BTR_CLKDIV(1)|FSMC_BTR_DATLAT(2)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR3);
putreg32(0xffffffff, STM32_FSMC_BWTR3);

2
configs/stm3220g-eval/src/stm32_selectlcd.c
View File

@ -153,7 +153,7 @@ void stm32_selectlcd(void)
/* Bank3 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTRUN(0) |
putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) |
FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_ACCMODA, STM32_FSMC_BTR3);
putreg32(0xffffffff, STM32_FSMC_BWTR3);

2
configs/stm3220g-eval/src/stm32_selectsram.c
View File

@ -174,7 +174,7 @@ void stm32_selectsram(void)
/* Bank1 NOR/SRAM timing register configuration */
putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) |
FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | FSMC_BTR_BUSTRUN(SRAM_BUS_TURNAROUND_DURATION) |
FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) |
FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) |
FSMC_BTR_ACCMODA),
STM32_FSMC_BTR2);

2
configs/stm3240g-eval/src/stm32_selectlcd.c
View File

@ -153,7 +153,7 @@ void stm32_selectlcd(void)
/* Bank3 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTRUN(0) |
putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) |
FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_ACCMODA, STM32_FSMC_BTR3);
putreg32(0xffffffff, STM32_FSMC_BWTR3);

2
configs/stm3240g-eval/src/stm32_selectsram.c
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@ -174,7 +174,7 @@ void stm32_selectsram(void)
/* Bank1 NOR/SRAM timing register configuration */
putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) |
FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | FSMC_BTR_BUSTRUN(SRAM_BUS_TURNAROUND_DURATION) |
FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) |
FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) |
FSMC_BTR_ACCMODA),
STM32_FSMC_BTR2);

2
configs/stm32f4discovery/src/stm32_ssd1289.c
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@ -325,7 +325,7 @@ void stm32_selectlcd(void)
/* Bank1 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTRUN(0) |
putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) |
FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_ACCMODA, STM32_FSMC_BTR1);
putreg32(0xffffffff, STM32_FSMC_BWTR1);

2
configs/viewtool-stm32f107/src/stm32_ssd1289.c
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@ -472,7 +472,7 @@ static void stm32_selectlcd(void)
/* Bank1 NOR/SRAM timing register configuration */
putreg32(
FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTRUN(0)| FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA,
FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTURN(0)| FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA,
STM32_FSMC_BTR1);
/* As ext mode is not active the write timing is ignored!! */