Tiva Timer: Add functions to set match registers; Add logic to select count direction
This commit is contained in:
Gregory Nutt
parent
8552b2f679
commit
626d6cdab4
@ -479,33 +479,33 @@
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/* GPTM Timer A/B Mode (TAMR and TBMR) */
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#define TIMER_TnMR_TnMR_SHIFT 0 /* Bits 1-0: Timer A Mode */
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#define TIMER_TnMR_TnMR_SHIFT 0 /* Bits 1-0: Timer A/B Mode */
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#define TIMER_TnMR_TnMR_MASK (3 << TIMER_TnMR_TnMR_SHIFT)
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# define TIMER_TnMR_TnMR_ONESHOT (1 << TIMER_TnMR_TnMR_SHIFT) /* One-Shot Timer mode */
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# define TIMER_TnMR_TnMR_PERIODIC (2 << TIMER_TnMR_TnMR_SHIFT) /* Periodic Timer mode */
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# define TIMER_TnMR_TnMR_CAPTURE (3 << TIMER_TnMR_TnMR_SHIFT) /* Capture mode */
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#define TIMER_TnMR_TACMR (1 << 2) /* Bit 2: Timer A Capture Mode */
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# define TIMER_TnMR_TACMR_EDGECOUNT (0 << TIMER_TnMR_TACMR_SHIFT) /* Edge-Count mode */
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# define TIMER_TnMR_TACMR_EDGETIME (1 << TIMER_TnMR_TACMR_SHIFT) /* Edge-Time mode */
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#define TIMER_TnMR_TAAMS (1 << 3) /* Bit 3: Timer A Alternate Mode Select */
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# define TIMER_TnMR_TAAMS_CAPTURE (0 << TIMER_TnMR_TAAMS_SHIFT) /* Capture mode is enabled */
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# define TIMER_TnMR_TAAMS_PWM (1 << TIMER_TnMR_TAAMS_SHIFT) /* PWM mode is enabled */
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#define TIMER_TnMR_TnCMR (1 << 2) /* Bit 2: Timer A/B Capture Mode */
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# define TIMER_TnMR_TnCMR_EDGECOUNT (0 << TIMER_TnMR_TnCMR_SHIFT) /* Edge-Count mode */
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# define TIMER_TnMR_TnCMR_EDGETIME (1 << TIMER_TnMR_TnCMR_SHIFT) /* Edge-Time mode */
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#define TIMER_TnMR_TnAMS (1 << 3) /* Bit 3: Timer A/B Alternate Mode Select */
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# define TIMER_TnMR_TnAMS_CAPTURE (0 << TIMER_TnMR_TnAMS_SHIFT) /* Capture mode is enabled */
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# define TIMER_TnMR_TnAMS_PWM (1 << TIMER_TnMR_TnAMS_SHIFT) /* PWM mode is enabled */
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_TnMR_TACDIR (1 << 4) /* Bit 4: Timer A Count Direction */
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# define TIMER_TnMR_TACDIR_DOWN (0 << TIMER_TnMR_TACDIR_SHIFT) /* The timer counts down */
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# define TIMER_TnMR_TACDIR_UP (1 << TIMER_TnMR_TACDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */
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# define TIMER_TnMR_TAMIE (1 << 5) /* Bit 5: Timer A Match Interrupt Enable */
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# define TIMER_TnMR_TAWOT (1 << 6) /* Bit 6: GPTM Timer A Wait-on-Trigger */
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# define TIMER_TnMR_TASNAPS (1 << 7) /* Bit 7: GPTM Timer A Snap-Shot Mode */
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# define TIMER_TnMR_TAILD (1 << 8) /* Bit 8: GPTM Timer A Interval Load Write */
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# define TIMER_TnMR_TAPWMIE (1 << 9) /* Bit 9: GPTM Timer A PWM Interrupt Enable */
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# define TIMER_TnMR_TnMRSU (1 << 10) /* Bit 10: GPTM Timer A Match Register Update */
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# define TIMER_TnMR_TAPLO (1 << 11) /* Bit 11: GPTM Timer A PWM Legacy Operation */
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# define TIMER_TnMR_TnCDIR (1 << 4) /* Bit 4: Timer A/B Count Direction */
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# define TIMER_TnMR_TnCDIR_DOWN (0) /* Timer counts down */
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# define TIMER_TnMR_TnCDIR_UP TIMER_TnMR_TnCDIR /* Timer counts up (one-shot/periodic modes) */
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# define TIMER_TnMR_TnMIE (1 << 5) /* Bit 5: Timer A/B Match Interrupt Enable */
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# define TIMER_TnMR_TnWOT (1 << 6) /* Bit 6: GPTM Timer A/B Wait-on-Trigger */
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# define TIMER_TnMR_TnSNAPS (1 << 7) /* Bit 7: GPTM Timer A/B Snap-Shot Mode */
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# define TIMER_TnMR_TnILD (1 << 8) /* Bit 8: GPTM Timer A/B Interval Load Write */
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# define TIMER_TnMR_TnPWMIE (1 << 9) /* Bit 9: GPTM Timer A/B PWM Interrupt Enable */
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# define TIMER_TnMR_TnMRSU (1 << 10) /* Bit 10: GPTM Timer A/B Match Register Update */
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# define TIMER_TnMR_TnPLO (1 << 11) /* Bit 11: GPTM Timer A/B PWM Legacy Operation */
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIMER_TnMR_TACINTD (1 << 12) /* Bit 12: One-shot/Periodic Interrupt Disable */
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# define TIMER_TnMR_TnCINTD (1 << 12) /* Bit 12: One-shot/Periodic Interrupt Disable */
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# define TIMER_TnMR_TCACT_SHIFT (13) /* Bits 13-15: Timer Compare Action Select */
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# define TIMER_TnMR_TCACT_MASK (7 << TIMER_TnMR_TCACT_SHIFT)
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# define TIMER_TnMR_TCACT_NONE (0 << TIMER_TnMR_TCACT_SHIFT) /* Disable compare operations */
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@ -522,26 +522,23 @@
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#define TIMER_CTL_TAEN (1 << 0) /* Bit 0: Timer A Enable */
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#define TIMER_CTL_TASTALL_SHIFT (1 << 1) /* Bit 1: Timer A Stall Enable */
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_CTL_TAEVENT_SHIFT (2) /* Bits 2-3: GPTM Timer A Event Mode */
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# define TIMER_CTL_TAEVENT_MASK (3 << TIMER_CTL_TAEVENT_SHIFT)
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# define TIMER_CTL_TAEVENT_POS (0 << TIMER_CTL_TAEVENT_SHIFT) /* Positive edge */
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# define TIMER_CTL_TAEVENT_NEG (1 << TIMER_CTL_TAEVENT_SHIFT) /* Negative edge */
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# define TIMER_CTL_TAEVENT_BOTH (3 << TIMER_CTL_TAEVENT_SHIFT) /* Both edges */
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# define TIMER_CTL_RTCEN (1 << 4) /* Bit 4: GPTM RTC Stall Enable */
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# define TIMER_CTL_TAOTE (1 << 5) /* Bit 5: GPTM Timer A Output Trigger Enable */
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# define TIMER_CTL_TAPWML (1 << 6) /* Bit 6: GPTM Timer A PWM Output Level */
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# define TIMER_CTL_TBEN (1 << 8) /* Bit 8: GPTM Timer B Enable */
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# define TIMER_CTL_TBSTALL (1 << 9) /* Bit 9: GPTM Timer B Stall Enable */
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# define TIMER_CTL_TBEVENT_SHFIT (10) /* Bits 10-11: GPTM Timer B Event Mode */
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# define TIMER_CTL_TBEVENT_MASK (3 << TIMER_CTL_TBEVENT_SHFIT)
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# define TIMER_CTL_TBEVENT_POS (0 << TIMER_CTL_TBEVENT_SHFIT) /* Positive edge */
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# define TIMER_CTL_TBEVENT_NEG (1 << TIMER_CTL_TBEVENT_SHFIT) /* Negative edge */
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# define TIMER_CTL_TBEVENT_BOTH (3 << TIMER_CTL_TBEVENT_SHFIT) /* Both edges */
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# define TIMER_CTL_TBOTE (1 << 13) /* Bit 13: GPTM Timer B Output Trigger Enable */
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# define TIMER_CTL_TBPWML (1 << 14) /* Bit 14: GPTM Timer B PWM Output Level */
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#endif
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#define TIMER_CTL_TAEVENT_SHIFT (2) /* Bits 2-3: GPTM Timer A Event Mode */
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#define TIMER_CTL_TAEVENT_MASK (3 << TIMER_CTL_TAEVENT_SHIFT)
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# define TIMER_CTL_TAEVENT_POS (0 << TIMER_CTL_TAEVENT_SHIFT) /* Positive edge */
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# define TIMER_CTL_TAEVENT_NEG (1 << TIMER_CTL_TAEVENT_SHIFT) /* Negative edge */
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# define TIMER_CTL_TAEVENT_BOTH (3 << TIMER_CTL_TAEVENT_SHIFT) /* Both edges */
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#define TIMER_CTL_RTCEN (1 << 4) /* Bit 4: GPTM RTC Stall Enable */
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#define TIMER_CTL_TAOTE (1 << 5) /* Bit 5: GPTM Timer A Output Trigger Enable */
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#define TIMER_CTL_TAPWML (1 << 6) /* Bit 6: GPTM Timer A PWM Output Level */
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#define TIMER_CTL_TBEN (1 << 8) /* Bit 8: GPTM Timer B Enable */
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#define TIMER_CTL_TBSTALL (1 << 9) /* Bit 9: GPTM Timer B Stall Enable */
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#define TIMER_CTL_TBEVENT_SHFIT (10) /* Bits 10-11: GPTM Timer B Event Mode */
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#define TIMER_CTL_TBEVENT_MASK (3 << TIMER_CTL_TBEVENT_SHFIT)
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# define TIMER_CTL_TBEVENT_POS (0 << TIMER_CTL_TBEVENT_SHFIT) /* Positive edge */
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# define TIMER_CTL_TBEVENT_NEG (1 << TIMER_CTL_TBEVENT_SHFIT) /* Negative edge */
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# define TIMER_CTL_TBEVENT_BOTH (3 << TIMER_CTL_TBEVENT_SHFIT) /* Both edges */
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#define TIMER_CTL_TBOTE (1 << 13) /* Bit 13: GPTM Timer B Output Trigger Enable */
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#define TIMER_CTL_TBPWML (1 << 14) /* Bit 14: GPTM Timer B PWM Output Level */
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/* GPTM Synchronize (GPTM0 only) */
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@ -793,52 +790,28 @@
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/* GPTM Timer A Match (TAMATCHR) (32-bit value) */
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/* GPTM Timer B Match (TBMATCHR) (32-bit value) */
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/* GPTM Timer A Prescale (TAPR) */
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/* GPTM Timer A/B Prescale (TnPR) */
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#define TIMER_TAPR_TAPSR_SHIFT (0) /* Bits 0-8: GPTM Timer A Prescale */
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#define TIMER_TAPR_TAPSR_MASK (0xff << TIMER_TAPR_TAPSR_SHIFT)
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# define TIMER_TAPR_TAPSR(n) ((uint32_t)(n) << TIMER_TAPR_TAPSR_SHIFT)
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#define TIMER_TnPR_TnPSR_SHIFT (0) /* Bits 0-8: GPTM Timer A/B Prescale */
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#define TIMER_TnPR_TnPSR_MASK (0xff << TIMER_TnPR_TnPSR_SHIFT)
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# define TIMER_TnPR_TnPSR(n) ((uint32_t)(n) << TIMER_TnPR_TnPSR_SHIFT)
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#if 0
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# define TIMER_TAPR_TAPSRH_SHIFT (8) /* Bits 8-15: GPTM Timer A Prescale High Byte */
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# define TIMER_TAPR_TAPSRH_MASK (0xff << TIMER_TAPR_TAPSRH_SHIFT)
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# define TIMER_TAPR_TAPSRH(n) ((uint32_t)(n) << TIMER_TAPR_TAPSRH_SHIFT)
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# define TIMER_TnPR_TnPSRH_SHIFT (8) /* Bits 8-15: GPTM Timer A/B Prescale High word */
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# define TIMER_TnPR_TnPSRH_MASK (0xff << TIMER_TnPR_TnPSRH_SHIFT)
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# define TIMER_TnPR_TnPSRH(n) ((uint32_t)(n) << TIMER_TnPR_TnPSRH_SHIFT)
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#endif
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/* GPTM Timer B Prescale (TBPR) */
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/* GPTM Timer A/B Prescale Match (TnPMR) */
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#define TIMER_TBPR_TBPSR_SHIFT (0) /* Bits 0-8: GPTM Timer B Prescale */
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#define TIMER_TBPR_TBPSR_MASK (0xff << TIMER_TBPR_TBPSR_SHIFT)
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# define TIMER_TBPR_TBPSR(n) ((uint32_t)(n) << TIMER_TBPR_TBPSR_SHIFT)
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#define TIMER_TnPMR_TnPSMR_SHIFT (0) /* Bits 0-8: GPTM Timer A/B Prescale Match */
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#define TIMER_TnPMR_TnPSMR_MASK (0xff << TIMER_TnPMR_TnPSMR_SHIFT)
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# define TIMER_TnPMR_TnPSMR(n) ((uint32_t)(n) << TIMER_TnPMR_TnPSMR_SHIFT)
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#if 0
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# define TIMER_TBPR_TBPSRH_SHIFT (8) /* Bits 8-15: GPTM Timer B Prescale High Byte */
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# define TIMER_TBPR_TBPSRH_MASK (0xff << TIMER_TBPR_TBPSRH_SHIFT)
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# define TIMER_TBPR_TBPSRH(n) ((uint32_t)(n) << TIMER_TBPR_TBPSRH_SHIFT)
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#endif
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/* GPTM TimerA Prescale Match (TAPMR) */
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#define TIMER_TAPMR_TAPSMR_SHIFT (0) /* Bits 0-8: GPTM Timer A Prescale Match */
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#define TIMER_TAPMR_TAPSMR_MASK (0xff << TIMER_TAPMR_TAPSMR_SHIFT)
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# define TIMER_TAPMR_TAPSMR(n) ((uint32_t)(n) << TIMER_TAPMR_TAPSMR_SHIFT)
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#if 0
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# define TIMER_TAPMR_TAPSMRH_SHIFT (8) /* Bits 8-15: GPTM Timer A Prescale Match High Byte */
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# define TIMER_TAPMR_TAPSMRH_MASK (0xff << TIMER_TAPMR_TAPSMRH_SHIFT)
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# define TIMER_TAPMR_TAPSMRH(n) ((uint32_t)(n) << TIMER_TAPMR_TAPSMRH_SHIFT)
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#endif
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/* GPTM TimerB Prescale Match (TBPMR) */
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#define TIMER_TBPMR_TBPSMR_SHIFT (0) /* Bits 0-8: GPTM Timer B Prescale Match */
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#define TIMER_TBPMR_TBPSMR_MASK (0xff << TIMER_TBPMR_TBPSMR_SHIFT)
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# define TIMER_TBPMR_TBPSMR(n) ((uint32_t)(n) << TIMER_TBPMR_TBPSMR_SHIFT)
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#if 0
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# define TIMER_TBPMR_TBPSMRH_SHIFT (8) /* Bits 8-15: GPTM Timer B Prescale Match High Byte */
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# define TIMER_TBPMR_TBPSMRH_MASK (0xff << TIMER_TBPMR_TBPSMRH_SHIFT)
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# define TIMER_TBPMR_TBPSMRH(n) ((uint32_t)(n) << TIMER_TBPMR_TBPSMRH_SHIFT)
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# define TIMER_TnPMR_TnPSMRH_SHIFT (8) /* Bits 8-15: GPTM Timer A/B Prescale Match High word */
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# define TIMER_TnPMR_TnPSMRH_MASK (0xff << TIMER_TnPMR_TnPSMRH_SHIFT)
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# define TIMER_TnPMR_TnPSMRH(n) ((uint32_t)(n) << TIMER_TnPMR_TnPSMRH_SHIFT)
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#endif
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/* GPTM Timer A (TAR) (32-bit value) */
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@ -854,36 +827,20 @@
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# define TIMER_RTCPD(n) ((uint32_t)(n) << TIMER_RTCPD_SHIFT)
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#endif
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/* GPTM Timer A Prescale Snapshot (TAPS) */
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/* GPTM Timer A/B Prescale Snapshot (TnPS) */
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_TAPS_PSS_SHIFT (0) /* Bits 0-15: GPTM Timer A Prescaler Snapshot */
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# define TIMER_TAPS_PSS_MASK (0xffff << TIMER_TAPS_PSS_SHIFT)
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# define TIMER_TAPS_PSS(n) ((uint32_t)(n) << TIMER_TAPS_PSS_SHIFT)
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# define TIMER_TnPS_PSS_SHIFT (0) /* Bits 0-15: GPTM Timer A/B Prescaler Snapshot */
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# define TIMER_TnPS_PSS_MASK (0xffff << TIMER_TnPS_PSS_SHIFT)
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# define TIMER_TnPS_PSS(n) ((uint32_t)(n) << TIMER_TnPS_PSS_SHIFT)
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#endif
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/* GPTM Timer B Prescale Snapshot (TBPS) */
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/* GPTM Timer A/B Prescale Value (TnPV) */
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_TBPS_PSS_SHIFT (0) /* Bits 0-15: GPTM Timer A Prescaler Value */
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# define TIMER_TBPS_PSS_MASK (0xffff << TIMER_TBPS_PSS_SHIFT)
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# define TIMER_TBPS_PSS(n) ((uint32_t)(n) << TIMER_TBPS_PSS_SHIFT)
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#endif
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/* GPTM Timer A Prescale Value (TAPV) */
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_TAPV_PSS_SHIFT (0) /* Bits 0-15: GPTM Timer A Prescaler Value */
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# define TIMER_TAPS_PSS_MASK (0xffff << TIMER_TAPS_PSS_SHIFT)
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# define TIMER_TAPS_PSS(n) ((uint32_t)(n) << TIMER_TAPS_PSS_SHIFT)
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#endif
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/* GPTM Timer B Prescale Value (TBPV) */
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIMER_TBPV_PSS_SHIFT (0) /* Bits 0-15: GPTM Timer B Prescaler Value */
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# define TIMER_TBPS_PSS_MASK (0xffff << TIMER_TBPS_PSS_SHIFT)
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# define TIMER_TBPS_PSS(n) ((uint32_t)(n) << TIMER_TBPS_PSS_SHIFT)
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# define TIMER_TnPV_PSS_SHIFT (0) /* Bits 0-15: GPTM Timer A/B Prescaler Value */
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# define TIMER_TnPS_PSS_MASK (0xffff << TIMER_TnPS_PSS_SHIFT)
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# define TIMER_TnPS_PSS(n) ((uint32_t)(n) << TIMER_TnPS_PSS_SHIFT)
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#endif
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/* GPTM DMA Event (DMAEV) */
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@ -678,14 +678,61 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv,
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tiva_putreg(priv, TIVA_TIMER_TAMR_OFFSET, regval);
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/* 4. Optionally configure the TnSNAPS, TnWOT, TnMTE, and TnCDIR bits in
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* the GPTMTnMR register to select whether to capture the value of the
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/* 4. Optionally configure the TASNAPS, TAWOT, TAMINTD, and TACDIR bits in
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* the GPTMTAMR register to select whether to capture the value of the
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* free-running timer at time-out, use an external trigger to start
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* counting, configure an additional trigger or interrupt, and count up
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* or down. In addition, if using CCP pins, the TCACT field can be
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* programmed to configure the compare action.
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* or down.
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*
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* TASNAPS - GPTM Timer A Snap-Shot Mode
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* 0: Snap-shot mode is disabled (default)
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* 1: If the 32-bit timeris configured in the periodic mode,
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* the actual free-running, capture or snapshot value of
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* the timer is loaded at the time-out event/capture or
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* snapshot event into the concatenated GPTM Timer A
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* (GPTMTAR) register.
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* TAWOT - GPTM Timer A Wait-on-Trigger
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* 0: The 32-bit timer begins counting as soon as it is
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* enabled (default).
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* 1: If the 32-bit timer is enabled, it does not begin
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* counting until it receives a trigger from the timer
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* in the previous position in the daisy chain.
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* TAINTD - One-shot/Periodic Interrupt Disable
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* 0: Time-out interrupt functions as normal.
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* 1: Time-out interrupt are disabled (default).
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* TACDIR - GPTM Timer A Count Direction
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* 0: The timer counts down (default).
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* 1: The timer counts up. When counting up, the timer
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* starts from a value of 0.
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*/
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#warning Missing logic
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/* Setup defaults */
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regval &= (TIMER_TnMR_TnCDIR | TIMER_TnMR_TnWOT | TIMER_TnMR_TnCDIR);
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regval |= TIMER_TnMR_TnCINTD;
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/* Enable snapshot mode? */
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#warning Missing Logic
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/* Enable wait-on-trigger? */
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#warning Missing Logic
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/* Enable one-shot/periodic interrupts? */
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#warning Missing Logic
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/* Enable count down? */
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if (timer->countup)
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{
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regval |= TIMER_TnMR_TnCDIR_UP;
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}
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tiva_putreg(priv, TIVA_TIMER_TAMR_OFFSET, regval);
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/* In addition, if using CCP pins, the TCACT field can be programmed to
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* configure the compare action.
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*/
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#warning Missing Logic
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/* 5. Load the start value into the GPTM Timer n Interval Load Register
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* (GPTMTAILR).
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@ -767,14 +814,62 @@ static int tiva_oneshot_periodic_mode16(struct tiva_gptmstate_s *priv,
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tiva_putreg(priv, regoffset, regval);
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/* 4. Optionally configure the TnSNAPS, TnWOT, TnMTE, and TnCDIR bits in
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/* 4. Optionally configure the TnSNAPS, TnWOT, TnMINTD, and TnCDIR bits in
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* the GPTMTnMR register to select whether to capture the value of the
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* free-running timer at time-out, use an external trigger to start
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* counting, configure an additional trigger or interrupt, and count up
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||||
* or down. In addition, if using CCP pins, the TCACT field can be
|
||||
* programmed to configure the compare action.
|
||||
*
|
||||
* TnSNAPS - GPTM Timer A/B Snap-Shot Mode
|
||||
* 0: Snap-shot mode is disabled (default)
|
||||
* 1: If the 16-bit timer is configured in the periodic mode,
|
||||
* the actual free-running, capture or snapshot value of
|
||||
* the timer is loaded at the time-out event/capture or
|
||||
* snapshot event into the GPTM Timer A/B (GPTMTnR)
|
||||
* register. If the timer prescaler is used, the prescaler
|
||||
* snapshot is loaded into the GPTM Timer A/B (GPTMTnPR).
|
||||
* TnWOT - GPTM Timer A/B Wait-on-Trigger
|
||||
* 0: The 16-bit begins counting as soon as it is enabled (default).
|
||||
* 1: If the 16-bit timer is enabled, it does not begin counting
|
||||
* until it receives a trigger from the timer in the
|
||||
* previous position in the daisy chain.
|
||||
* TnINTD - One-shot/Periodic Interrupt Disable
|
||||
* 0: Time-out interrupt functions as normal.
|
||||
* 1: Time-out interrupt are disabled (default).
|
||||
* TnCDIR - GPTM Timer A/B Count Direction
|
||||
* 0: The timer counts down (default).
|
||||
* 1: The timer counts up. When counting up, the timer
|
||||
* starts from a value of 0.
|
||||
*/
|
||||
#warning Missing logic
|
||||
|
||||
/* Setup defaults */
|
||||
|
||||
regval &= (TIMER_TnMR_TnCDIR | TIMER_TnMR_TnWOT | TIMER_TnMR_TnCDIR);
|
||||
regval |= TIMER_TnMR_TnCINTD;
|
||||
|
||||
/* Enable snapshot mode? */
|
||||
#warning Missing Logic
|
||||
|
||||
/* Enable wait-on-trigger? */
|
||||
#warning Missing Logic
|
||||
|
||||
/* Enable one-shot/periodic interrupts? */
|
||||
#warning Missing Logic
|
||||
|
||||
/* Enable count down? */
|
||||
|
||||
if (timer->countup)
|
||||
{
|
||||
regval |= TIMER_TnMR_TnCDIR_UP;
|
||||
}
|
||||
|
||||
tiva_putreg(priv, regoffset, regval);
|
||||
|
||||
/* In addition, if using CCP pins, the TCACT field can be programmed to
|
||||
* configure the compare action.
|
||||
*/
|
||||
#warning Missing Logic
|
||||
|
||||
/* 5. Load the start value into the GPTM Timer n Interval Load Register
|
||||
* (GPTMTnILR).
|
||||
|
||||
@ -85,8 +85,8 @@
|
||||
|
||||
#define TIMER_SYNC(n) (1 << (n))
|
||||
|
||||
/* Identifies 16-bit timer A and timer B. In most cases, the 32-bit timer
|
||||
* is equivalent to timer a.
|
||||
/* Identifies 16-bit timer A and timer B. In contexts where an index is
|
||||
* needed, the 32-bit timer is equivalent to the timer A index.
|
||||
*/
|
||||
|
||||
#define TIMER32 0
|
||||
@ -134,7 +134,7 @@ typedef void (*timer32_handler_t)(TIMER_HANDLE handle,
|
||||
|
||||
struct tiva_timer32config_s
|
||||
{
|
||||
bool down; /* False: Count up; True: Count down */
|
||||
bool countup; /* True: Count up; False: Count down */
|
||||
timer32_handler_t handler; /* Non-NULL: Interrupts will be enabled
|
||||
* and forwarded to this function */
|
||||
/* TODO: Add fields to support ADC trigger events */
|
||||
@ -170,7 +170,7 @@ typedef void (*timer16_handler_t)(TIMER_HANDLE handle,
|
||||
struct tiva_timer16config_s
|
||||
{
|
||||
uint8_t mode; /* See enum tiva_timermode_e */
|
||||
bool down; /* False: Count up; True: Count down */
|
||||
bool countup; /* True: Count up; False: Count down */
|
||||
timer16_handler_t handler; /* Non-NULL: Interrupts will be enabled
|
||||
* and forwarded to this function */
|
||||
/* TODO: Add fields to support ADC trigger events */
|
||||
@ -323,13 +323,31 @@ static inline void tiva_timer16_start(TIMER_HANDLE handle, int tmndx)
|
||||
{
|
||||
uint32_t setbits = tmndx ? TIMER_CTL_TBEN : TIMER_CTL_TAEN;
|
||||
|
||||
/* Set the TnEN bit in the GPTMCTL register to enable the timer and start
|
||||
* counting
|
||||
/* Set the TnEN bit in the GPTMCTL register to enable the 16-bit timer and
|
||||
* start counting
|
||||
*/
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, 0, setbits);
|
||||
}
|
||||
|
||||
static inline void tiva_timer16a_start(TIMER_HANDLE handle)
|
||||
{
|
||||
/* Set the TAEN bit in the GPTMCTL register to enable 16-bit timer A and
|
||||
* start counting
|
||||
*/
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, 0, TIMER_CTL_TAEN);
|
||||
}
|
||||
|
||||
static inline void tiva_timer16b_start(TIMER_HANDLE handle)
|
||||
{
|
||||
/* Set the TBEN bit in the GPTMCTL register to enable 16-bit timer B and
|
||||
* start counting
|
||||
*/
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, 0, TIMER_CTL_TBEN);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_timer32_stop
|
||||
*
|
||||
@ -341,9 +359,7 @@ static inline void tiva_timer16_start(TIMER_HANDLE handle, int tmndx)
|
||||
|
||||
static inline void tiva_timer32_stop(TIMER_HANDLE handle)
|
||||
{
|
||||
/* Clear the TAEN bit in the GPTMCTL register to enable the timer and
|
||||
* start counting
|
||||
*/
|
||||
/* Clear the TAEN bit in the GPTMCTL register to disable the 16-bit timer */
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, TIMER_CTL_TAEN, 0);
|
||||
}
|
||||
@ -361,13 +377,25 @@ static inline void tiva_timer16_stop(TIMER_HANDLE handle, int tmndx)
|
||||
{
|
||||
uint32_t clrbits = tmndx ? TIMER_CTL_TBEN : TIMER_CTL_TAEN;
|
||||
|
||||
/* Clear the TAEN bit in the GPTMCTL register to enable the timer and
|
||||
* start counting
|
||||
*/
|
||||
/* Clear the TnEN bit in the GPTMCTL register to disable the 16-bit timer */
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, clrbits, 0);
|
||||
}
|
||||
|
||||
static inline void tiva_timer16a_stop(TIMER_HANDLE handle)
|
||||
{
|
||||
/* Clear the TAEN bit in the GPTMCTL register to disable the 16-bit timer A */
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, TIMER_CTL_TAEN, 0);
|
||||
}
|
||||
|
||||
static inline void tiva_timer16b_stop(TIMER_HANDLE handle)
|
||||
{
|
||||
/* Clear the TBEN bit in the GPTMCTL register to disable the 16-bit timer B */
|
||||
|
||||
tiva_gptm_modifyreg(handle, TIVA_TIMER_CTL_OFFSET, TIMER_CTL_TBEN, 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_timer32_setload
|
||||
*
|
||||
@ -400,11 +428,64 @@ static inline void tiva_timer16_setload(TIMER_HANDLE handle, uint16_t load,
|
||||
tiva_gptm_putreg(handle, regoffset, load);
|
||||
}
|
||||
|
||||
static inline void tiva_timer16a_setload(TIMER_HANDLE handle, uint16_t load)
|
||||
{
|
||||
tiva_gptm_putreg(handle, TIVA_TIMER_TAILR_OFFSET, load);
|
||||
}
|
||||
|
||||
static inline void tiva_timer16b_setload(TIMER_HANDLE handle, uint16_t load)
|
||||
{
|
||||
tiva_gptm_putreg(handle, TIVA_TIMER_TBILR_OFFSET, load);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_timer32_setmatch
|
||||
*
|
||||
* Description:
|
||||
* This function may be called at any time to change the timer interval
|
||||
* match value of a 32-bit timer.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void tiva_timer32_setmatch(TIMER_HANDLE handle, uint32_t match)
|
||||
{
|
||||
tiva_gptm_putreg(handle, TIVA_TIMER0_TAMATCHR, match);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_timer16_setmatch
|
||||
*
|
||||
* Description:
|
||||
* This function may be called at any time to change the timer interval
|
||||
* match value of a 16-bit timer.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void tiva_timer16_setmatch(TIMER_HANDLE handle, uint16_t match,
|
||||
int tmndx)
|
||||
{
|
||||
unsigned int regoffset =
|
||||
tmndx ? TIVA_TIMER0_TBMATCHR : TIVA_TIMER0_TAMATCHR;
|
||||
|
||||
tiva_gptm_putreg(handle, regoffset, match);
|
||||
}
|
||||
|
||||
static inline void tiva_timer16a_setmatch(TIMER_HANDLE handle, uint16_t match)
|
||||
{
|
||||
tiva_gptm_putreg(handle, TIVA_TIMER0_TAMATCHR, match);
|
||||
}
|
||||
|
||||
static inline void tiva_timer16b_setmatch(TIMER_HANDLE handle, uint16_t match)
|
||||
{
|
||||
tiva_gptm_putreg(handle, TIVA_TIMER0_TBMATCHR, match);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gptm0_synchronize
|
||||
*
|
||||
* Description:
|
||||
* Trigger timers from GPTM0 output.
|
||||
* Trigger timers from GPTM0 output. This is part of the timer
|
||||
* configuration logic and should be called before timers are enabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user