SAMD21: Add memory map header file
This commit is contained in:
Gregory Nutt
parent
b4682bd839
commit
62973af6eb
@ -394,10 +394,15 @@
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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# if defined(CONFIG_ARCH_CHIP_SAMD21E15A)
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
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# else
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# define SAMDL_FLASHRWW_SIZE (1*1024) /* 1KB */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_SAMD21E16A) || defined(CONFIG_ARCH_CHIP_SAMD21E16B)
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# define SAMD21 1 /* SAMD21 family */
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@ -408,10 +413,15 @@
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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# if defined(CONFIG_ARCH_CHIP_SAMD21E16A)
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
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# else
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# define SAMDL_FLASHRWW_SIZE (2*1024) /* 2KB */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_SAMD21E17A)
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# define SAMD21 1 /* SAMD21 family */
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@ -422,7 +432,7 @@
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
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# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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@ -436,7 +446,7 @@
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
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# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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@ -450,10 +460,15 @@
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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# if defined(CONFIG_ARCH_CHIP_SAMD21G15A)
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
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# else
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# define SAMDL_FLASHRWW_SIZE (1*1024) /* 1KB */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_SAMD21G16A) || defined(CONFIG_ARCH_CHIP_SAMD21G16B)
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# define SAMD21 1 /* SAMD21 family */
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@ -464,10 +479,15 @@
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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# if defined(CONFIG_ARCH_CHIP_SAMD21G16A)
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
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# else
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# define SAMDL_FLASHRWW_SIZE (2*1024) /* 2KB */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_SAMD21G17A)
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# define SAMD21 1 /* SAMD21 family */
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@ -478,7 +498,7 @@
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
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# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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@ -492,7 +512,7 @@
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
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# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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@ -506,10 +526,15 @@
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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# if defined(CONFIG_ARCH_CHIP_SAMD21J15A)
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
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# else
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# define SAMDL_FLASHRWW_SIZE (1*1024) /* 1KB */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_SAMD21J16A) || defined(CONFIG_ARCH_CHIP_SAMD21J16B)
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# define SAMD21 1 /* SAMD21 family */
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@ -520,10 +545,15 @@
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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# if defined(CONFIG_ARCH_CHIP_SAMD21J16A)
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
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# else
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# define SAMDL_FLASHRWW_SIZE (2*1024) /* 2KB */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_SAMD21J17A)
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# define SAMD21 1 /* SAMD21 family */
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@ -534,7 +564,7 @@
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
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# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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@ -548,7 +578,7 @@
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
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# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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@ -1,9 +1,13 @@
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/****************************************************************************************
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* arch/arm/include/samd/samd21_irq.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
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* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@ -56,6 +56,8 @@
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#if defined(CONFIG_ARCH_FAMILY_SAMD20)
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# include "chip/samd20_memorymap.h"
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#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
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# include "chip/samd21_memorymap.h"
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#elif defined(CONFIG_ARCH_FAMILY_SAML21)
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# include "chip/saml21_memorymap.h"
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#else
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130
arch/arm/src/samdl/chip/samd21_memorymap.h
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130
arch/arm/src/samdl/chip/samd21_memorymap.h
Normal file
@ -0,0 +1,130 @@
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/********************************************************************************************
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* arch/arm/src/samdl/chip/samd21_memorymap.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
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* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD21_MEMORYMAP_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD21_MEMORYMAP_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* System Memory Map */
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#define SAM_FLASH_BASE 0x00000000 /* Embedded FLASH memory space (<= 256KB) */
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#define SAM_FLASHRWW_BASE 0x00100000 /* Embedded FLASH RWW memory space (<= 2KB) */
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#define SAM_CALIB_BASE 0x00800000 /* Calibration and auxiliary space */
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#define SAM_SRAM_BASE 0x20000000 /* Embedded SRAM memory space (<= 64KB) */
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#define SAM_AHBA_BASE 0x40000000 /* AHB-APB Bridge A (64KB) */
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#define SAM_AHBB_BASE 0x41000000 /* AHB-APB Bridge B (64KB) */
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#define SAM_AHBC_BASE 0x42000000 /* AHB-APB Bridge C (64KB) */
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/* Calibration and Auxiliary Space */
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#define SAM_AUTOCAL_BASE 0x00800000 /* Automatic Calibration row */
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#define SAM_AUX0_BASE 0x00804000 /* AUX0 offset address */
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#define SAM_AUX1_BASE 0x00806000 /* AUX1 offset address */
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# define SAM_AUX1_AREA1 0x00806000 /* Area 1 offset address (reserved, 64 bits) */
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# define SAM_AUX1_AREA2 0x00806008 /* Area 2 Device configuration area (64 bits) */
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# define SAM_AUX1_AREA3 0x00806010 /* Area 3 offset address (reserved, 128 bits) */
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# define SAM_AUX1_AREA4 0x00806020 /* Area 4 Software calibration area (256 bits) */
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/* AHB-APB Bridge A */
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#define SAM_PAC0_BASE 0x40000000 /* Peripheral Access Controller 0 */
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#define SAM_PM_BASE 0x40000400 /* Power Manager */
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#define SAM_SYSCTRL_BASE 0x40000800 /* System Controller */
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#define SAM_GCLK_BASE 0x40000c00 /* Generic Clock Controller */
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#define SAM_WDT_BASE 0x40001000 /* Watchdog Timer */
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#define SAM_RTC_BASE 0x40001400 /* Real-Time Counter */
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#define SAM_EIC_BASE 0x40001800 /* External Interrupt Controller */
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/* AHB-APB Bridge B */
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#define SAM_PAC1_BASE 0x41000000 /* Peripheral Access Controller 1 */
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#define SAM_DSU_BASE 0x41002000 /* Device Service Unit */
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#define SAM_NVMCTRL_BASE 0x41004000 /* Non-Volatile Memory Controller */
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#define SAM_PORT_BASE 0x41004400 /* Ports */
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#define SAM_DMAC_BASE 0x41004800 /* DMA Controller */
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#define SAM_USB_BASE 0x41005000 /* USB */
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#define SAM_MTB_BASE 0x41006000 /* Micro Trace Buffer (MTB) */
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/* AHB-APB Bridge C */
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#define SAM_PAC2_BASE 0x42000000 /* Peripheral Access Controller 2 */
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#define SAM_EVSYS_BASE 0x42000400 /* Event System */
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#define SAM_SERCOM0_BASE 0x42000800 /* Serial Communication Interface 0 */
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#define SAM_SERCOM1_BASE 0x42000c00 /* Serial Communication Interface 1 */
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#define SAM_SERCOM2_BASE 0x42001000 /* Serial Communication Interface 2 */
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#define SAM_SERCOM3_BASE 0x42001400 /* Serial Communication Interface 3 */
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#define SAM_SERCOM4_BASE 0x42001800 /* Serial Communication Interface 4 */
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#define SAM_SERCOM5_BASE 0x42001c00 /* Serial Communication Interface 5 */
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#define SAM_TCC0_BASE 0x42002000 /* Timer/Counter Control 0 */
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#define SAM_TCC1_BASE 0x42002400 /* Timer/Counter Control 1 */
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#define SAM_TCC2_BASE 0x42002800 /* Timer/Counter Control 2 */
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#define SAM_TC3_BASE 0x42002c00 /* Timer/Counter 3 */
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#define SAM_TC4_BASE 0x42003000 /* Timer/Counter 4 */
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#define SAM_TC5_BASE 0x42003400 /* Timer/Counter 5 */
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#define SAM_TC6_BASE 0x42003800 /* Timer/Counter 6 */
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#define SAM_TC7_BASE 0x42003c00 /* Timer/Counter 7 */
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#define SAM_ADC_BASE 0x42004000 /* Analog-to-Digital Converter */
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#define SAM_AC_BASE 0x42004400 /* Analog Comparator*/
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#define SAM_DAC_BASE 0x42004800 /* Digital-to-Analog Converter */
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#define SAM_PTC_BASE 0x42004c00 /* Peripheral Touch Controller */
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#define SAM_I2S_BASE 0x42005000 /* Inter IC Sound */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD21_MEMORYMAP_H */
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