Add EEFC header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2482 42af7a65-404d-4744-a932-0658087f49c3
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arch/arm/src/sam3u/sam3u_eefc.h
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arch/arm/src/sam3u/sam3u_eefc.h
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/****************************************************************************************
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* arch/arm/src/sam3u/sam3u_eefc.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H
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#define __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "sam3u_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* EEFC register offsets ****************************************************************/
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#define SAM3U_EEFC_FMR_OFFSET 0x00 /* EEFC Flash Mode Register */
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#define SAM3U_EEFC_FCR_OFFSET 0x04 /* EEFC Flash Command Register */
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#define SAM3U_EEFC_FSR_OFFSET 0x08 /* EEFC Flash Status Register */
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#define SAM3U_EEFC_FRR_OFFSET 0x0c /* EEFC Flash Result Register */
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/* EEFC register adresses ***************************************************************/
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#define SAM3U_EEFC_FMR(n) (SAM3U_EEFC_BASE(n)+SAM3U_EEFC_FMR_OFFSET)
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#define SAM3U_EEFC_FCR(n) (SAM3U_EEFC_BASE(n)+SAM3U_EEFC_FCR_OFFSET)
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#define SAM3U_EEFC_FSR(n) (SAM3U_EEFC_BASE(n)+SAM3U_EEFC_FSR_OFFSET)
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#define SAM3U_EEFC_FRR(n) (SAM3U_EEFC_BASE(n)+SAM3U_EEFC_FRR_OFFSET)
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#define SAM3U_EEFC0_FMR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FMR_OFFSET)
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#define SAM3U_EEFC0_FCR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FCR_OFFSET)
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#define SAM3U_EEFC0_FSR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FSR_OFFSET)
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#define SAM3U_EEFC0_FRR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FRR_OFFSET)
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#define SAM3U_EEFC1_FMR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FMR_OFFSET)
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#define SAM3U_EEFC1_FCR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FCR_OFFSET)
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#define SAM3U_EEFC1_FSR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FSR_OFFSET)
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#define SAM3U_EEFC1_FRR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FRR_OFFSET)
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/* EEFC register bit definitions ********************************************************/
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#define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */
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#define EEFC_FMR_FWS_SHIFT (8) /* Bits 8-11: Flash Wait State */
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#define EEFC_FMR_FWS_MASK (15 << EEFC_FMR_FWS_SHIFT)
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#define EEFC_FMR_FAM (1 << 24) /* Bit 24: Flash Access Mode */
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#define EEFC_FCR_FCMD_SHIFT (0) /* Bits 0-7: Flash Command */
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#define EEFC_FCR_FCMD_MASK (0xff << EEFC_FCR_FCMD_SHIFT)
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# define EEFC_FCR_FCMD_GETD (0 << EEFC_FCR_FCMD_SHIFT) /* Get Flash Descriptor */
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# define EEFC_FCR_FCMD_WP (1 << EEFC_FCR_FCMD_SHIFT) /* Write page */
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# define EEFC_FCR_FCMD_WPL (2 << EEFC_FCR_FCMD_SHIFT) /* Write page and lock */
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# define EEFC_FCR_FCMD_EWP (3 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page */
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# define EEFC_FCR_FCMD_EWPL (4 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page then lock */
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# define EEFC_FCR_FCMD_EA (5 << EEFC_FCR_FCMD_SHIFT) /* Erase all */
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# define EEFC_FCR_FCMD_SLB (8 << EEFC_FCR_FCMD_SHIFT) /* Set Lock Bit */
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# define EEFC_FCR_FCMD_CLB (9 << EEFC_FCR_FCMD_SHIFT) /* Clear Lock Bit */
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# define EEFC_FCR_FCMD_GLB (10 << EEFC_FCR_FCMD_SHIFT) /* Get Lock Bit */
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# define EEFC_FCR_FCMD_SGPB (11 << EEFC_FCR_FCMD_SHIFT) /* Set GPNVM Bit */
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# define EEFC_FCR_FCMD_CGPB (12 << EEFC_FCR_FCMD_SHIFT) /* Clear GPNVM Bit */
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# define EEFC_FCR_FCMD_GGPB (13 << EEFC_FCR_FCMD_SHIFT) /* Get GPNVM Bit */
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# define EEFC_FCR_FCMD_STUI (14 << EEFC_FCR_FCMD_SHIFT) /* Start Read Unique Identifier */
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# define EEFC_FCR_FCMD_SPUI (15 << EEFC_FCR_FCMD_SHIFT) /* Stop Read Unique Identifier */
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#define EEFC_FCR_FARG_SHIFT (8) /* Bits 8-23: Flash Command Argument */
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#define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT)
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#define EEFC_FCR_FKEY_SHIFT (24) /* Bits 24-31: Flash Writing Protection Key */
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#define EEFC_FCR_FKEY__MASK (0xff << EEFC_FCR_FKEY_SHIFT)
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#define EEFC_FSR_FRDY (1 << 0) /* Bit 0: Flash Ready Status */
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#define EEFC_FSR_FCMDE (1 << 1) /* Bit 1: Flash Command Error Status */
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#define EEFC_FSR_FLOCKE (1 << 2) /* Bit 2: Flash Lock Error Status */
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H */
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@ -105,8 +105,9 @@
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#define SAM3U_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */
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#define SAM3U_UART_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART */
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#define SAM3U_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */
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#define SAM3U_EFC0_BASE 0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */
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#define SAM3U_EFC1_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */
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#define SAM3U_EEFC_BASE(n) (0x400e0800+((n)*0x200)
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#define SAM3U_EEFC0_BASE 0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */
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#define SAM3U_EEFC1_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */
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#define SAM3U_PIOA_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */
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#define SAM3U_PIOB_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */
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#define SAM3U_PIOC_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */
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