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Add BCR index calculation

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2460 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2009-12-29 22:44:03 +00:00
parent 8530da2baf
commit 62da3e6427
7 changed files with 136 additions and 13 deletions
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6
arch/arm/src/lpc313x/Make.defs
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@ -46,9 +46,9 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
up_undefinedinsn.c up_usestack.c
CGU_ASRCS =
CGU_CSRCS = lpc313x_clkdomain.c lpc313x_clkfreq.c lpc313x_esrndx.c \
lpc313x_fdcndx.c lpc313x_freqin.c lpc313x_pllconfig.c \
lpc313x_setfreqin.c lpc313x_softreset.c
CGU_CSRCS = lpc313x_bcrndx.c lpc313x_clkdomain.c lpc313x_clkfreq.c \
lpc313x_esrndx.c lpc313x_fdcndx.c lpc313x_freqin.c \
lpc313x_pllconfig.c lpc313x_setfreqin.c lpc313x_softreset.c
CHIP_ASRCS = $(CGU_ASRCS)
CHIP_CSRCS = lpc313x_allocateheap.c lpc313x_boot.c lpc313x_irq.c \

110
arch/arm/src/lpc313x/lpc313x_bcrndx.c Executable file
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@ -0,0 +1,110 @@
/************************************************************************
* arch/arm/src/lpc313x/lpc313x_bcrndx.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************/
/************************************************************************
* Included Files
************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "up_arch.h"
#include "lpc313x_cgudrvr.h"
/************************************************************************
* Pre-processor Definitions
************************************************************************/
/************************************************************************
* Private Data
************************************************************************/
/************************************************************************
* Private Functions
************************************************************************/
/************************************************************************
* Public Functions
************************************************************************/
/************************************************************************
* Name: lp313x_esrndx
*
* Description:
* Given a clock ID, return the index of the corresponding ESR
* register (or ESRNDX_INVALID if there is no ESR associated with
* this clock ID). Indexing of ESRs differs slightly from the clock
* ID: There are 92 clock IDs but only 89 ESR regisers. There are no
* ESR registers for :
*
*
* CLKID_I2SRXBCK0 Clock ID 87: I2SRX_BCK0
* CLKID_I2SRXBCK1, Clock ID 88: I2SRX_BCK1
*
* and
*
* CLKID_SYSCLKO Clock ID 91: SYSCLK_O
*
************************************************************************/
int lp313x_ncrndx(enum lpc313x_domainid_e dmnid)
{
switch (dmnid)
{
/* BCR0-3 correspond directly to domains 0-3 */
case DOMAINID_SYS: /* Domain 0: SYS_BASE */
case DOMAINID_AHB0APB0: /* Domain 1: AHB0APB0_BASE */
case DOMAINID_AHB0APB1: /* Domain 2: AHB0APB1_BASE */
case DOMAINID_AHB0APB2: /* Domain 3: AHB0APB2_BASE */
return (int)dmnid;
/* There is a BCR register corresponding to domain 7, but it is at
* index 4
*/
case DOMAINID_CLK1024FS: /* Domain 7: CLK1024FS_BASE */
return 4;
default: /* There is no BCR register for the other
* domains. */
break;
}
return BCRNDX_INVALID;
}

8
arch/arm/src/lpc313x/lpc313x_cgu.h
View File

@ -421,6 +421,7 @@
/* Base control registers (BCR) for SYS base */
#define LPC313X_CGU_BCR_OFFSET(n) (0x504+((n)<<2))
#define LPC313X_CGU_BCR0_OFFSET 0x504 /* SYS base */
#define LPC313X_CGU_BCR1_OFFSET 0x508 /* AHB0_APB0 base */
#define LPC313X_CGU_BCR2_OFFSET 0x50c /* AHB0_APB1 base */
@ -951,6 +952,7 @@
/* Base control registers (BCR) for SYS base */
#define LPC313X_CGU_BCR(n) (LPC313X_CGU_CSB_VBASE+LPC313X_CGU_BCR_OFFSET(n))
#define LPC313X_CGU_BCR0 (LPC313X_CGU_CSB_VBASE+LPC313X_CGU_BCR0_OFFSET)
#define LPC313X_CGU_BCR1 (LPC313X_CGU_CSB_VBASE+LPC313X_CGU_BCR1_OFFSET)
#define LPC313X_CGU_BCR2 (LPC313X_CGU_CSB_VBASE+LPC313X_CGU_BCR2_OFFSET)
@ -1215,11 +1217,7 @@
/* Base control registers 0 BCR0 to BCR7, addresses 0x13004504 to 0x13004514 */
#define CGU_BCR0_FDRUN (1 << 0) /* Bit 0: Enable fractional dividers in SYS base */
#define CGU_BCR1_FDRUN (1 << 0) /* Bit 0: Enable fractional dividers in AHB0_APB0 base */
#define CGU_BCR2_FDRUN (1 << 0) /* Bit 0: Enable fractional dividers in AHB0_APB1 base */
#define CGU_BCR3_FDRUN (1 << 0) /* Bit 0: Enable fractional dividers in AHB0_APB2 base */
#define CGU_BCR7_FDRUN (1 << 0) /* Bit 0: Enable fractional dividers in CLK1024FS */
#define CGU_BCR_FDRUN (1 << 0) /* Bit 0: Enable fractional dividers */
/* Fractional divider register 0 to 23 FDC0 to FDC23 (except FDC17) addresses 0x13004518 to 0x13004574 */

17
arch/arm/src/lpc313x/lpc313x_cgudrvr.h
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@ -58,6 +58,7 @@
/* Clock ID ranges (see enum lpc313x_clockid_e) *************************************************/
#define CLKID_FIRST CLKID_APB0CLK
#define CLKID_SYSBASE_FIRST CLKID_APB0CLK /* Domain 0: SYS_BASE */
#define CLKID_SYSBASE_LAST CLKID_INTCCLK
#define _D0B(id) _RBIT(id,CLKID_SYSBASE_FIRST)
@ -105,11 +106,13 @@
#define CLKID_SYSCLKO_FIRST CLKID_SYSCLKO /* Domain 11: SYSCLKO_BASE */
#define CLKID_SYSCLKO_LAST CLKID_SYSCLKO
#define _D11B(id) _RBIT(id,CLKID_SYSCLKO_FIRST)
#define CLKID_LAST CLKID_SYSCLKO
#define CGU_NDOMAINS 12 /* The number of clock domains */
#define CLKID_INVALIDCLK -1 /* Indicates and invalid clock ID */
#define DOMAINID_INVALID -1 /* Indicates an invalid domain ID */
#define ESRNDX_INVALID -1 /* Indicates an invalid ESR register index */
#define BCRNDX_INVALID -1 /* Indicates an invalid BCR register index */
/* There are 24 fractional dividers, indexed 0 to 23. The following definitions
* provide (1) the number of fractional dividers available for each base frequency,
@ -167,7 +170,7 @@
#define FRACDIV_BASE11_CNT 0 /* No fractional divider available */
#define FDCNDX_INVALID -1 /* Indicates an invalid fractional
#define FDCNDX_INVALID -1 /* Indicates an invalid fractional
* divider index */
/************************************************************************
@ -563,6 +566,18 @@ EXTERN enum lpc313x_domainid_e lpc313x_clkdomain(enum lpc313x_clockid_e clkid);
EXTERN int lp313x_esrndx(enum lpc313x_clockid_e clkid);
/************************************************************************
* Name: lp313x_bcrndx
*
* Description:
* Only 5 of the 12 domains have an associated BCR register. This
* function returns the index to the associated BCR register (if any)
* or BCRNDX_INVALID otherwise.
*
************************************************************************/
EXTERN int lp313x_bcrndx(enum lpc313x_domainid_e dmnid);
/************************************************************************
* Name: lpc313x_fdcndx
*

4
arch/arm/src/lpc313x/lpc313x_pllconfig.c
View File

@ -98,7 +98,7 @@ lpc313x_switchdomains(const struct lpc313x_pllconfig_s * const cfg)
{
/* Yes.. switch reference clock in to FFAST */
lpc313x_selectfreqin(i, CGU_FS_FFAST);
lpc313x_selectfreqin((enum lpc313x_domainid_e)i, CGU_FS_FFAST);
/* Add the domain to the set to be restored after the PLL is configured */
@ -135,7 +135,7 @@ lpc313x_restoredomains(const struct lpc313x_pllconfig_s * const cfg,
{
/* Switch input reference clock to newly configured HPLL */
lpc313x_selectfreqin(i, finsel);
lpc313x_selectfreqin((enum lpc313x_domainid_e)i, finsel);
}
}
}

2
configs/ea3131/src/ea3131_internal.h
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@ -78,7 +78,7 @@
* Name: lpc313x_meminitialize
*
* Description:
* Initialize external memory resources
* Initialize external memory resources (sram, sdram, nand, nor, etc.)
*
************************************************************************************/

2
configs/ea3131/src/up_mem.c
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@ -296,7 +296,7 @@ static void lpc313x_sdraminitialize(void)
* Name: lpc313x_meminitialize
*
* Description:
* Initialize memory
* Initialize external memory resources (sram, sdram, nand, nor, etc.)
*
****************************************************************************/