STM32L15X UART, DMA, and heap initialization support
This commit is contained in:
Gregory Nutt
parent
5d80dfd129
commit
63679d05a6
@ -4739,4 +4739,6 @@
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More updates for the STM32L152 (2013-5-19).
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* configs/stm32ldiscovey: Configuration for the STM32L-Discovery board.
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Still does not build on initial check-in (2013-5-19)
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* STM32L15X: Add DMA and UART start. Correctly initialize the heap
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(2013-5-19).
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@ -269,7 +269,7 @@
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/* DMA channel number of data register */
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#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
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#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
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#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
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/* DMA Channel mapping. Each DMA channel has a mapping to several possible
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* sources/sinks of data. The requests from peripherals assigned to a channel
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@ -295,7 +295,70 @@
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#define STM32_DMA2_CHAN4 (10)
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#define STM32_DMA2_CHAN5 (11)
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#if defined(CONFIG_STM32_STM32F10XX)
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#if defined(CONFIG_STM32_STM32L15XX)
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# define DMACHAN_ADC1 STM32_DMA1_CHAN1
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# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1
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# define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1
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# define DMACHAN_SPI1_RX STM32_DMA1_CHAN2
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# define DMACHAN_USART3_TX STM32_DMA1_CHAN2
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# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2
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# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2
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# define DMACHAN_TIM6_UP STM32_DMA1_CHAN2
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# define DMACHAN_DAC_CHAN1 STM32_DMA1_CHAN2
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# define DMACHAN_SPI1_TX STM32_DMA1_CHAN3
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# define DMACHAN_USART3_RX STM32_DMA1_CHAN3
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# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3
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# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3
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# define DMACHAN_TIM7_UP STM32_DMA1_CHAN3
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# define DMACHAN_DAC_CHAN2 STM32_DMA1_CHAN3
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# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4
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# define DMACHAN_USART1_TX STM32_DMA1_CHAN4
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# define DMACHAN_I2C2_TX STM32_DMA1_CHAN4
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# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4
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# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5
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# define DMACHAN_USART1_RX STM32_DMA1_CHAN5
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# define DMACHAN_I2C2_RX STM32_DMA1_CHAN5
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# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5
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# define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5
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# define DMACHAN_USART2_RX STM32_DMA1_CHAN6
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# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6
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# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6
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# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6
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# define DMACHAN_USART2_TX STM32_DMA1_CHAN7
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# define DMACHAN_I2C1_RX STM32_DMA1_CHAN7
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# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7
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# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7
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# define DMACHAN_TIM4_UP STM32_DMA1_CHAN7
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# define DMACHAN_SPI3_RX STM32_DMA2_CHAN1
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# define DMACHAN_USART5_TX STM32_DMA2_CHAN1
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# define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1
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# define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1
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# define DMACHAN_TIM5_COM STM32_DMA2_CHAN1
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# define DMACHAN_SPI3_TX STM32_DMA2_CHAN2
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# define DMACHAN_USART5_RX STM32_DMA2_CHAN2
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# define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2
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# define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
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# define DMACHAN_UART4_RX STM32_DMA2_CHAN3
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# define DMACHAN_AES_OUT STM32_DMA2_CHAN3
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# define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4
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# define DMACHAN_SDIO STM32_DMA2_CHAN4
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# define DMACHAN_UART4_TX STM32_DMA2_CHAN5
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# define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5
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# define DMACHAN_AES_IN STM32_DMA2_CHAN5
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#elif defined(CONFIG_STM32_STM32F10XX)
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# define DMACHAN_ADC1 STM32_DMA1_CHAN1
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# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1
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@ -353,7 +416,6 @@
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# define DMACHAN_I2S3_TX STM32_DMA2_CHAN2
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# define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2
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# define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
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# define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
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# define DMACHAN_TIM8_TRIG STM32_DMA2_CHAN2
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# define DMACHAN_TIM8_COM STM32_DMA2_CHAN2
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221
arch/arm/src/stm32/chip/stm32l15xxx_uart.h
Normal file
221
arch/arm/src/stm32/chip/stm32l15xxx_uart.h
Normal file
@ -0,0 +1,221 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32l15xxx_uart.h
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* For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based
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* 32-bit MCUs
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32L15XXX_UART_H
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#define __ARCH_ARM_STC_STM32_CHIP_STM32L15XXX_UART_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
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#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
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#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
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#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
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#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
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#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
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#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
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/* Register Addresses ***************************************************************/
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#if STM32_NUSART > 0
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# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
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# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
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#endif
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#if STM32_NUSART > 1
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# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
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# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
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#endif
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#if STM32_NUSART > 2
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# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
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# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
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#endif
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#if STM32_NUSART > 3
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# define STM32_USART4_SR (STM32_USART4_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART4_DR (STM32_USART4_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART4_BRR (STM32_USART4_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART4_CR1 (STM32_USART4_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART4_CR2 (STM32_USART4_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART4_CR3 (STM32_USART4_BASE+STM32_USART_CR3_OFFSET)
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#endif
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#if STM32_NUSART > 4
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# define STM32_USART5_SR (STM32_USART5_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART5_DR (STM32_USART5_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART5_BRR (STM32_USART5_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART5_CR1 (STM32_USART5_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART5_CR2 (STM32_USART5_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART5_CR3 (STM32_USART5_BASE+STM32_USART_CR3_OFFSET)
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#endif
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/* Register Bitfield Definitions ****************************************************/
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/* Status register */
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#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
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#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
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#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
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#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
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#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
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#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
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#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
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#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
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#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
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#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
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#define USART_SR_ALLBITS (0x03ff)
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#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
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/* Data register */
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#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
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#define USART_DR_MASK (0x1ff << USART_DR_SHIFT)
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/* Baud Rate Register */
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#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
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#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
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#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
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#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
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/* Control register 1 */
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#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
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#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
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#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
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#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
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#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
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#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
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#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
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#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
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#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
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#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
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#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
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#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
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#define USART_CR1_M (1 << 12) /* Bit 12: word length */
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#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
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#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
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#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
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/* Control register 2 */
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#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
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#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
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#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
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#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
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#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
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#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
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#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
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#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
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#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
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#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
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# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
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# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
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# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
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# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
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#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
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/* Control register 3 */
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#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
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#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
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#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
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#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
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#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
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#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
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#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
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#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
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#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
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#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
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#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
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#define USART_CR1_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
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/* Guard time and prescaler register */
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#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
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#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
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#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
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#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
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/* Compatibility definitions ********************************************************/
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/* L15 Transmit/Read registers */
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#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */
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#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32L15XXX_UART_H */
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@ -1,6 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32l15xxx_vectors.h
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* For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based 32-bit MCUs
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* For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based
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* 32-bit MCUs
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -92,12 +92,37 @@
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# undef CONFIG_STM32_FSMC_SRAM
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#endif
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|
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/* For the STM312F10xxx family, all internal SRAM is in one contiguous block
|
||||
* starting at g_idle_topstack and extending through CONFIG_DRAM_END (my apologies for
|
||||
* the bad naming). In addition, external FSMC SRAM may be available.
|
||||
/* The STM32L15xxx family has only internal SRAM. The heap is in one contiguous
|
||||
* block starting at g_idle_topstack and extending through CONFIG_DRAM_END.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX)
|
||||
#if defined(CONFIG_STM32_STM32L15XX)
|
||||
|
||||
/* Set the end of system SRAM */
|
||||
|
||||
# define SRAM1_END CONFIG_DRAM_END
|
||||
|
||||
/* There is no FSMC (Other EnergyLite STM32's do have an FSMC, but not the STM32L15X */
|
||||
|
||||
# undef CONFIG_STM32_FSMC_SRAM
|
||||
|
||||
/* The STM32L EnergyLite family has no CCM SRAM */
|
||||
|
||||
# undef CONFIG_STM32_CCMEXCLUDE
|
||||
# define CONFIG_STM32_CCMEXCLUDE 1
|
||||
|
||||
/* Only one memory region can be support (internal SRAM) */
|
||||
|
||||
# if CONFIG_MM_REGIONS > 1
|
||||
# error "CONFIG_MM_REGIONS > 1. The STM32L15X has only one memory region."
|
||||
# endif
|
||||
|
||||
/* For the STM312F10xxx family, all internal SRAM is in one contiguous block
|
||||
* starting at g_idle_topstack and extending through CONFIG_DRAM_END (my apologies
|
||||
* for the bad naming). In addition, external FSMC SRAM may be available.
|
||||
*/
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F10XX)
|
||||
|
||||
/* Set the end of system SRAM */
|
||||
|
||||
|
||||
@ -71,7 +71,8 @@
|
||||
* channels.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
|
||||
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX)
|
||||
# include "stm32f10xxx_dma.c"
|
||||
#elif defined(CONFIG_STM32_STM32F20XX)
|
||||
# include "stm32f20xxx_dma.c"
|
||||
|
||||
@ -47,7 +47,8 @@
|
||||
|
||||
/* Include the correct DMA register definitions for this STM32 family */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
|
||||
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX)
|
||||
# include "chip/stm32f10xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F20XX)
|
||||
# include "chip/stm32f20xxx_dma.h"
|
||||
@ -61,7 +62,8 @@
|
||||
* DMA callback function (see dma_callback_t).
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
|
||||
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX)
|
||||
# define DMA_STATUS_FEIF 0 /* (Not available in F1) */
|
||||
# define DMA_STATUS_DMEIF 0 /* (Not available in F1) */
|
||||
# define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */
|
||||
@ -103,7 +105,8 @@ typedef FAR void *DMA_HANDLE;
|
||||
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
|
||||
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX)
|
||||
struct stm32_dmaregs_s
|
||||
{
|
||||
uint32_t isr;
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_uart.h
|
||||
*
|
||||
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2012-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -44,7 +44,9 @@
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX)
|
||||
#if defined(CONFIG_STM32_STM32L15XX)
|
||||
# include "chip/stm32l15xxx_uart.h"
|
||||
#elif defined(CONFIG_STM32_STM32F10XX)
|
||||
# include "chip/stm32f10xxx_uart.h"
|
||||
#elif defined(CONFIG_STM32_STM32F20XX)
|
||||
# include "chip/stm32f20xxx_uart.h"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user