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xtensa: Replace the implementation of up_cpu_pause

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Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commit is contained in:
hujun5 2024-10-07 14:48:39 +08:00 committed by Xiang Xiao
parent fbed4ece2c
commit 6392d5a6b3
2 changed files with 46 additions and 4 deletions
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27
arch/xtensa/src/esp32/esp32_spiram.c
View File

@ -74,6 +74,26 @@
static bool spiram_inited = false; static bool spiram_inited = false;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: pause_cpu_handler
****************************************************************************/
#ifdef CONFIG_SMP
static volatile bool g_cpu_wait = true;
static volatile bool g_cpu_pause = false;
static int pause_cpu_handler(FAR void *cookie)
{
g_cpu_pause = true;
while (g_cpu_wait);
return OK;
}
#endif
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
@ -183,7 +203,10 @@ unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid,
if (os_ready) if (os_ready)
{ {
cpu_to_stop = this_cpu() == 1 ? 0 : 1; cpu_to_stop = this_cpu() == 1 ? 0 : 1;
up_cpu_pause(cpu_to_stop); g_cpu_wait = true;
g_cpu_pause = false;
nxsched_smp_call_single(cpu_to_stop, pause_cpu_handler, NULL, false);
while (!g_cpu_pause);
} }
spi_disable_cache(1); spi_disable_cache(1);
@ -221,7 +244,7 @@ unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid,
if (os_ready) if (os_ready)
{ {
up_cpu_resume(cpu_to_stop); g_cpu_wait = false;
} }
#endif #endif

23
arch/xtensa/src/esp32s3/esp32s3_spiram.c
View File

@ -263,6 +263,22 @@ static int IRAM_ATTR esp_mmu_map_region(uint32_t vaddr, uint32_t paddr,
return ret; return ret;
} }
/****************************************************************************
* Name: pause_cpu_handler
****************************************************************************/
#ifdef CONFIG_SMP
static volatile bool g_cpu_wait = true;
static volatile bool g_cpu_pause = false;
static int pause_cpu_handler(FAR void *cookie)
{
g_cpu_pause = true;
while (g_cpu_wait);
return OK;
}
#endif
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
@ -309,7 +325,10 @@ int IRAM_ATTR cache_dbus_mmu_map(int vaddr, int paddr, int num)
if (smp_start) if (smp_start)
{ {
up_cpu_pause(other_cpu); g_cpu_wait = true;
g_cpu_pause = false;
nxsched_smp_call_single(other_cpu, pause_cpu_handler, NULL, false);
while (!g_cpu_pause);
} }
cache_state[other_cpu] = cache_suspend_dcache(); cache_state[other_cpu] = cache_suspend_dcache();
@ -336,7 +355,7 @@ int IRAM_ATTR cache_dbus_mmu_map(int vaddr, int paddr, int num)
cache_resume_dcache(cache_state[other_cpu]); cache_resume_dcache(cache_state[other_cpu]);
if (smp_start) if (smp_start)
{ {
up_cpu_resume(other_cpu); g_cpu_wait = false;
} }
#endif #endif