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Move enabling of GPIO peripherals form UART setup to clockconfig. This is not a UART function. It is needed by all periphrals.

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This commit is contained in:
Gregory Nutt 2017-04-17 17:20:55 -06:00
parent 8b157b034d
commit 639bf31eb4
2 changed files with 8 additions and 8 deletions
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8
arch/arm/src/stm32f0/stm32f0_clockconfig.c
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@ -111,4 +111,12 @@ void stm32f0_clockconfig(void)
regval |= RCC_CFGR_SW_PLL;
putreg32(regval, STM32F0_RCC_CFGR);
while ((getreg32(STM32F0_RCC_CFGR) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL);
/* Enable basic peripheral support */
/* Enable all GPIO modules */
regval = getreg32(STM32F0_RCC_AHBENR);
regval |= RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPAEN |\
RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPAEN;
putreg32(regval, STM32F0_RCC_AHBENR);
}

8
arch/arm/src/stm32f0/stm32f0_lowputc.c
View File

@ -297,7 +297,6 @@ void stm32f0_lowsetup(void)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
uint32_t cr;
#endif
uint32_t clken;
#if defined(HAVE_CONSOLE)
/* Enable USART APB1/2 clock */
@ -305,13 +304,6 @@ void stm32f0_lowsetup(void)
modifyreg32(STM32F0_CONSOLE_APBREG, 0, STM32F0_CONSOLE_APBEN);
#endif
/* Enable all GPIO modules */
clken = getreg32(STM32F0_RCC_AHBENR);
clken |= RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPAEN |\
RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPAEN;
putreg32(clken, STM32F0_RCC_AHBENR);
#ifdef STM32F0_CONSOLE_TX
stm32f0_configgpio(STM32F0_CONSOLE_TX);
#endif