From 639f77341ac7521b026bdee941d5062d125d90d3 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Sat, 25 Nov 2017 06:39:44 -0600 Subject: [PATCH] arch/arm/src/xmc4: Remove hard-coded values in clock configuration. USB will be fixed later. --- arch/arm/src/xmc4/xmc4_clockconfig.c | 48 +++++++++++++++------ configs/xmc4500-relax/include/board.h | 62 ++++++++++++++++++++++++++- 2 files changed, 96 insertions(+), 14 deletions(-) diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index 87ecba768e..2f39ce7096 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -103,13 +103,7 @@ #define PLL_K2DIV_120MHZ (VCO / 120000000) #define CLKSET_VALUE (0x00000000) -#define SYSCLKCR_VALUE (0x00010001) -#define CPUCLKCR_VALUE (0x00000000) -#define CCUCLKCR_VALUE (0x00000000) -#define WDTCLKCR_VALUE (0x00000000) -#define EBUCLKCR_VALUE (0x00000003) #define USBCLKCR_VALUE (0x00010000) -#define EXTCLKCR_VALUE (0x01200003) #if BOARD_PBDIV == 1 # define PBCLKCR_VALUE SCU_PBCLKCR_PBDIV_FCPU @@ -391,14 +385,44 @@ void xmc4_clock_configure(void) /* Before scaling to final frequency we need to setup the clock dividers */ - putreg32(SYSCLKCR_VALUE, XMC4_SCU_SYSCLKCR); + /* Setup fSYS clock */ + + regval = (BOARD_ENABLE_PLL << SCU_SYSCLKCR_SYSSEL); + regval |= SCU_SYSCLKCR_SYSDIV(BOARD_SYSDIV); + putreg32(regval, XMC4_SCU_SYSCLKCR); + + /* Setup peripheral clock divider */ + putreg32(PBCLKCR_VALUE, XMC4_SCU_PBCLKCR); - putreg32(CPUCLKCR_VALUE, XMC4_SCU_CPUCLKCR); - putreg32(CCUCLKCR_VALUE, XMC4_SCU_CCUCLKCR); - putreg32(WDTCLKCR_VALUE, XMC4_SCU_WDTCLKCR); - putreg32(EBUCLKCR_VALUE, XMC4_SCU_EBUCLKCR); + + /* Setup fCPU clock */ + + putreg32(BOARD_CPUDIV_ENABLE, XMC4_SCU_CPUCLKCR); + + /* Setup CCU clock */ + + putreg32(BOARD_CCUDIV_ENABLE, XMC4_SCU_CCUCLKCR); + + /* Setup Watchdog clock */ + + regval = (BOARD_WDT_SOURCE << SCU_WDTCLKCR_WDTSEL_SHIFT); + regval |= SCU_WDTCLKCR_WDTDIV(BOARD_WDTDIV); + putreg32(regval, XMC4_SCU_WDTCLKCR); + + /* Setup EBU clock */ + + regval = SCU_EBUCLKCR_EBUDIV(BOARD_EBUDIV); + putreg32(regval, XMC4_SCU_EBUCLKCR); + + /* Setup USB clock */ + putreg32(USBCLKCR_VALUE | USB_DIV, XMC4_SCU_USBCLKCR); - putreg32(EXTCLKCR_VALUE, XMC4_SCU_EXTCLKCR); + + /* Setup EXT */ + + regval = (BOARD_EXT_SOURCE << SCU_EXTCLKCR_ECKSEL_SHIFT); + regval |= SCU_EXTCLKCR_ECKDIV(BOARD_EXTDIV); + putreg32(regval, XMC4_SCU_EXTCLKCR); #if BOARD_ENABLE_PLL /* PLL frequency stepping...*/ diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h index af06f3ba3c..74eba56506 100644 --- a/configs/xmc4500-relax/include/board.h +++ b/configs/xmc4500-relax/include/board.h @@ -51,12 +51,26 @@ * Pre-processor Definitions ************************************************************************************/ +/* Clocking *************************************************************************/ + /* The maximum frequency for the XMC4500 is 120MHz. */ #undef BOARD_FCPU_144MHZ -#define BOARD_FCPU_120MHZ 1 +#define BOARD_FCPU_120MHZ 1 -/* Clocking *************************************************************************/ +/* Watchdog clock source selection */ + +#define WDT_CLKSRC_FOFI 0 /* fOFI clock */ +#define WDT_CLKSRC_FSTDY 1 /* fSTDY clock */ +#define WDT_CLKSRC_FPLL 2 /* fPLL clock */ + +/* External Clock source selection */ + +#define EXT_CLKSRC_FSYS 0 /* fSYS clock */ +#define EXT_CLKSRC_FUSB 2 /* fUSB clock divided by ECKDIV */ +#define EXT_CLKSRC_FPLL 3 /* fPLL clock divided by ECKDIV */ + +/* Factory Calibration */ #undef BOARD_FOFI_CALIBRATION /* Enable factory calibration */ @@ -117,6 +131,28 @@ # define BOARD_CPUDIV_ENABLE 1 /* Enable PLL dive by 2 for fCPU */ # define BOARD_CPU_FREQUENCY 144000000 +/* CCU frequency may be divided down from system frequency */ + +# define BOARD_CCUDIV_ENABLE 1 /* Enable PLL div by 2 */ +# define BOARD_CCU_FREQUENCY 144000000 + +/* Watchdog clock settings */ + +# define BOARD_WDT_SOURCE WDT_CLKSRC_FOFI +# define BOARD_WDTDIV 1 +# define BOARD_WDT_FREQUENCY 24000000 + +/* EBU frequency may be divided down from system frequency */ + +# define BOARD_EBUDIV 2 /* fSYS / 2 */ +# define BOARD_EBU_FREQUENCY 72000000 + +/* EXT clock settings */ + +# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL +# define BOARD_EXTDIV 289 /* REVISIT */ +# define BOARD_EXT_FREQUENCY 498270 /* REVISIT */ + /* The peripheral clock, fPERIPH, derives from fCPU with no division */ # define BOARD_PBDIV 1 /* No division */ @@ -170,6 +206,28 @@ # define BOARD_CPUDIV_ENABLE 0 /* No divison */ # define BOARD_CPU_FREQUENCY 120000000 +/* CCU frequency may be divided down from system frequency */ + +# define BOARD_CCUDIV_ENABLE 0 /* No divison */ +# define BOARD_CCU_FREQUENCY 120000000 + +/* Watchdog clock setting */ + +# define BOARD_WDT_SOURCE WDT_CLKSRC_FOFI +# define BOARD_WDTDIV 1 +# define BOARD_WDT_FREQUENCY 24000000 + +/* EBU frequency may be divided down from system frequency */ + +# define BOARD_EBUDIV 2 /* fSYS/2 */ +# define BOARD_EBU_FREQUENCY 60000000 + +/* EXT clock settings */ + +# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL +# define BOARD_EXTDIV 289 /* REVISIT */ +# define BOARD_EXT_FREQUENCY 415225 /* REVISIT */ + /* The peripheral clock, fPERIPH, derives from fCPU with no division */ # define BOARD_PBDIV 1 /* No division */