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stm32h7/rcc: make VOS0 configurable from board.h also for stm32h7x7xx

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Over-drive can be forced to a given state by adding define to the
board.h configuration file:

   #define STM32_VOS_OVERDRIVE 1 - force over-drive enabled,
   #define STM32_VOS_OVERDRIVE 0 - force over-drive disabled,
   #undef STM32_VOS_OVERDRIVE    - autoselect over-drive by the default RCC logic
This commit is contained in:
raiden00pl 2023-04-14 09:33:04 +02:00 committed by David Sidrane
parent 876b7a5e8e
commit 642358e68f
1 changed files with 44 additions and 21 deletions
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65
arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
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@ -98,6 +98,34 @@
# define USE_PLL3 # define USE_PLL3
#endif #endif
/* Over-drive is supported only for Voltage output scale 1 mode.
* It is required when SYSCLK frequency is over 400 MHz or it can be forced
* to a given state by adding define to the board.h configuration file:
*
* #define STM32_VOS_OVERDRIVE 1 - force over-drive enabled,
* #define STM32_VOS_OVERDRIVE 0 - force over-drive disabled,
* #undef STM32_VOS_OVERDRIVE - autoselect over-drive by logic below
*
* Boosting the core voltage can be a workaround solution to problems with
* poor board signal integration for high-speed digital interfaces like ULPI.
* Higher voltage means faster clock signal edges which may be sufficient to
* synchronise the high-speed clock and data.
*/
#ifndef STM32_VOS_OVERDRIVE
# if (STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1) && \
(STM32_SYSCLK_FREQUENCY > 400000000)
# define STM32_VOS_OVERDRIVE 1
# else
# define STM32_VOS_OVERDRIVE 0
# endif
#else
# if (STM32_VOS_OVERDRIVE == 1) && \
(STM32_PWR_VOS_SCALE != PWR_D3CR_VOS_SCALE_1)
# error Over-drive can be selected only when VOS1 is configured
# endif
#endif
/**************************************************************************** /****************************************************************************
* Private Data * Private Data
****************************************************************************/ ****************************************************************************/
@ -855,30 +883,25 @@ void stm32_stdclockconfig(void)
{ {
} }
/* Over-drive is needed if #if STM32_VOS_OVERDRIVE && (STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1)
* - Voltage output scale 1 mode is selected and SYSCLK frequency is /* Over-drive support for VOS1 */
* over 400 MHz.
*/
if ((STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1) && /* Enable System configuration controller clock to Enable ODEN */
STM32_SYSCLK_FREQUENCY > 400000000)
regval = getreg32(STM32_RCC_APB4ENR);
regval |= RCC_APB4ENR_SYSCFGEN;
putreg32(regval, STM32_RCC_APB4ENR);
/* Enable Overdrive */
regval = getreg32(STM32_SYSCFG_PWRCR);
regval |= SYSCFG_PWRCR_ODEN;
putreg32(regval, STM32_SYSCFG_PWRCR);
while ((getreg32(STM32_PWR_D3CR) & STM32_PWR_D3CR_VOSRDY) == 0)
{ {
/* Enable System configuration controller clock to Enable ODEN */
regval = getreg32(STM32_RCC_APB4ENR);
regval |= RCC_APB4ENR_SYSCFGEN;
putreg32(regval, STM32_RCC_APB4ENR);
/* Enable Overdrive to extend the clock frequency up to 480 MHz. */
regval = getreg32(STM32_SYSCFG_PWRCR);
regval |= SYSCFG_PWRCR_ODEN;
putreg32(regval, STM32_SYSCFG_PWRCR);
while ((getreg32(STM32_PWR_D3CR) & STM32_PWR_D3CR_VOSRDY) == 0)
{
}
} }
#endif
/* Configure FLASH wait states */ /* Configure FLASH wait states */