procfs：add xtensa cpuinfo
Signed-off-by: liaoao <liaoao@xiaomi.com>
This commit is contained in:
liaoao
Xiang Xiao
parent
db53c7abcf
commit
6424b5322f
@ -128,6 +128,7 @@ config ARCH_X86_64
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config ARCH_XTENSA
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bool "Xtensa"
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select ARCH_HAVE_BACKTRACE
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select ARCH_HAVE_CPUINFO
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select ARCH_HAVE_INTERRUPTSTACK
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select ARCH_HAVE_STACKCHECK
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select ARCH_HAVE_CUSTOMOPT
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@ -27,14 +27,15 @@ HEAD_ASRC += xtensa_int_handlers.S xtensa_user_handler.S
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CMN_ASRCS = xtensa_context.S xtensa_cpuint.S xtensa_panic.S
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CMN_CSRCS = xtensa_assert.c xtensa_cpenable.c xtensa_createstack.c
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CMN_CSRCS += xtensa_exit.c xtensa_getintstack.c xtensa_initialize.c
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CMN_CSRCS += xtensa_initialstate.c xtensa_irqdispatch.c xtensa_lowputs.c
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CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c
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CMN_CSRCS += xtensa_mdelay.c xtensa_nputs.c xtensa_releasestack.c
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CMN_CSRCS += xtensa_registerdump.c xtensa_sigdeliver.c xtensa_switchcontext.c
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CMN_CSRCS += xtensa_swint.c xtensa_stackframe.c xtensa_saveusercontext.c
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CMN_CSRCS += xtensa_schedsigaction.c xtensa_udelay.c xtensa_usestack.c
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CMN_CSRCS = xtensa_assert.c xtensa_cpenable.c xtensa_cpuinfo.c
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CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_getintstack.c
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CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_irqdispatch.c
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CMN_CSRCS += xtensa_lowputs.c xtensa_modifyreg8.c xtensa_modifyreg16.c
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CMN_CSRCS += xtensa_modifyreg32.c xtensa_mdelay.c xtensa_nputs.c xtensa_perf.c
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CMN_CSRCS += xtensa_releasestack.c xtensa_registerdump.c xtensa_sigdeliver.c
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CMN_CSRCS += xtensa_switchcontext.c xtensa_swint.c xtensa_stackframe.c
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CMN_CSRCS += xtensa_saveusercontext.c xtensa_schedsigaction.c xtensa_udelay.c
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CMN_CSRCS += xtensa_usestack.c
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# Configuration-dependent common Xtensa files
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232
arch/xtensa/src/common/xtensa_cpuinfo.c
Normal file
232
arch/xtensa/src/common/xtensa_cpuinfo.c
Normal file
@ -0,0 +1,232 @@
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/****************************************************************************
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* arch/xtensa/src/common/xtensa_cpuinfo.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/arch.h>
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#include <nuttx/config.h>
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#include <nuttx/fs/procfs.h>
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#include <arch/xtensa/xtensa_specregs.h>
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#include <sys/types.h>
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#if defined(CONFIG_FS_PROCFS) && !defined(CONFIG_FS_PROCFS_EXCLUDE_CPUINFO)
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: xtensa_getconfig0
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*
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* Description:
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* Get the value of the CONFIGID0 register.
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*
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****************************************************************************/
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static inline uint32_t xtensa_getconfig0(void)
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{
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uint32_t reg;
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__asm__ __volatile__
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(
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"rsr %0, CONFIGID0" : "=r"(reg)
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);
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return reg;
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}
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/****************************************************************************
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* Name: xtensa_getconfig1
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*
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* Description:
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* Get the value of the CONFIGID1 register.
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*
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****************************************************************************/
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static inline uint32_t xtensa_getconfig1(void)
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{
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uint32_t reg;
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__asm__ __volatile__
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(
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"rsr %0, CONFIGID1" : "=r"(reg)
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);
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return reg;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* name: up_show_cpuinfo
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****************************************************************************/
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ssize_t up_show_cpuinfo(FAR char *buf, size_t buf_size, off_t file_off)
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{
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procfs_sprintf(buf, buf_size, &file_off,
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"CPU count\t: %u\n"
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"vendor_id\t: Tensilica\n"
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"model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n",
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CONFIG_SMP_NCPUS);
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procfs_sprintf(buf, buf_size, &file_off,
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"core ID\t\t: " XCHAL_CORE_ID "\n"
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"build ID\t: 0x%x\n"
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"config ID\t: %08" PRIx32 ":%08" PRIx32 "\n",
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XCHAL_BUILD_UNIQUE_ID,
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xtensa_getconfig0(), xtensa_getconfig1());
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procfs_sprintf(buf, buf_size, &file_off,
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"byte order\t: %s\n"
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"cpu MHz\t\t: %lu.%02lu\n"
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"bogomips\t: %u.%02u\n",
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XCHAL_HAVE_BE ? "big" : "little",
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up_perf_getfreq() / 1000000,
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(up_perf_getfreq() / 10000) % 100,
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(CONFIG_BOARD_LOOPSPERMSEC / 1000),
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(CONFIG_BOARD_LOOPSPERMSEC / 10) % 100);
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/* Features */
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procfs_sprintf(buf, buf_size, &file_off, "flags\t\t: "
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#if XCHAL_HAVE_NMI
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"nmi "
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#endif
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#if XCHAL_HAVE_DEBUG
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"debug "
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# if XCHAL_HAVE_OCD
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"ocd "
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# endif
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#endif
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#if XCHAL_HAVE_DENSITY
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"density "
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#endif
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#if XCHAL_HAVE_BOOLEANS
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"boolean "
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#endif
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#if XCHAL_HAVE_LOOPS
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"loop "
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#endif
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#if XCHAL_HAVE_NSA
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"nsa "
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#endif
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#if XCHAL_HAVE_MINMAX
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"minmax "
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#endif
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#if XCHAL_HAVE_SEXT
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"sext "
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#endif
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#if XCHAL_HAVE_CLAMPS
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"clamps "
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#endif
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#if XCHAL_HAVE_MAC16
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"mac16 "
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#endif
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#if XCHAL_HAVE_MUL16
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"mul16 "
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#endif
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#if XCHAL_HAVE_MUL32
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"mul32 "
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#endif
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#if XCHAL_HAVE_MUL32_HIGH
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"mul32h "
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#endif
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#if XCHAL_HAVE_FP
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"fpu "
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#endif
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#if XCHAL_HAVE_S32C1I
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"s32c1i "
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#endif
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#ifdef XCHAL_HAVE_EXCLUSIVE
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# if XCHAL_HAVE_EXCLUSIVE
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"exclusive "
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# endif
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#endif
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"\n");
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/* Registers */
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procfs_sprintf(buf, buf_size, &file_off,
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"physical aregs\t: %d\n"
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"misc regs\t: %d\n"
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"ibreak\t\t: %d\n"
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"dbreak\t\t: %d\n",
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XCHAL_NUM_AREGS,
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XCHAL_NUM_MISC_REGS,
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XCHAL_NUM_IBREAK,
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XCHAL_NUM_DBREAK);
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/* Interrupt */
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procfs_sprintf(buf, buf_size, &file_off,
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"num ints\t: %d\n"
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"ext ints\t: %d\n"
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"int levels\t: %d\n"
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"timers\t\t: %d\n"
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"debug level\t: %d\n",
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XCHAL_NUM_INTERRUPTS,
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XCHAL_NUM_EXTINTERRUPTS,
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XCHAL_NUM_INTLEVELS,
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XCHAL_NUM_TIMERS,
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XCHAL_DEBUGLEVEL);
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/* Cache */
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#ifdef CONFIG_XTENSA_ICACHE
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procfs_sprintf(buf, buf_size, &file_off,
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"icache line size: %d\n"
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"icache ways\t: %d\n"
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"icache size\t: %d\n"
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"icache flags\t: "
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#if XCHAL_ICACHE_LINE_LOCKABLE
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"lock "
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#endif
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"\n",
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XCHAL_ICACHE_LINESIZE,
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XCHAL_ICACHE_WAYS,
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XCHAL_ICACHE_SIZE);
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#endif
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#ifdef CONFIG_XTENSA_DCACHE
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procfs_sprintf(buf, buf_size, &file_off,
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"dcache line size: %d\n"
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"dcache ways\t: %d\n"
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"dcache size\t: %d\n"
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"dcache flags\t: "
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#if XCHAL_DCACHE_IS_WRITEBACK
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"writeback "
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#endif
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#if XCHAL_DCACHE_LINE_LOCKABLE
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"lock "
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#endif
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"\n",
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XCHAL_DCACHE_LINESIZE,
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XCHAL_DCACHE_WAYS,
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XCHAL_DCACHE_SIZE);
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#endif
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return -file_off;
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}
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#endif /* CONFIG_FS_PROCFS && !CONFIG_FS_PROCFS_EXCLUDE_CPUINFO */
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